CN117479825A - Preparation method of MIM capacitor - Google Patents
Preparation method of MIM capacitor Download PDFInfo
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- CN117479825A CN117479825A CN202311307899.7A CN202311307899A CN117479825A CN 117479825 A CN117479825 A CN 117479825A CN 202311307899 A CN202311307899 A CN 202311307899A CN 117479825 A CN117479825 A CN 117479825A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 42
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 118
- 238000005530 etching Methods 0.000 claims abstract description 91
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000012495 reaction gas Substances 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000002161 passivation Methods 0.000 abstract description 10
- 229920000642 polymer Polymers 0.000 abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- 239000004065 semiconductor Substances 0.000 description 12
- 239000007789 gas Substances 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000009751 slip forming Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000036962 time dependent Effects 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- -1 silicon gallium compound Chemical class 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/88—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by patterning layers, e.g. by etching conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The application provides a preparation method of an MIM capacitor, which comprises the following steps: providing a substrate, wherein a lower electrode plate layer, an intermediate insulating layer and an upper electrode plate layer are formed on the substrate; forming a hard mask layer; executing a first etching process to etch the hard mask layer and the upper electrode plate layer with partial thickness; executing a second etching process to etch the upper electrode plate layer with the residual thickness, wherein the reaction gas involved in the second etching process comprises Cl 2 And CH (CH) 4 . The method comprises the steps of firstly executing a first etching process to remove most of the upper polar plate layer with the thickness, and then executing a second etching process to etch the rest upper polar plate layer; and introducing CH in the second etching process 4 The polymer can be continuously generated in the second etching process, and the passivation layer can be formed on the side wall of the upper electrode plate layer and the upper surface of the middle insulating layer, so that the middle insulating layer is dynamically protected from being mistakenly etched in the second etching process, and the Reliability of the MIM capacitor is improved&TDDB performance.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a preparation method of an MIM capacitor.
Background
In the BEOL MIM (Metal-Insulator-Metal) capacitor process, to increase the capacitance density of the MIM capacitor, a High-k (High-k) dielectric material is selected as a new material for the MIM capacitor insulating layer, and the High-k dielectric material is used to replace the conventional silicon nitride material as the middle insulating layer of the MIM capacitor.
To achieve MIM capacitance density of 6fF/μm 2 The thickness of the high-k insulating layer is controlled toHereinafter, in order to ensure Reliability of MIM capacitor&TDDB (Time Dependent Dielectric Breakdown, time dependent gate dielectric breakdown) performance, in the process of etching the upper plate of the MIM capacitor, needs to be stopped on the upper surface of the high-k insulating layer and to ensure that the high-k insulating layer is not erroneously etched as much as possible, which presents a significant challenge to the etching process of the upper plate of the MIM capacitor.
However, in the current process of etching the upper plate of the MIM capacitor, it is difficult to stop on the upper surface of the MIM capacitor insulating layer, and the current MIM capacitor insulating layer is always etched by mistake in the process of etching the upper plate of the MIM capacitor, which results in serious influence on the Reliability & TDDB performance of the MIM capacitor.
Disclosure of Invention
The application provides a preparation method of an MIM capacitor, which can solve the problem that an insulating layer of the MIM capacitor is always etched by mistake in the process of etching an upper polar plate of the MIM capacitor at present.
The embodiment of the application provides a preparation method of an MIM capacitor, which comprises the following steps:
providing a substrate, wherein a lower electrode plate layer, an intermediate insulating layer and an upper electrode plate layer are formed on the substrate;
forming a hard mask layer, wherein the hard mask layer covers the upper polar plate layer;
executing a first etching process to etch the hard mask layer and the upper electrode plate layer with partial thickness;
and executing a second etching process to etch the upper electrode plate layer with the residual thickness, wherein the participation reaction gas in the second etching process comprises the following components: cl 2 And CH (CH) 4 。
Optionally, in the method for manufacturing the MIM capacitor, the intermediate insulating layer is a high K dielectric layer.
Optionally, in the method for manufacturing the MIM capacitor, the thickness of the intermediate insulating layer is smaller thanAnd is greater than->
Optionally, in the preparation method of the MIM capacitor, in a process of performing a second etching process to etch the upper plate layer with the remaining thickness, etching process parameters of the upper plate layer with the remaining thickness include: the source power is 400W-1000W; the bias power is 0W-45W; the pressure of the process chamber is 5 mT-10 mT.
Optionally, in the preparation method of the MIM capacitor, cl is in a process of performing a second etching process to etch the upper plate layer with a residual thickness 2 And CH (CH) 4 The flow ratio of (2) is 3.8:1.
Optionally, in the method for manufacturing the MIM capacitor, CH 4 The flow rate of (2) is greater than 0sccm and less than or equal to 50sccm.
Optionally, in the method for manufacturing the MIM capacitor, in the process of performing the first etching process to etch the hard mask layer and the upper plate layer with a partial thickness, the partial thickness of the upper plate layer removed by etching is greater than four fifths of the total thickness of the upper plate layer.
Optionally, in the method for manufacturing the MIM capacitor, in a process of performing a first etching process to etch the hard mask layer and the upper plate layer with a partial thickness, etching process parameters of etching the upper plate layer with a partial thickness include: the source power is 0W-1000W; the bias power is 0W-500W; the pressure of the process cavity is 0 mT-20 mT; the participation reaction gas includes: cl 2 And BCl 3 。
Optionally, in the method for manufacturing the MIM capacitor, a first etching process is performed to etchIn the process of etching the hard mask layer and the upper electrode plate layer with partial thickness, cl 2 And BCl 3 The flow ratio of (2) is 1:1.
Optionally, in the method for manufacturing the MIM capacitor, an etching rate of the first etching process is greater than an etching rate of the second etching process.
The technical scheme of the application at least comprises the following advantages:
the method comprises the steps of firstly executing a first etching process to remove most of the upper polar plate layer with the thickness, and then executing a second etching process to etch the rest upper polar plate layer; and introducing CH in the second etching process 4 So that the polymer (mainly C) x H y ) Polymer C x H y The passivation layer can be formed along the sidewall epitaxy of the upper polar plate layer and on the upper surface of the middle insulating layer, and in the second etching process, the passivation layer is continuously etched by etching gas and continuously regenerated, so that the continuously formed passivation layer can dynamically protect the middle insulating layer from being mistakenly etched in the second etching process, thereby improving the Reliability of the MIM capacitor&TDDB performance.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a method of fabricating a MIM capacitor according to an embodiment of the present invention;
fig. 2-9 are schematic views of semiconductor structures in various process steps for fabricating MIM capacitors according to an embodiment of the present invention;
wherein reference numerals are as follows:
10-substrate, 20-lower plate layer, 30-intermediate insulating layer, 40-upper plate layer of residual thickness, 50-hard mask layer, 60-photoresist layer, 61-patterned photoresist layer, 70-passivation layer.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
An embodiment of the present application provides a method for manufacturing a MIM capacitor, referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a MIM capacitor according to an embodiment of the present invention, where the method for manufacturing a MIM capacitor includes:
step S10: providing a substrate, wherein a lower electrode plate layer, an intermediate insulating layer and an upper electrode plate layer are formed on the substrate;
step S20: forming a hard mask layer, wherein the hard mask layer covers the upper polar plate layer;
step S30: executing a first etching process to etch the hard mask layer and the upper electrode plate layer with partial thickness;
step S40: and executing a second etching process to etch the upper electrode plate layer with the residual thickness, wherein the participation reaction gas in the second etching process comprises the following components: cl 2 And CH (CH) 4 。
Referring to fig. 2-9, fig. 2-9 are schematic semiconductor structures at various process steps for fabricating MIM capacitors according to an embodiment of the present invention. Next, a method for manufacturing the MIM capacitor according to the embodiment of the present application will be described in detail.
First, as shown in fig. 2, fig. 2 is a schematic view of a semiconductor structure after forming an upper plate layer according to an embodiment of the present application, a substrate 10 is provided, and a lower plate layer 20, an intermediate insulating layer 30 and an upper plate layer 40 are formed on the substrate 10.
Wherein, the substrate 10 may be one of monocrystalline silicon, polycrystalline silicon and amorphous silicon, the substrate 10 may also be gallium arsenide, silicon gallium compound and the like, and the substrate 10 may also have a silicon-on-insulator or epitaxial layer structure on silicon; the substrate 10 may also be a semiconductor structure that has been formed with multiple device film layers, which are not further illustrated herein. The material and specific structure of the substrate 10 are not limited in this application.
In this embodiment, the lower plate layer 20 is a titanium nitride layer; the upper plate layer 40 is a titanium nitride layer.
Preferably, the intermediate insulating layer 30 is a high-K dielectric layer.
In the present embodiment, the intermediate insulating layer 30 is Al 2 O 3 A layer.
Further, the thickness of the intermediate insulating layer 30 is smaller thanAnd is greater than->
Next, as shown in fig. 3, fig. 3 is a schematic view of a semiconductor structure after forming a hard mask layer according to an embodiment of the present application, a hard mask layer 50 is formed, and the hard mask layer 50 covers the upper plate layer 40.
In this embodiment, the hard mask layer 50 is made of silicon nitride.
Next, as shown in fig. 4, fig. 4 is a schematic diagram of a semiconductor structure after forming a photoresist layer according to an embodiment of the present application, and a photoresist layer 60 is formed, where the photoresist layer 60 covers the hard mask layer 50.
Further, as shown in fig. 5, fig. 5 is a schematic view of a semiconductor structure after forming a patterned photoresist layer according to an embodiment of the present application, where the photoresist layer 60 is converted into a patterned photoresist layer 61 by a photolithography process such as exposure, development, etc. The patterned photoresist layer 61 opens a process window where the upper plate layer 40 needs to be etched.
Next, as shown in fig. 6, fig. 6 is a schematic view of the semiconductor structure after etching the hard mask layer according to the embodiment of the present application, and the hard mask layer 50 is etched by a wet etching process or a dry etching process using the patterned photoresist layer 61 as a mask.
Further, as shown in fig. 7, fig. 7 is a schematic view of a semiconductor structure after performing a first etching process according to an embodiment of the present application, wherein the first etching process is performed to etch the hard mask layer 50 and a portion of the thickness of the upper plate layer 40.
In this embodiment, the first etching process may be performed using a dry etching process.
Preferably, in the process of performing the first etching process to etch the hard mask layer 50 and the upper plate layer 40 with a partial thickness, the partial thickness of the upper plate layer 40 removed by etching is greater than four fifths of the total thickness of the upper plate layer 40, i.e., the partial thickness of the upper plate layer 40 removed by etching is greater than 4/5 of the total thickness of the upper plate layer 40.
Preferably, in the process of performing the first etching process to etch the hard mask layer 30 and the upper pole plate layer 40 with a partial thickness, etching process parameters of the upper pole plate layer 40 with a partial thickness include: the source power is 0W-1000W; the bias power is 0W-500W; the pressure of the process cavity is 0 mT-20 mT; the participation reaction gas includes: cl 2 And BCl 3 Wherein, cl 2 Is the main etching gas.
Specifically, during the first etching process to etch the hard mask layer 30 and the upper plate layer 40 with partial thickness, cl 2 And BCl 3 The flow ratio of (2) is 1:1.
Wherein, the reaction formula related to the first etching process comprises:
TiN+Cl*→TiCl 4 ；
BCl x +Cl*→BCl x+1 。
next, as shown in fig. 8, fig. 8 is a schematic view of a semiconductor structure after performing a second etching process in the embodiment of the present application, and the second etching process is performed to etch the remaining thickness of the upper plate layer 40, where the participating reaction gases in the second etching process include: cl 2 And CH (CH) 4 Wherein, cl 2 Is an etching gas.
In this embodiment, the second etching process may be performed using a dry etching process.
In the process of performing the second etching process to etch the remaining thickness of the upper plate layer 40, the etching process parameters of etching the remaining thickness of the upper plate layer 40 include: the source power is 400W-1000W; the bias power is 0W-45W; the pressure of the process chamber is 5 mT-10 mT.
Preferably, cl is removed during the second etching process to etch the remaining thickness of the upper plate layer 40 2 The flow rate of the water is 0 sccm-80 sccm; CH (CH) 4 The flow rate of (C) is 0sccm to 50sccm, namely Cl 2 The flow rate of (2) is greater than 0sccm and less than or equal to 80sccm; CH (CH) 4 Is greater than 0sccm andless than or equal to 50sccm.
In the present embodiment, cl 2 And CH (CH) 4 The flow ratio of (2) is 3.8:1.
Wherein, the reaction formula related to the second etching process comprises:
TiN+Cl→TiCl 4 ；
CH 4 →C x H y 。
as can be seen from the above equation, CH is introduced in the second etching process 4 Can effectively and continuously generate the polymer C in the second etching process x H y Polymer C x H y The passivation layer 70 may be formed along the sidewall extension of the upper plate layer 40 at the bottom of the patterned photoresist 61 and on the upper surface of the intermediate insulating layer 30, and in the second etching process, the passivation layer 70 is continuously etched by the etching gas and is continuously regenerated, so that the continuously etched and continuously formed passivation layer 70 may dynamically protect the intermediate insulating layer 30 from being erroneously etched in the second etching process.
Further, the etching rate of the first etching process is greater than the etching rate of the second etching process.
Finally, as shown in fig. 9, fig. 9 is a schematic diagram of the semiconductor structure after removing the patterned photoresist layer and the hard mask layer according to the embodiment of the present application, and removing the patterned photoresist layer 61 and the hard mask layer 30.
In this embodiment, an ashing process may be used to remove the patterned photoresist layer 61; a wet etch process may be used to remove the hard mask layer 30 at the bottom of the patterned photoresist layer 61.
In the present application, the first etching process is performed to remove most of the upper plate layer 40, and then the second etching process is performed to clean the remaining upper plate layer 41; and introducing CH in the second etching process 4 So that the polymer (mainly C) x H y ) Polymer C x H y Can be epitaxially and intermediately insulated along the sidewalls of upper plate layer 40 at the bottom of patterned photoresist 61The passivation layer 70 is formed on the upper surface of the rim layer 30, and is continuously etched by the etching gas and continuously regenerated in the second etching process, so that the continuously formed passivation layer can dynamically protect the intermediate insulating layer from being erroneously etched in the second etching process, thereby improving the Reliability of the MIM capacitor&TDDB performance.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.
Claims (10)
1. A method of fabricating a MIM capacitor comprising:
providing a substrate, wherein a lower electrode plate layer, an intermediate insulating layer and an upper electrode plate layer are formed on the substrate;
forming a hard mask layer, wherein the hard mask layer covers the upper polar plate layer;
executing a first etching process to etch the hard mask layer and the upper electrode plate layer with partial thickness;
and executing a second etching process to etch the upper electrode plate layer with the residual thickness, wherein the participation reaction gas in the second etching process comprises the following components: cl 2 And CH (CH) 4 。
2. The method of claim 1, wherein the intermediate insulating layer is a high K dielectric layer.
3. The method of claim 2, wherein the thickness of the intermediate insulating layer is less thanAnd is greater than->
4. The method of claim 2, wherein the etching process parameters for etching the remaining thickness of the upper plate layer during the second etching process to etch the remaining thickness of the upper plate layer comprise: the source power is 400W-1000W; the bias power is 0W-45W; the pressure of the process chamber is 5 mT-10 mT.
5. The method of claim 1, wherein Cl is during the second etching process to etch the remaining thickness of the upper plate layer 2 And CH (CH) 4 The flow ratio of (2) is 3.8:1.
6. The method of fabricating a MIM capacitor according to claim 1, wherein CH 4 The flow rate of (2) is greater than 0sccm and less than or equal to 50sccm.
7. The method of claim 1, wherein during the first etching process to etch the hard mask layer and a portion of the thickness of the upper plate layer, the etching removes a portion of the thickness of the upper plate layer greater than four fifths of the total thickness of the upper plate layer.
8. The method of claim 1, wherein the etching process parameters for etching the partial thickness upper plate layer during the first etching process to etch the hard mask layer and the partial thickness upper plate layer comprise: the source power is 0W-1000W; the bias power is 0W-500W; the pressure of the process cavity is 0 mT-20 mT; the participation reaction gas includes: cl 2 And BCl 3 。
9. The method of manufacturing a MIM capacitor according to claim 8, whereinIn the process of executing the first etching process to etch the hard mask layer and the upper electrode plate layer with partial thickness, cl 2 And BCl 3 The flow ratio of (2) is 1:1.
10. The method of claim 1, wherein the first etching process has a greater etch rate than the second etching process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311307899.7A CN117479825A (en) | 2023-10-10 | 2023-10-10 | Preparation method of MIM capacitor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311307899.7A CN117479825A (en) | 2023-10-10 | 2023-10-10 | Preparation method of MIM capacitor |
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| Publication Number | Publication Date |
|---|---|
| CN117479825A true CN117479825A (en) | 2024-01-30 |
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| CN202311307899.7A Pending CN117479825A (en) | 2023-10-10 | 2023-10-10 | Preparation method of MIM capacitor |
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| CN (1) | CN117479825A (en) |
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