CN117293122A - 用于高密度装置封装的六边形布置连接图案 - Google Patents

用于高密度装置封装的六边形布置连接图案 Download PDF

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CN117293122A
CN117293122A CN202311502534.XA CN202311502534A CN117293122A CN 117293122 A CN117293122 A CN 117293122A CN 202311502534 A CN202311502534 A CN 202311502534A CN 117293122 A CN117293122 A CN 117293122A
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elements
pairs
power supply
connection
pattern
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A·罗摩克里希南
R·谢里菲
D·萨拉斯沃图拉
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Avago Technologies International Sales Pte Ltd
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Avago Technologies General IP Singapore Pte Ltd
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Abstract

本申请案涉及用于高密度装置封装的六边形布置连接图案。用于装置封装的六边形布置的连接图案允许将高密度电路裸片组装成可制造大小的封装。所述连接图案可为用于焊球阵列或半导体封装下的其它类型的连接机构的图案。尽管所述连接图案的密度增加，但所述连接图案满足所述高密度电路的高速操作的高要求串扰规范。

Description

用于高密度装置封装的六边形布置连接图案
分案申请的相关信息
本案是分案申请。该分案的母案是申请日为2019年12月18日、申请号为201911309786.4、发明名称为“用于高密度装置封装的六边形布置连接图案”的发明专利申请案。
技术领域
本发明涉及半导体封装。本发明还涉及用于半导体封装的连接图案及球栅及/或引脚图案。
背景技术
在巨大的客户需求的推动下，电子、联网及通信技术的快速发展导致各种电子装置的广泛采用。在过去四十年中，在半导体(集成电路)裸片上创建装置电路的制造工艺已经过渡通过许多不同的制造工艺节点，从20世纪70年代中期的6μm工艺到撰写本文时的7nm工艺。电路的不断增加的密度、功能性及复杂性已经给承载集成电路裸片的半导体封装带来重大挑战，包含将半导体封装机械及电连接到外部系统电路的挑战。
发明内容
一方面，本申请案提供一种用于半导体封装的连接图案，其包括：多个连接元件，其以六边形图案布置，其包括：多个电力供应元件；多个接地元件；一或多对发射元件；及一或多对接收元件，所述一或多对接收元件中的每一者通过所述接地元件、所述电力供应元件或两者中的一或多者与其它对接收元件分离并与所述一或多对发射元件的全部分离。
另一方面，本申请案提供一种用于半导体封装的连接图案，其包括：多个连接元件，其以六边形图案布置，其包括：多个电力供应元件；多个接地元件；一或多对发射元件；及一或多对接收元件，所述多个连接元件包含：边缘行，其经配置以邻近半导体封装边缘延伸；且其中所述多个电力供应元件中没有一者在所述边缘行中。
另一方面，本申请案提供一种装置，其包括：一组互连电路层；集成电路裸片，其结合到所述组互连电路层的第一表面；六边形布置的导电连接元件阵列，其在所述组互连电路层的第二表面上，其中所述导电连接元件被组织成多个群组，其中所述群组中的一或多者各自包括：多个电力供应元件；多个接地元件；一或多对发射元件；及一或多对接收元件，所述一或多对接收元件中的每一者通过接地元件、电力供应元件或两者中的一或多者与其它对接收元件分离并与所述一或多对发射元件的全部分离。
附图说明
将更容易地获得本发明及其许多伴随优点的更完整的理解，这是因为当结合附图考虑时，将通过参考以下详细描述将更好地理解本发明及其许多伴随优点，其中：
图1说明半导体封装的简化实例；
图2说明现有技术的连接图案；
图3说明根据本发明的实施例的集成电路架构的简化功能框图；
图4说明根据本发明的一些实施例的连接图案；及
图5说明根据本发明的一些实施例的装置封装的仰视图
具体实施方式
下文阐述的详细描述希望作为对主题技术的各种配置的描述，并且不希望表示可实践主题技术的唯一配置。附图并入本文并构成详细描述的一部分。详细描述包含用于提供对主题技术的透彻理解的特定细节。然而，主题技术不限于本文阐述的特定细节，并且可使用一或多个实施方案来实践。在一或多个例子中，以简化形式展示结构及组件，以避免模糊主题技术的概念。
现在参考图式，其中相似参考数字贯穿若干视图表示相同或对应部分，本发明的示范性方面包含用于装置封装的连接图案及球/引脚图案。下文论述的用于装置封装的连接图案及球/引脚图案允许将高密度集成电路裸片组装成可制造大小的封装。连接图案可为用于焊球阵列或半导体封装下的其它类型的电连接机构的图案。尽管连接图案的密度增加，但连接图案仍然满足关于通过连接图案与封装内芯片上的高密度电路进行的高速信令发射及接收的高要求串扰及其它信号完整性规范。
图1说明半导体封装的简化实例。图1展示封装横截面100，其包含在衬底上限定的电路层，所述电路层可结合在一起并且可使用例如通孔来互连电路层。封装横截面100展示结合到一组互连电路层106的第一表面的集成电路裸片104。互连电路层106连接到例如在互连电路层106的第二表面上布置成连接图案的群组的导电连接元件108的阵列。在一些实施例中，连接元件108可为焊球(作为连接元件108)的球栅阵列(BGA)形式，通过连接元件108将封装焊接到印刷电路板(PCB)110上的焊盘图案。下文论述的原理适用于由其它类型的导电连接元件构成的其它类型的连接图案，所述元件包含引脚的引脚栅格阵列(PGA)、平面金属触点的焊盘栅格阵列(LGA)及其它类型的连接机构。此外，除下文描述的特定类型的联网及通信电路之外，下文论述的原理还适用于受信号性能规范约束的任何电路。
将信号连接、电力供应连接及接地连分配到连接图案内的连接点(无论是焊球、引脚或焊盘)是高速电路的重大技术挑战。例如，用于联网及通信装置的高速串行器/解串行器(SerDes)核心必须满足严格的信号性能规范，以确保可靠的操作，特别是远端及近端串扰(FEXT及NEXT)规范。可能适用的额外信号性能规范包含在PCB处测量的发射(Tx)及接收(Rx)回波损耗(RL)、Tx及Rx共模(CM)RL、插入损耗(IL)以及Tx及Rx FEXT。
信号分配的重要复杂因素是整个封装大小必须保持在可制造的大小，但增加连接图案的密度以减小封装大小可能会对信号性能产生不利影响。随着电路速度的增加，信号规格变得更加严格，并且随着封装中裸片上的电路芯数目的增加，找到可制造且满足所需信号完整性规范的可行连接图案的挑战变得极其困难。还应注意，实现更小封装大小也可显著降低制造成本。例如，将封装大小从75mm减小到70mm可使每封装节省大约20美元。
影响信号规范的另一因素是关于从通信伙伴发送到封装的信号的有效接收距离，例如通过PCB上的电路迹线。有效距离有时分为长距离或短距离。封装与通信伙伴之间的插入损耗为30dB或更好可代表短距离，而大于30dB的插入损耗可代表长距离。针对短距离实施方案，接收信号规范通常允许更大的串扰，这是因为接收信号更强，而长距离实施方案需要满足更保守接收串扰规范，这是因为接收信号更弱并且更容易被噪声及干扰破坏。
图2说明用于四个邻近SerDes核心例子的现有技术连接图案200。图2中说明的实例假设每一SerDes核心例子包含四个差分Tx对及四个差分Rx对(四个通道)、一或多个电力供应器及接地信号。现有技术连接图案，例如图2中说明的连接图案可能不能在小于约75mm的主体大小中容纳大量的(例如128个)四通道SerDes核心。
在下文描述的一些实施例中，八通道SerDes核心例子各自包含八个差分Tx对、八个差分Rx对、电力供应器及接地信号，但不同速度及/或具有不同数目的通道的SerDes核心也可采用本文揭示的概念。这些SerDes核心可为集成电路裸片(例如图1中所展示的集成电路裸片104)的一部分，所述集成电路裸片还可包含集成电路内的高速交换机及/或路由器电路核心。图3说明一种此架构的简化功能框图300。在图3中，一或多个SerDes核心305可连接到例如交换机及/或路由器电路核心310，以提供到此电路核心的接口。交换机及/或路由器电路核心310的功能可为例如将网络数据(分组及类似者)从由SerDes核心305中的一者提供的连接交换或路由到由SerDes核心305中的另一者提供的连接。虽然仅展示与SerDes核心305中的每一者相关联的单个Tx及Rx信号线，但应认识到SerDes核心305中的每一者可具有多个Tx及Rx信号线。举例来说，在一些实施例中，SerDes核心305中的每一者可具有八个差分Tx对及八个差分Rx对。另外，图3中未展示SerDes核心305中的每一者中的电路的操作可能需要的电力供应器及接地连接。
图4说明根据本发明的实施例的连接图案。在图4中所展示的实施例中，连接元件400(焊球、引脚等)可以交错或六边形图案布置。与传统矩形(正方形)图案相比，使用六边形图案可将连接密度增加大约13％。另外，在六边形图案中，每一连接点与其六个最近邻居中的每一者等距。图4说明两个六边形连接图案-图案1 403可沿着装置封装的左及右边缘使用，而图案2 405可在装置封装的顶部及底部边缘处使用。
图5说明根据本发明的一些实施例的装置封装500的仰视图。在图5中，图案1 510是沿着装置封装500的左边缘及右边缘的多个图案1中的一者，而图案2 515是沿着装置封装500的顶部边缘及底部边缘的多个图案2中的一者。
再次返回图4，信号连接可布置在连接图案中的每一者中以确保高信号完整性。举例来说，连接图案403及405可用于与八通道400Gbps SerDes核心介接。这些连接图案可遵循一或多个特定设计规则，以帮助连接图案满足所需的信号完整性规范。并非所有连接图案都需要遵循相同规则，并且给定规则是否适用可能取决于速度阈值或其它决策因素。举例来说，每一Rx对可由模拟接地(AGND)连接(例如，展示为虚线区域410及412)及/或模拟供应电压(AVDD)连接来环绕(隔离)。另外，每一Tx对可由模拟接地(AGND)及模拟供应电压(AVDD)连接(例如，展示为虚线区域415及417)的组合来环绕(隔离)。为降低EMI及共模回波损耗，可在最外面的连接行(邻近封装边缘)中避免AVDD连接。Tx或Rx连接可邻近封装边缘放置。
在下表中描述实例设计规则
上文展示的连接图案设计规则可应用于每一个别群组的连接图案403及405内，但是在一些实施例中，也适用于邻近布置的群组的整体连接图案，例如图5中所展示的那些。因此，举例来说，在群组的左边缘处的图4中的Rx对435在另一群组经定位到所说明的连接图案403的左边时与其它Rx对隔离。
已提供以上描述以允许所属领域的技术人员能够制造及使用所主张的发明。可修改以上描述的原理，并且可应用原理及其变型来实现其它连接图案并实现其它设计目标。举例来说，给定以上表达的设计规则，可实施形成连接图案的连接点的其它排列，其也满足任何给定的信号规范集。也就是说，描述及图式提供本发明的实例，并且本发明不仅限于所提供的特定实例。
在可认为以上描述被描述为单独的实施例的程度上，将描述组织到实施例中仅仅是为便于理解本文描述的发明概念。因而，每一实施例的特征可与其它实施例的特征组合而没有限制。显然，鉴于上文教示，本发明的众多修改及变化是可能的。因此，应理解，在所附权利要求书的范围内，本发明可不同于本文具体描述的那样实践。

Claims (18)

1.一种用于半导体封装的连接图案，其包括：
多个连接元件，其以六边形图案布置，其包括：
多个电力供应元件；
多个接地元件；及
多对通信元件，其包括八对发射元件和八对接收元件，
其中所述八对接收元件中的每一者通过由所述接地元件、所述电力供应元件或这两者中的多者所构成的所述六边形图案与所述八对接收元件中的其它者分离并与所述八对发射元件中的全部者分离；
其中所述八对发射元件中的每一者通过由所述接地元件、所述电力供应元件或这两者中的多者所构成的所述六边形图案与所述八对发射元件中的其它者分离；
其中当所述多对通信元件中的每一对的两个元件以垂直的方式布置在所述连接图案中时，所述六边形图案经布置以使得所述每一对的所述两个元件周围的电力供应元件和/或接地元件与所述两个元件中的每一者处于不同的水平位置；且
其中当所述多对通信元件中的每一对的两个元件以倾斜的方式布置在所述连接图案中时，所述六边形图案经布置以使得相应电力供应元件和/或相应接地元件与所述每一对的所述两个元件中的每一者处于相同的水平位置。
2.根据权利要求1所述的连接图案，其中所述八对发射元件中的每一者通过所述接地元件、所述电力供应元件或两者中的一或多者与所述八对接收元件中的全部者分离。
3.根据权利要求1所述的连接图案，其中一个量值的所述多个电力供应元件中的每一者通过接地元件、一对发射元件及一对接收元件中的至少一者与其它量值的其它电力供应元件中的每一者分离。
4.根据权利要求1所述的连接图案，其中所述多个连接元件包含边缘行，其经配置以邻近所述半导体封装的边缘延伸，其中所述多个电力供应元件中没有一者在所述边缘行中。
5.根据权利要求1所述的连接图案，其中所述八对接收元件中的每一者指派到串行器/解串行器SerDes电路的八个接收通道中的一者，并且所述八对发射元件中的每一者指派到所述SerDes电路的八个发射通道中的一者。
6.根据权利要求5所述的连接图案，其中所述SerDes电路通信地连接到分组交换机。
7.根据权利要求5所述的连接图案，其中所述SerDes电路通信地连接到分组路由器。
8.一种用于半导体封装的连接图案，其包括：
多个连接元件，其以六边形图案布置，其包括：
多个电力供应元件；
多个接地元件；
多对通信元件，其包括八对发射元件和八对接收元件；及
所述多个连接元件包含：
边缘行，其经配置以邻近半导体封装边缘延伸；且
其中所述多个电力供应元件中没有一者在所述边缘行中；
其中所述八对接收元件中的每一者通过由所述多个接地元件、所述多个电力供应元件或这两者中的多者所构成的所述六边形图案与所述八对接收元件中的其它者分离并与所述八对发射元件中的全部者分离；
其中所述八对发射元件中的每一者通过由所述多个接地元件、所述多个电力供应元件或这两者中的多者所构成的所述六边形图案与所述八对发射元件中的其它者分离；
其中当所述多对通信元件中的每一对的两个元件以垂直的方式布置在所述连接图案中时，所述六边形图案经布置以使得所述每一对的所述两个元件周围的电力供应元件和/或接地元件与所述两个元件中的每一者处于不同的水平位置；且
其中当所述多对通信元件中的每一对的两个元件以倾斜的方式布置在所述连接图案中时，所述六边形图案经布置以使得相应电力供应元件和/或相应接地元件与所述每一对的所述两个元件中的每一者处于相同的水平位置。
9.根据权利要求8所述的连接图案，其中：
所述多个电力供应元件包括个别电力供应连接元件，且；
一个量值的所述多个电力供应元件当中的每一电力供应连接元件与所述多个电力供应元件当中的其它量值的其它电力供应连接元件中的每一者分离。
10.一种装置，其包括：
一组互连电路层；
集成电路裸片，其结合到所述组互连电路层的第一表面；
以六边形图案布置的导电连接元件阵列，其在所述组互连电路层的第二表面上，其中所述导电连接元件被组织成导电连接元件的多个群组，其中导电连接元件的所述群组中的一或多者各自包括：
多个电力供应元件；
多个接地元件；
多对通信元件，其包括八对发射元件和八对接收元件；及
其中所述八对接收元件中的每一者通过由所述接地元件、所述电力供应元件或这两者中的多者所构成的所述六边形图案与所述八对接收元件中的其它者分离并与所述八对发射元件中的全部者分离；
其中导电连接元件的所述一或多个组的第一组中的所述八对接收元件与导电连接元件的所述一或多个组的邻近组中的对发射元件相分离；
其中，在导电连接元件的所述群组的每一组中，所述八对发射元件中的每一者通过由所述接地元件、所述电力供应元件或这两者中的多者所构成的所述六边形图案与所述八对发射元件中的其它者分离；
其中当所述多对通信元件中的每一对的两个元件以垂直的方式布置在所述阵列中时，所述六边形图案经布置以使得所述每一对的所述两个元件周围的电力供应元件和/或接地元件与所述两个元件中的每一者处于不同的水平位置；且
其中当所述多对通信元件中的每一对的两个元件以倾斜的方式布置在所述阵列中时，所述六边形图案经布置以使得相应电力供应元件和/或相应接地元件与所述每一对的所述两个元件中的每一者处于相同的水平位置。
11.根据权利要求10所述的装置，其中所述八对发射元件中的每一者通过所述接地元件、所述电力供应元件或两者中的一或多者与所述八对接收元件中的全部者分离。
12.根据权利要求10所述的装置，其中一个量值的所述多个电力供应元件中的每一者通过接地元件、一对发射元件及一对接收元件中的至少一者与其它量值的其它电力供应元件中的每一者分离。
13.根据权利要求10所述的装置，其中所述八对接收元件中的每一者通过接地元件、电力供应元件或两者中的一或多者与位于一组邻近的导电连接元件中的接收元件对及发射元件对分离。
14.根据权利要求10所述的装置，其中所述导电连接元件包含边缘行，其经配置以邻近所述组互连电路层的所述第二表面的边缘延伸，其中所述多个电力供应元件中没有一者在所述边缘行中。
15.根据权利要求10所述的装置，其中所述八对接收元件中的每一者指派到串行器/解串行器SerDes电路的八个接收通道中的一者，并且所述八对发射元件中的每一者指派到所述SerDes电路的八个发射通道中的一者。
16.根据权利要求15所述的装置，其中所述SerDes电路通信地连接到分组交换机。
17.根据权利要求15所述的装置，其中所述SerDes电路通信地连接到分组路由器。
18.根据权利要求10所述的装置，其中一个量值的所述多个电力供应元件中的至少一者通过接地元件、一对发射元件及一对接收元件中的至少一者与其它量值的其它电力供应元件中的每一者分离。
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