CN116819178A - Chip scribing groove and extension resistance testing method - Google Patents
Chip scribing groove and extension resistance testing method Download PDFInfo
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- CN116819178A CN116819178A CN202310797317.1A CN202310797317A CN116819178A CN 116819178 A CN116819178 A CN 116819178A CN 202310797317 A CN202310797317 A CN 202310797317A CN 116819178 A CN116819178 A CN 116819178A
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Abstract
The application provides a chip scribing groove and an extension resistance testing method, wherein the chip scribing groove comprises the following steps: the scale structure is arranged between the adjacent chips of the wafer and is used for acquiring measurement of an initial distance; the chip structure to be tested comprising the scale structure is placed in an extended resistance test instrument, and is ground along the direction perpendicular to the intersection point of the two scribing grooves and the preset angle formed by the scribing grooves, so that the target distance of the two probes for testing is amplified according to the initial distance, wherein the target distance is greater than or equal to the inherent distance between the two probes in the extended resistance test process. Therefore, the problem that the SRP test cannot be realized at the position of the scribing groove with insufficient vertical spacing and probe spacing in the SRP test structure is solved, and the SRP positioning test can be realized more accurately for the scribing groove injection.
Description
Technical Field
The application relates to the technical field of extended resistance test chip structures, in particular to a chip scribing groove and an extended resistance test method.
Background
The extended resistance test (spreading resistance profile, SRP) has the advantages of high resistivity test resolution, high speed, longitudinal depth reaching nano-scale and the like, is widely applied to the measurement of the resistance, the resistivity, the carrier concentration and the junction depth of chip substrates, epitaxy and the like, and is one of the common production monitoring or failure analysis important means in the semiconductor industry.
The extended resistance test includes a two probe extended resistance test method. The space between the SRP double probes is generally about 85 mu m, so that the width of the test structure is required to be about 100 mu m in order to ensure the normal work between the double probes, and the length of the test structure is 10-50 times of the depth of the junction to be tested. For example, to test a junction depth of 10um, the length of the test structure required is 140um (longitudinal resolution 0.1 um), 240um (longitudinal resolution 0.05 um). Therefore, the chip area is required to be larger during testing, and the cost of the flow sheet is increased. Or test analysis cannot be realized, for example, the test doped structure is put into the scribing groove, but the width of the scribing groove is only 80 mu m, and the test sample area is smaller than the double-probe interval, so that the extension resistance of the test sample cannot be tested.
Therefore, a new chip dicing channel and extended resistance test scheme is needed.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a chip dicing groove and an extended resistance testing method, which are applied to a process of implementing an extended resistance test by the dicing groove.
The embodiment of the specification provides the following technical scheme:
the embodiment of the specification provides a chip dicing groove, which comprises: the structure of the scale is that,
the scale structure is arranged between the adjacent chips of the wafer and is used for obtaining the measurement of the initial distance;
the chip structure to be tested comprising the scale structure is placed in an extended resistance test instrument, and is ground along the direction perpendicular to the intersection point of the two scribing grooves and the direction of the preset angle formed by the scribing grooves, so that the target distance of the two probes for testing is amplified according to the initial distance, wherein the target distance is greater than or equal to the inherent distance between the two probes in the extended resistance test process.
In some alternatives, the predetermined angle is 45 °, and the target distance is maximally amplified to ∈2 times the scribe line vertical distance.
In some alternatives, the scribe line with the scale structure includes a scribe line peripheral to the scribe line; the scale positions are arranged on the periphery of the scribing groove at intervals of preset width, and the scale positions comprise metal structures or poly (grid) structures.
In some alternatives, the peripheral scale marks of the scribing groove are obtained through exposure and development treatment of a photoetching plate, the surface is shielded by photoresist during photoetching, and then the etching step is carried out.
In some examples, the scale structure is disposed in the wafer die area.
In some alternatives, the scale structure is also used to perform ranging positioning for the chip.
The embodiment of the specification also provides an extended resistance test method, which adopts the chip dicing groove according to any one of the technical schemes, and comprises the following steps:
grinding the chip structure to be detected along the direction perpendicular to the intersection point of the two scribing grooves and the scribing groove according to a preset angle to obtain a ground interface;
detecting whether the double probes are in the scribing groove or not in the ground interface, if yes, placing the double probes into the scribing groove area, and testing along the grinding starting point to obtain a target distance and an SRP test result;
and if not, obtaining an SRP test result by respectively testing the chip area, the first part of the scribing groove area or the second part of the scribing groove area.
Compared with the prior art, the beneficial effects that above-mentioned at least one technical scheme that this description embodiment adopted can reach include at least:
the scribing grooves are simply provided with the corresponding scale structures, and grinding is carried out along the direction perpendicular to the intersection point of the two scribing grooves and the scribing grooves to form a preset angle in the testing process of the extension resistor, so that the target distance of the extension resistor is tested according to the initial distance by amplifying the two probes, wherein the target distance is greater than or equal to the inherent distance of the two probes in the testing process of the extension resistor. Therefore, the problem that the SRP test cannot be realized at the position of the scribing groove with insufficient vertical spacing and probe spacing in the SRP test structure is solved, and the SRP positioning test can be realized more accurately for the scribing groove injection.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic illustration of a chip dicing channel according to the application;
FIG. 2 is a schematic illustration of the post-grinding interface of the present application;
FIG. 3 is a schematic illustration of a dual probe placement in scribe line test in accordance with the present application;
FIG. 4 is a schematic illustration of a dual probe in scribe line test marking according to the present application;
FIG. 5 is a schematic diagram of the extended resistance test junction depth acquisition in the present application;
FIG. 6 is a schematic diagram of an extended resistance test using a chip scribe line in accordance with the present application;
FIG. 7 (a) is a schematic diagram of a partial structure of the present application for performing an extension resistance test using a chip scribe line;
FIG. 7 (b) is a schematic diagram showing a partial structure of the chip dicing groove for performing the extension resistance test according to the application;
FIG. 8 (a) is a schematic diagram of a partial structure of the present application for performing an extension resistance test using a chip scribe line;
fig. 8 (b) is a schematic diagram showing a partial structure of the chip dicing groove for performing the extension resistance test according to the application.
Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, apparatus may be implemented and/or methods practiced using any number and aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the present application may be practiced without these specific details.
The extended resistance test in the prior art is widely applied to the measurement of the resistance, resistivity, carrier concentration and junction depth of chip substrates, epitaxy and the like. The method comprises the step of testing the double-probe extended resistance, wherein when the double-probe method is used for testing, terminals are arranged at two ends of a sample, and through inputting alternating voltage signals, currents at two ends of the sample are collected, so that the sample resistance is obtained, and the sample resistivity is obtained through conversion relation.
However, the space between the SRP double probes is generally about 85 μm, so that the width of the test structure is required to be about 100 μm in order to ensure the normal work between the double probes, and the length of the test structure is 10-50 times of the junction depth to be tested. Therefore, the area of the chip required by the test is larger, and the cost of the chip is increased; or cannot be analyzed due to the absence of test structures, such as considering placement of the doped structures into the scribe line, because the scribe line width is only 80 μm and the test sample area is smaller than the double probe pitch, the spreading resistance of the sample cannot be tested.
Based on this, the embodiment of the present specification proposes a new chip dicing groove and extension resistance test scheme: the scale structure is arranged between adjacent wafer chips based on the existing chip scribing grooves, namely, the chip scribing grooves with the scale structure are obtained.
Typically, hundreds to thousands of chips are connected together on a wafer, and the gap between the chips is called a scribe line. With the development of the size reduction of wafer chips, the width of part of the dicing channels is only 80 μm.
However, the pitch of the SRP dual probes is generally about 85 μm, and the dicing grooves 80 μm cannot meet the distance requirement, so that the extended resistance test cannot be realized. Therefore, in the embodiment of the specification, the dicing grooves are simply provided with the corresponding scale structures, and in the process of testing the extension resistor, the chip structure to be tested containing the scale structures is placed in the test instrument of the extension resistor, and is ground along the direction perpendicular to the intersection point of the two dicing grooves and the direction of the preset angle formed by the dicing grooves, so that the target distance of the extension resistor for testing the two probes is amplified according to the initial distance, wherein the target distance is greater than or equal to the inherent distance of the two probes in the process of testing the extension resistor. Therefore, the problem that the SRP test cannot be realized at the position of the scribing groove with insufficient vertical spacing and probe spacing in the SRP test structure is solved, and the SRP positioning test can be realized more accurately for the scribing groove injection.
The following describes the technical scheme provided by each embodiment of the present application with reference to the accompanying drawings.
In the embodiment of the specification, the scale structures are arranged in the chip scribing grooves, for example, the scale spacing is designed to be 5 μm, and the specific size can be adjusted according to the size of the scribing grooves and the injection depth of the sample. The scale structure can be arranged as scale marks on the periphery of the scribing groove, and can also be arranged in the wafer chip area.
As shown in FIG. 1, for example, the scribe line vertical distance is 80 μm and the scale pitch is 10. Mu.m. The DIE interface is the scribe line doping structure to be tested, and the gray frame is the grinding area with the implant area.
In the process of the extended resistance test, the scribing grooves and adjacent DIEs are ground along the 45-degree direction of the boundary of the two scribing grooves by utilizing a graduated scale, so that the actual test distance (namely the target distance) is increased according to the initial distance measured by the scale structure, the original vertical distance is 80 mu m, and the maximum extension can be realized as the length of an inclined diagonal lineTherefore, the problem that the test cannot be performed due to the fact that the probe spacing is larger than the scribing groove spacing is solved. In some embodiments, the inherent spacing of the two probes during the extended resistance test is 80 μm. The target distance for the two probe tests is amplified based on the initial distance, see the extended resistance test method described in detail below. The target distance is greater than or equal to the initial distance. Of course, if the target distance is smaller than the initial distance, the solution of the embodiment of the present specification can be used to perform the extension resistance test.
According to the embodiment of the specification, the scribing grooves are simply provided with the corresponding scale structures, in the process of testing the extension resistor, the chip structure to be tested containing the scale structures is placed in the test instrument of the extension resistor, and is ground along the direction perpendicular to the intersection point of the two scribing grooves and the preset angle formed by the scribing grooves, so that the target distance of the test of the two probes is amplified according to the initial distance, and the target distance is larger than or equal to the inherent distance between the two probes in the process of testing the extension resistor. The problem that SRP test cannot be realized for the positions of the scribing grooves with insufficient vertical spacing and probe spacing is solved, and SRP positioning test is realized more accurately by injecting the scribing grooves.
In some embodiments the predetermined angle is 45 °, and the target distance is maximally amplified to the scribe line vertical distanceMultiple times.
In combination with the above embodiments, in the embodiments of the present disclosure, a chip structure to be tested including a scale structure is placed in an extended resistance test apparatus, and is polished in a direction perpendicular to the intersection point of two scribe grooves and forming 45 ° with the scribe grooves, referring to the polishing example of fig. 3. Thus, by means of the fixed angle a (as shown in fig. 5) when the sample is tested by the extended resistance, the target distance of the two probe tests can be amplified according to the initial distance measured by the scale structure.
Specifically, if the ground interface satisfies that both probes are placed in the scribe groove, then a is used, using equation one: z=Δx×sina to obtain the target distance for actual amplification. In the formula one, Z represents the test depth, and Deltax represents the target distance. If the ground interface does not meet the requirement that the two probes are placed in the dicing grooves, a formula II is utilized: (see in particular the description below) to obtain the target distance for the actual amplification.
Based on the above embodiment, the vertical distance of the scribe line during the extended resistance test is 80 μm, and the maximum extendable test length is the diagonal length
In some embodiments, the scribe line with the scale structure includes a scribe line peripheral to the scribe line. The scale positions are arranged on the periphery of the scribing groove at intervals of preset width, and the scale positions comprise metal structures or poly (grid) structures.
As shown in fig. 1, the scribe line with the scale structure may include a scribe line peripheral to the scribe line. The scale marks on the periphery of the scribing groove are arranged at intervals of preset width to set scale positions, wherein the preset width is set to be 5 mu m or 10 mu m, and the scale positions are specifically set according to actual requirements.
In some embodiments the scale position comprises a metal structure or a poly structure. However, the scale position in the embodiment of the present specification is not limited to the above-described example structure, and various types of settings may be made according to actual demands.
In some embodiments, the peripheral graduation marks of the scribing groove are obtained through exposure and development treatment of a photoetching plate, the surface is shielded by photoresist during photoetching, and then the etching step is carried out.
Specifically, the scale can be arranged in the step of scribing the groove, the characteristic pattern is drawn on the photoetching plate to obtain the scale position, then the surface is blocked by photoresist during photoetching, and the surrounding structure is etched through the etching step, so that the characteristic pattern with the characteristic pattern, namely the scale position, is reserved for subsequent SRP test.
In some embodiments, the scale structures are disposed within the wafer die area.
Specifically, dicing grooves are formed among thousands of chips on a wafer, and the dicing grooves of the chips in the embodiment of the specification can also be used for arranging a scale structure in a wafer chip area, so that the scale structure can be used for carrying out double-probe positioning to obtain an initial distance in the SRP test process, and further the target distance of two-probe test is amplified. The problem that the prior art scribing groove cannot perform SRP test because the vertical distance cannot meet the inherent distance of the dual-probe test is solved. The scale structure is arranged in the wafer chip area, and can be used for positioning the chip structure, and SRP test can be carried out on any scale position to determine the injection condition of each position.
In some embodiments, the scale structure is also used to perform ranging positioning for the chip.
By combining the embodiments, the scale structure is arranged in the wafer chip area, and can be used for positioning the chip structure, and SRP test is performed on any scale position to determine the injection condition of each position.
In combination with the above embodiments, the present embodiments provide an extended resistance test method. The chip dicing groove adopting the embodiment is used for carrying out the extension resistance test, and specifically comprises the following steps: 1. and grinding the chip structure to be tested along the direction perpendicular to the intersection point of the two scribing grooves and the scribing groove according to the preset angle direction to obtain a ground interface. 2. And detecting whether the double probes are in the scribing groove or not in the interface after grinding, if so, putting the double probes into the scribing groove area, and testing along the grinding starting point to obtain a target distance and an SRP test result. 3. And if not, obtaining SRP test results by testing the chip area, the first part of the scribing groove area or the second part of the scribing groove area respectively.
Specifically, in the wafer chip structure illustrated in fig. 1, polishing is performed along a direction perpendicular to the intersection point of the two scribe lines and the scribe line at 45 ° and the scribe line and the DIE area are polished simultaneously, and the polished chip structure is shown in fig. 2. The preset angle can be used as other examples according to actual conditions, and the preset angle of 45 degrees in the embodiment is convenient for obtaining the SRP test result.
If the ground interface satisfies that the dual probes are in the scribe line, the dual probes are placed into the scribe line area for direct testing, as shown in fig. 3.
If the ground interface cannot meet the requirement that the dual probes are in the scribe line, the SRP test result is obtained by combining the test chip area and the first partial scribe line area or the second partial scribe line area of the scribe line.
The specific test principle is as follows:
if the range of the grinding area is larger, the dual probes fall into the DIE area for testing, the size X of the ground chip structure area is recorded by utilizing a graduated scale, and the probes can be tested along the grinding starting point.
Specifically, as shown in FIG. 4, if the scribe line test depth requirement is Z A Placing the double probes in a DIE area equidistant from the edge of the scribing groove, wherein the junction between the grinding surface DIE and the scribing groove is points A and A ', the points A and A' are x mu m according to the direct reading position of the scale, and the vertical distance from A 'to AA' is known according to the rule of the perpendicular bisector of the equilateral right triangleThe depth of the scribe line in the non-scribe line region was +.>(wherein a is the fixed angle of the angle device when the SRP is prepared, namely formula three) mu m. As shown in FIG. 5, the total test depth Z Measuring ＝Z A +Z B (equation II) because the probe first walks the DIE region segment +.>The actual path taken by the scribe line is to remove Z B Partial data. Thus in-scribe-groove SRP test junctionDepth 0-Z is required to be converted by SRP result B And deleting part of the results to obtain a final result which is the actual test result in the scribing groove.
In some embodiments, detecting that the ground interface satisfies that the dual probes are in the scribe line, placing the dual probes in the scribe line area and testing along the grinding start point to obtain the target distance and the SRP test result includes: and if the length of the test structure is smaller than or equal to the maximum test length and the test depth and the test distance meet the preset conditions, the target distance and the SRP test result are directly obtained in the scribing groove area by utilizing the double probes.
With the inherent structure of the extended resistance test apparatus, the scribe line vertical distance is 80 μm, and the maximum test length that can be extended is 80×2μm=114 μm. Therefore, the length of the test structure is smaller than or equal to the maximum test length, and the test depth and the test distance meet the preset conditions, so that the target distance and the SRP test result are directly obtained in the scribing groove area by utilizing the double probes.
Specifically, the calculation of the test depth and the target distance is as follows: z=Δx×sina. Thereby obtaining the actual test result of the scribing groove.
The scribe line vertical distance is 80 μm, and the polishing direction is 45 ° along the boundary of the two scribe lines for a dual probe pitch 85 μm structure. For example, the scribe line substrate is N-type and has a 6 μm P deep implant with a test depth of 8 μm and a test structure length of 114 μm, the test distance 88 (i.e., 8++sina, where the fixed angle a=5.25°) μm, the scribe line region can be tested directly in the scribe line region if the test initiation line does not exceed point a ", as shown in fig. 6, B is the test initiation point, B" is the test termination point, and the slope between the test initiation line and the test termination point represents the actual test width.
Specifically, the test distance 88 μm is smaller than the maximum test length 114 μm, the test depth is 8 μm, and the corresponding preset conditions of these 2 (the actual test width is 10-50 times of the junction depth to be tested) are satisfied, so that the double probe is placed in the scribe groove as long as the test starting line does not exceed the point a "as in fig. 4, and the actual test width is 88 μm and the SRP test result is obtained.
In some embodiments, if otherwise, obtaining SRP test results by testing the chip area, the first partial scribe line area, or the second partial scribe line area, respectively, includes: if the length of the test structure is greater than the maximum test length, judging the initial end of the scribing groove, and if the initial end of the scribing groove is obtained, dividing the test distance into the test chip length and the scribing groove test length in the area of the first part of the scribing groove corresponding to the initial distance, so as to obtain the target distance of the test and the SRP test result according to the initial distance.
If the test structure length is greater than the maximum test length, the test is performed by using the area of the DIE. And (3) adopting a formula II: z is Z Measuring ＝Z A +Z B ，Z A To test depth of scribe line, Z B To walk through the depth of the non-scribe line region(wherein a is the fixed angle of the angle device such as 5.25 DEG when SRP is used for preparing samples, namely, the third formula), so that the deformation of the second formula is utilized to obtain Z A ＝Z Measuring -Z B The actual test depth of the scribing groove can be obtained, and then according to the formula I: z=Δx×sina obtains the scribe line measured target distance and SRP test result.
For example, the scribe line substrate is N-type and has a depth of 12 μm m P type implant, a test depth of 14 μm, a test structure length of 114 μm, a test width of 140 μm, and a structure 140 μm larger than 114 μm cannot meet the test requirement, and the test is completed in two steps by means of the scale structure.
The first step: as in structure 1 of FIG. 7 (a), the starting point is stopped at the scale (e.g., 10 μm before) before point A "(part of the structure is not tested), i.e., the starting point B is set at 10 μm before point A", where the initial distance of the scribe line is 104 μm, and the test junction depth is 0-10.4 μm satisfying the preset condition. The second step, total test junction depth was 14 μm, resulting in a depth of 3.6 μm (longitudinal resolution 0.1 μm) for grinding to the DIE region,according to formula IIIWherein Z is B =3.6 μm, a is 5.25 °, obtaining x of about 56 μm. Thus, the test chip length can be obtained, and the probe is placed in the DIE area, the total test depth is set to 14um, and the first 56um result is that the DIE area result can be deleted after test, as shown in fig. 7 (b).
In some embodiments, if otherwise, obtaining SRP test results by testing the chip area, the first partial scribe line area, or the second partial scribe line area, respectively, includes: if the length of the test structure is greater than the maximum test length and the initial end of the scribing groove cannot be obtained, a corresponding first curve map is obtained by adopting the test chip area and the first part of the scribing groove area, a corresponding second curve map is obtained by adopting the test chip area and the second part of the scribing groove area, abnormal parts in the first curve map and the second curve map are removed respectively, and normal parts are combined to obtain a complete SRP test result.
In combination with the above embodiments, after the test structure length is greater than the maximum test length, SRP is performed by means of the DIE area and the final target distance and SRP test result are obtained. And combining curves corresponding to the test chip area, the first part of scribing groove area and the second part of scribing groove area to obtain a complete SRP test result.
Specifically, the SRP test results of result 1 were obtained by testing the front section of the scribe line (e.g., the first partial scribe line region) first, as shown in fig. 8 (a), where the sample was tested in a normal SRP configuration, which is a normal test pattern, and the dashed line portion after 5 μm was a non-tested result. The back section of the scribe line (e.g., the second partial scribe line region) is retested to obtain the SRP test result of result 2, as shown in fig. 8 (b), the structure at the starting position is not a normal SRP test structure, so the test pattern is abnormal, and the test is entered into the normal region when the test pattern is normal. The 5 μm rear portion of FIG. 8 (b) contains the results shown by the dashed lines after 8 (a) 5 μm, and the complete scribe line SRP test results can be obtained by combining the two curve results. The test chip area corresponding to the first part of the scribing groove area and the test chip area corresponding to the second part of the scribing groove area can be the same or different.
It is noted that the terms "first," "second," "third," "fourth," and the like in the description and claims of the application and in the foregoing figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein.
The same and similar parts of the embodiments in this specification are all mutually referred to, and each embodiment focuses on the differences from the other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the description is relatively simple, and reference is made to the description of parts of the system embodiments.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present application should be included in the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. A die scribe line, the die scribe line comprising:
the scale structure is arranged between the adjacent chips of the wafer and is used for acquiring measurement of an initial distance;
the chip structure to be tested comprising the scale structure is placed in an extended resistance test instrument, and is ground along the direction perpendicular to the intersection point of the two scribing grooves and the direction of the preset angle formed by the scribing grooves, so that the target distance of the two probes for testing is amplified according to the initial distance, wherein the target distance is greater than or equal to the inherent distance between the two probes in the extended resistance test process.
2. The die scribe line of claim 1, wherein the predetermined angle is 45 ° and the target distance is maximally amplified to ≡2 times the scribe line vertical distance.
3. The die scribe line of claim 1, wherein the scribe line with scale structure comprises a scribe line peripheral to the scribe line; the scale positions are arranged on the periphery of the scribing groove at intervals of preset width, and the scale positions comprise metal structures or poly (grid) structures.
4. A chip dicing groove according to claim 3, wherein the peripheral graduation marks of the dicing groove are obtained by exposure and development treatment of a photomask, masking the surface by a photoresist during lithography, and then etching.
5. The die scribe line of claim 1, wherein the scale structures are disposed within a wafer die area.
6. The die scribe line of claim 5, wherein the scale structure is further used to perform ranging positioning for a die.
7. An extended resistance test method using the chip scribe line according to any one of claims 1 to 6, comprising:
grinding the chip structure to be tested along the direction perpendicular to the intersection point of the two scribing grooves and the scribing groove according to a preset angle to obtain a ground interface;
detecting whether the double probes are in the scribing groove or not in the ground interface, if yes, placing the double probes into the scribing groove area, and testing along the grinding starting point to obtain a target distance and an SRP test result;
and if not, obtaining SRP test results by testing the chip area, the first part of the scribing groove area or the second part of the scribing groove area respectively.
8. The method of claim 7, wherein if yes, placing the dual probes into the scribe line area to test along the polishing start point to obtain the target distance and the SRP test result, comprising:
and if the length of the test structure is smaller than or equal to the maximum test length and the test depth and the test distance meet the preset conditions, the target distance and the SRP test result are directly obtained in the scribing groove area by utilizing the double probes.
9. The method of claim 7, wherein if not, obtaining SRP test results by testing the chip area, the first partial scribe line area, or the second partial scribe line area, respectively, comprises:
if the length of the test structure is greater than the maximum test length, judging the starting end of the scribing groove,
if the starting end of the scribing groove is obtained, the testing distance is divided into the testing chip length and the initial distance which correspond to the scribing groove testing length in the first part of the scribing groove area, so that the target distance of the test and the SRP testing result are obtained according to the initial distance.
10. The method of claim 7, wherein if not, obtaining SRP test results by testing the chip area, the first partial scribe line area, or the second partial scribe line area, respectively, comprises:
if the test structure length is greater than the maximum test length and the initial end of the scribe line cannot be obtained,
a corresponding first curve pattern is obtained by using the test chip region and the first part of the scribing groove region, and a corresponding second curve pattern is obtained by using the test chip region and the second part of the scribing groove region,
and respectively removing abnormal parts in the first curve map and the second curve map, and combining the normal parts to obtain a complete SRP test result.
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