CN112635610A - Photoelectric chip and preparation method thereof - Google Patents
Photoelectric chip and preparation method thereof Download PDFInfo
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- CN112635610A CN112635610A CN202011612872.5A CN202011612872A CN112635610A CN 112635610 A CN112635610 A CN 112635610A CN 202011612872 A CN202011612872 A CN 202011612872A CN 112635610 A CN112635610 A CN 112635610A
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- 238000002360 preparation method Methods 0.000 title abstract description 8
- 238000009792 diffusion process Methods 0.000 claims abstract description 150
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 230000000873 masking effect Effects 0.000 claims abstract description 31
- 230000005693 optoelectronics Effects 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 8
- 238000000206 photolithography Methods 0.000 claims description 7
- 239000000523 sample Substances 0.000 abstract description 24
- 238000012360 testing method Methods 0.000 abstract description 14
- 238000010521 absorption reaction Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention relates to the technical field of chip testing, and discloses a photoelectric chip and a preparation method of the photoelectric chip. The photoelectric chip includes: a first region, a second region, and a third region; the first region comprises a substrate, an epitaxial structure arranged on the substrate and a masking film arranged on the epitaxial structure; the second region comprises a substrate, an epitaxial structure arranged on the substrate and a first diffusion doping layer arranged on the epitaxial structure; the third region comprises a substrate, an epitaxial structure arranged on the substrate and a second diffusion doping layer arranged on the epitaxial structure; the first diffusion doping layer and the second diffusion doping layer are spaced apart from each other. The performance and parameters of the photoelectric chip are tested on the first diffusion doping layer by forming the first diffusion doping layer and the second diffusion doping layer, so that the problem that the performance of the photoelectric chip is inconvenient to detect due to the fact that the needle point diameter of a probe is too large or the probe cannot directly detect the second diffusion region is avoided; the yield of the photoelectric chip is improved.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a photoelectric chip and a preparation method of the photoelectric chip.
Background
In the manufacturing process of the photodetector chip, the diffusion process is used as a ring that directly affects the performance of the photodetector chip, and the diffusion depth of the photodetector chip is usually required to be measured after the photodetector chip is diffused, however, the operation of measuring the diffusion depth of the photodetector chip is complicated and the precision is limited. The diffusion depth of the photodetector chip is typically determined by testing other parameters, such as by testing the magnitude of the breakdown voltage.
However, the speed of a high-speed photoelectric detector chip is above 25Gbps, and a single photon detector chip or other photoelectric chips with special requirements generally have a very small diffusion area, so that the probe test bench cannot directly test the performance of the photoelectric chip, such as breakdown voltage, dark current and the like, after the photoelectric chip is diffusion-doped. Under the circumstance, the photoelectric chip is subjected to the next process, so that the risk is high, and the yield is low.
Disclosure of Invention
The invention provides a photoelectric chip and a preparation method thereof, aiming at solving the technical problems of inconvenient performance test and low yield of the photoelectric chip in the related technology.
In a first aspect, the present invention provides an optoelectronic chip, comprising: a first region, a second region, and a third region; wherein the first region comprises a substrate, an epitaxial structure disposed on the substrate, and a masking film disposed on the epitaxial structure; the second region comprises the substrate, the epitaxial structure arranged on the substrate and a first diffusion doping layer arranged on the epitaxial structure; the third region comprises the substrate, the epitaxial structure arranged on the substrate and a second diffusion doping layer arranged on the epitaxial structure; the first and second diffusion doping layers are spaced apart from each other.
Optionally, the number of the second areas is one or more; the number of the third regions is one.
Optionally, the second region and the third region are spaced apart from each other, and a shortest spacing distance between the second region and the third region is greater than 10 um.
Optionally, the diffusion concentrations of the first diffusion doping layer and the second diffusion doping layer are the same, and the diffusion depths of the first diffusion doping layer and the second diffusion doping layer are the same.
Optionally, the surface area of the second region is greater than the surface area of the third region.
Optionally, the outer contour of the first diffusion doping layer is circular, and the outer contour of the second diffusion doping layer is circular; the diameter of the first diffusion doping layer is larger than that of the second diffusion doping layer.
Optionally, the diameter of the first diffusion doping layer ranges from 30um to 50 um.
In a second aspect, the present invention further provides a method for manufacturing a photovoltaic chip, including:
forming an epitaxial structure on a substrate;
forming a masking film on the epitaxial structure;
removing partial areas on the masking film to form a first preset area and a second preset area respectively;
simultaneously carrying out diffusion doping on the first preset region and the second preset region to form a first diffusion doping layer and a second diffusion doping layer, wherein the first diffusion doping layer and the second diffusion doping layer are separated from each other at intervals;
the substrate, the epitaxial structure and the masking film form a first region, the substrate, the epitaxial structure and the first diffusion doping layer form a second region, and the substrate, the epitaxial structure and the second diffusion doping layer form a third region.
Optionally, the diffusion concentrations of the first diffusion doping layer and the second diffusion doping layer are the same, and the diffusion depths of the first diffusion doping layer and the second diffusion doping layer are the same.
Optionally, the removing the partial region on the masking film includes removing the partial region on the masking film by photolithography.
Compared with the prior art, the technical scheme provided by the embodiment of the invention has the following advantages:
the embodiment of the invention provides a photoelectric chip and a test method of the photoelectric chip. The photoelectric chip tests the performance and parameters of the photoelectric chip on the first diffusion doping layer by forming the first diffusion doping layer and the second diffusion doping layer, so that the problem that the performance of the photoelectric chip is inconvenient to detect because the needle point diameter of a probe is too large or the probe cannot directly detect the second diffusion region is avoided; and the risk caused by poor diffusion of the second diffusion doping layer can be reduced, and the yield of the photoelectric chip is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
In the drawings:
fig. 1 is a schematic structural diagram of an optoelectronic chip provided in an embodiment of the present invention;
fig. 2 is another schematic structural diagram of the optoelectronic chip according to the embodiment of the present invention.
Description of the drawings:
100. a photoelectric chip; 110. a first region; 120. a second region; 130. and a third region.
Detailed Description
For a more clear understanding of the technical features, objects and effects of the present invention, embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following description, it is to be understood that the orientations and positional relationships indicated by "front", "rear", "upper", "lower", "left", "right", "longitudinal", "lateral", "vertical", "horizontal", "top", "bottom", "inner", "outer", "leading", "trailing", and the like are configured and operated in specific orientations based on the orientations and positional relationships shown in the drawings, and are only for convenience of describing the present invention, and do not indicate that the device or element referred to must have a specific orientation, and thus, are not to be construed as limiting the present invention.
It is also noted that, unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," "disposed," and the like are intended to be inclusive and mean, for example, that they may be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. When an element is referred to as being "on" or "under" another element, it can be "directly" or "indirectly" on the other element or intervening elements may also be present. The terms "first", "second", "third", etc. are only for convenience in describing the present technical solution, and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated, whereby the features defined as "first", "second", "third", etc. may explicitly or implicitly include one or more of such features. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
Referring to fig. 1 and 2, an embodiment of the present invention provides an optoelectronic chip 100, including: a first region 110, a second region 120, and a third region 130; wherein the first region 110 includes a substrate, an epitaxial structure disposed on the substrate, and a masking film disposed on the epitaxial structure; the second region 120 includes a substrate, an epitaxial structure disposed on the substrate, and a first diffusion doping layer disposed on the epitaxial structure; the third region 130 includes a substrate, an epitaxial structure, and a second diffusion doping layer; the first diffusion doping layer and the second diffusion doping layer are spaced apart from each other.
The performance and parameters of the photoelectric chip 100 are tested on the first diffusion doping layer by forming the first diffusion doping layer and the second diffusion doping layer in the photoelectric chip 100, so that the problem that the performance detection of the photoelectric chip 100 is influenced and the performance of the photoelectric chip 100 is not favorable for detecting due to the fact that the probe tip diameter of a probe is too large or the probe cannot directly detect the second diffusion doping layer is avoided; and the risk caused by the poor diffusion of the second diffusion doping layer can be reduced, and the yield of the photoelectric chip 100 is improved.
The first diffusion doping layer is a non-functional region, which does not have the performance of the optoelectronic chip 100. The second diffusion doping layer is a functional region, which has the performance of the optoelectronic chip 100. The larger the diameter of the second diffusion doping region, the greater the impact on the performance of the optoelectronic chip 100. The larger the diameter of the second diffusion doping region, the lower the performance of the optoelectronic chip 100. Thus, the diameter of the second diffusion doped region is typically less than 30 um. Thus, when the second diffusion doping region is tested by the probe, the probe is difficult to detect the second diffusion doping layer due to the small diameter of the second diffusion doping region, so that the performance and parameters of the optoelectronic chip 100 cannot be tested. The first diffusion doping layer is used for detecting, the second diffusion doping region can be prevented from being detected, further the performance of the photoelectric chip 100 is prevented from being affected, the related performance and parameters of the photoelectric chip 100 can be obtained through indirect testing, and the risk caused by poor diffusion of the second diffusion doping region is reduced.
The diffusion concentration of the first diffusion doping layer is the same as that of the second diffusion doping layer, and the diffusion depth of the first diffusion doping layer is the same as that of the second diffusion doping layer. This allows indirect detection of the properties and parameters of the optoelectronic chip 100 by probing the first diffuse doping layer.
The number of the second regions 120 is one or more, and the number of the third regions 130 is one. The third region 130 is generally provided only one, and the number of the second regions 120 may be one or more, and the performance and parameters of the optoelectronic chip 100 can be tested by one second region 120.
The second region 120 and the third region 130 are spaced apart, and the shortest spacing distance between the second region 120 and the third region 130 is greater than 10 um. The larger the interval distance between the first diffusion doping layer and the second diffusion doping layer is, the better the performance of the optoelectronic chip 100 is. The first diffusion doping layer is typically selected to be located at four opposite corners of the optoelectronic chip 100, such that electrodes or other patterns may be formed adjacent to the second diffusion doping layer. The interval between the first diffusion doping layer and the second diffusion doping layer is smaller than 10um, and the first diffusion doping layer affects the performance of the photoelectric chip 100.
The substrate is an InP substrate. The masking film comprises SiO2One or more of a masking film or a SiN masking film. In one embodiment, the masking film comprises SiO2A masking film and a SiN masking film, the combination of which results in better performance of the optoelectronic chip 100.
The epitaxial structure comprises a buffer layer, an absorption layer and a top layer which are sequentially arranged, wherein the buffer layer is arranged on the substrate, and the masking film is arranged on the top layer. This may improve the performance of the optoelectronic chip 100.
The buffer layer is an N-type InP buffer layer, the absorption layer is an InGaAs absorption layer, and the top layer is an InP top layer.
The surface area of the second region 120 is greater than the surface area of the third region 130. The second region 120 may be used to test the parameters and performance of the optoelectronic chip 100. The surface area of the second region 120 is greater than the surface area of the third region 130 to facilitate probe testing.
The outer contour of the first diffusion doping layer is circular, and the outer contour of the second diffusion doping layer is circular. The outer contour of the first diffusion doping layer is set to be circular, so that the outer contour of the first diffusion doping layer is close to the real shape of the second diffusion doping layer, and the measured parameters of the photoelectric chip 100 are closer and more real. The diameter of the first diffusion doping layer is larger than that of the second diffusion doping layer, so that detection is convenient by using a probe, and the probe can easily contact the first diffusion doping layer so as to detect the performance of the photoelectric chip 100.
The first diffusion doping layer is of a circular hole structure. The first diffusion doping layer may also be a rectangular structure. Generally, the outer contour of the tip of the probe is cylindrical or conical, and in order to match the outer contour of the tip of the probe, the first diffusion doping layer may be configured to be a circular hole structure, so that the test effect of the optoelectronic chip 100 is better.
The diameter of the first diffusion doping layer is larger than that of the second diffusion doping layer. The diameter of the first diffusion doping layer ranges from 30um to 50 um. The diameter of the tip of the general probe is 30um, and the diameter of the first diffusion doping layer is larger than the diameter of the tip of the probe, so that the probe can detect the first diffusion doping layer more easily, and the yield of the photoelectric chip 100 is improved.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an optoelectronic chip 100 according to an embodiment of the present invention. The first region 110 is shown masked by a masking film and does not diffuse. The masking films of the second region 120 and the third region 130 are etched. The diameter of the second diffusion doping layer is very small in the illustration, typically less than 20um, and the probe tip is difficult to detect in the second diffusion region.
Referring to fig. 2, fig. 2 is a schematic structural diagram of an optoelectronic chip 100 according to another embodiment of the present invention. The second diffusion doping layer is in a ring shape, and the needle point of the probe cannot detect the second diffusion doping layer. So through set up a diameter and be 30um to 50 um's first diffusion doping layer outside the second diffusion doping layer, utilize first diffusion doping layer to test photoelectric chip 100's parameter and performance. Of course, the diameter of the first diffusion doping layer is not particularly limited, and may be generally larger than the diameter of the tip of the probe.
According to the photoelectric chip 100 provided by the embodiment of the invention, the probe is used for detecting the first diffusion doping layer, so that the performance and parameters of the photoelectric chip 100 are tested, the dark current and the breakdown voltage of the photoelectric chip 100 are obtained, and the yield of the photoelectric chip 100 is improved.
The embodiment of the invention also provides a preparation method of the photoelectric chip 100, which comprises the following steps:
forming an epitaxial structure on a substrate;
forming a masking film on the epitaxial structure;
removing partial areas on the masking film to form a first preset area and a second preset area respectively;
simultaneously carrying out diffusion doping on the first preset region and the second preset region to form a first diffusion doping layer and a second diffusion doping layer, wherein the first diffusion doping layer and the second diffusion doping layer are separated from each other at intervals;
the substrate, the epitaxial structure and the masking film constitute a first region 110, the substrate, the epitaxial structure and the first diffusion doping layer constitute a second region 120, and the substrate, the epitaxial structure and the second diffusion doping layer constitute a third region 130.
In the prior art, when the optoelectronic chip 100 is manufactured, a second preset region is generally formed only on the masking film by photolithography, and then the second preset region is subjected to diffusion doping, so as to form a second diffusion doping layer, and further form the third region 130. Thus, after the preparation of the optoelectronic chip 100 is completed, the optoelectronic chip 100 formed into a finished product needs to be tested to obtain the performance and parameters of the optoelectronic chip 100. However, the photoelectric chip 100 after diffusion doping is difficult to directly test through a probe, and the preparation method of the photoelectric chip 100 provided by the embodiment of the invention can indirectly test through the first diffusion doping layer to obtain the relevant performance and parameters of the photoelectric chip 100.
Specifically, removing the partial region on the masking film includes removing the partial region on the masking film by photolithography. Photolithography is a conventional process, and the prepared optoelectronic chip 100 has a good effect.
The substrate and the epitaxial structure are wafers for manufacturing the photoelectric chip 100 in the photodetector, and the epitaxial structure is prepared by sequentially growing an N-type InP buffer layer, an InGaAs absorption layer, and an InP top layer on an InP substrate.
Specifically, the step of photolithography of the masking film generally includes coating a photoresist, exposure, development, and etching. The etching is to remove the part without the protection of the photoresist, and the part with the protection of the photoresist is not etched. In this way, after removing the masking films on the second region 120 and the third region 130 by photolithography, the second region 120 and the third region 130 are simultaneously diffusion-doped to form a first diffusion-doped layer and a third diffusion-doped layer.
The diffusion concentration of the first diffusion doping layer is the same as that of the second diffusion doping layer, and the diffusion depth of the first diffusion doping layer is the same as that of the second diffusion doping layer. This allows indirect detection of the properties and parameters of the optoelectronic chip 100 by probing the first diffuse doping layer.
The diameter of the first diffusion doping layer ranges from 30um to 50um, so that the first diffusion doping layer can be conveniently detected by the probe.
It is to be understood that the foregoing examples, while indicating the preferred embodiments of the invention, are given by way of illustration and description, and are not to be construed as limiting the scope of the invention; it should be noted that, for those skilled in the art, the above technical features can be freely combined, and several changes and modifications can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention; therefore, all equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the claims of the present invention.
Claims (10)
1. An optoelectronic chip, comprising: a first region, a second region, and a third region; wherein the first region comprises a substrate, an epitaxial structure disposed on the substrate, and a masking film disposed on the epitaxial structure; the second region comprises the substrate, the epitaxial structure arranged on the substrate and a first diffusion doping layer arranged on the epitaxial structure; the third region comprises the substrate, the epitaxial structure arranged on the substrate and a second diffusion doping layer arranged on the epitaxial structure; the first and second diffusion doping layers are spaced apart from each other.
2. The optoelectronic chip of claim 1, wherein the number of the second regions is one or more; the number of the third regions is one.
3. The optoelectronic chip of claim 1, wherein the second region and the third region are spaced apart, and a shortest spacing distance between the second region and the third region is greater than 10 um.
4. The optoelectronic chip of claim 1, wherein the diffusion concentrations of the first and second diffusion doping layers are the same, and the diffusion depths of the first and second diffusion doping layers are the same.
5. The optoelectronic chip of claim 1, wherein a surface area of the second region is greater than a surface area of the third region.
6. The optoelectronic chip of claim 1, wherein the outer contour of the first diffusion doping layer is circular and the outer contour of the second diffusion doping layer is circular; the diameter of the first diffusion doping layer is larger than that of the second diffusion doping layer.
7. The optoelectronic chip of claim 6, wherein the diameter of the first diffusion doping layer ranges from 30um to 50 um.
8. A method for preparing a photoelectric chip is characterized by comprising the following steps:
forming an epitaxial structure on a substrate;
forming a masking film on the epitaxial structure;
removing partial areas on the masking film to form a first preset area and a second preset area respectively;
simultaneously carrying out diffusion doping on the first preset region and the second preset region to form a first diffusion doping layer and a second diffusion doping layer, wherein the first diffusion doping layer and the second diffusion doping layer are separated from each other at intervals;
the substrate, the epitaxial structure and the masking film form a first region, the substrate, the epitaxial structure and the first diffusion doping layer form a second region, and the substrate, the epitaxial structure and the second diffusion doping layer form a third region.
9. The method of claim 8, wherein the diffusion concentrations of the first diffusion doping layer and the second diffusion doping layer are the same, and the diffusion depths of the first diffusion doping layer and the second diffusion doping layer are the same.
10. The method of claim 8, wherein the removing the portion of the area on the masking film comprises removing the portion of the area on the masking film by photolithography.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011612872.5A CN112635610A (en) | 2020-12-30 | 2020-12-30 | Photoelectric chip and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011612872.5A CN112635610A (en) | 2020-12-30 | 2020-12-30 | Photoelectric chip and preparation method thereof |
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| CN112635610A true CN112635610A (en) | 2021-04-09 |
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