CN114121707A - Method for detecting STI trench depth - Google Patents
Method for detecting STI trench depth Download PDFInfo
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- CN114121707A CN114121707A CN202111413873.1A CN202111413873A CN114121707A CN 114121707 A CN114121707 A CN 114121707A CN 202111413873 A CN202111413873 A CN 202111413873A CN 114121707 A CN114121707 A CN 114121707A
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- sti
- alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
The application discloses a method for detecting STI trench depth, which comprises the following steps: placing a photoetching alignment mark in the scribing groove area; performing STI etching; collecting photoetching alignment signals; and detecting the STI depth by analyzing the photoetching alignment signal. In the method for detecting the depth of the STI trench, the STI depth is judged by collecting and analyzing the alignment signal, the alignment mark can be used for alignment, the STI depth can be obtained through optical path difference analysis, and the stability of the STI depth between different wafers is further analyzed.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a method for detecting STI trench depth.
Background
In the present IC circuit manufacturing process, a complete chip is usually subjected to tens to twenty times of photolithography, and in such times of photolithography, the remaining levels of photolithography, except for the first, align the pattern of the level with the pattern left by the previous level before exposure. The process of alignment is present during the exposure of the plate and wafer in order to overlay the pattern on the reticle to the pattern already present on the wafer with maximum accuracy.
Alignment accuracy is one of the most important performance indexes of photolithography, and a photolithography machine must perform alignment by optically recognizing alignment marks on a silicon wafer, and generally when the alignment marks of layers are simultaneously performed by a layer process, the alignment marks are used for alignment in the lower layer photolithography. The alignment marks are generally a group of strip-shaped structures with transverse and vertical directions, different widths and different numbers. However, in order to ensure optical recognition, the width is 1 micron or more, and the length is generally tens of microns.
Shallow trench isolation is widely applied to various semiconductor devices, the depth of a shallow trench has an important influence on electrical parameters of the devices, and the depth of the STI is mainly detected by an atomic force microscope at present, but the process of detecting the STI by using the atomic force microscope is slow and the program editing is complex.
Disclosure of Invention
The application provides a method for detecting STI (shallow trench isolation) groove depth, which aims to solve the problems that the process of detecting the STI depth through an atomic force microscope is slow and the program editing is complex at present.
The embodiment of the application provides a method for detecting the depth of an STI trench, which comprises the following steps:
placing a photoetching alignment mark in a scribing groove area;
step two, STI etching is carried out;
step three, collecting photoetching alignment signals;
and step four, detecting the STI depth by analyzing the photoetching alignment signals.
Further, the alignment signal value varies linearly with the STI depth.
Further, the stability of the STI depth between different wafers is judged by monitoring the alignment signal value.
Further, the STI etching is carried out, and the alignment process in the STI etching process carries out alignment under the alignment condition of the alignment mark.
Further, the alignment mark is a zero-level alignment mark.
Further, the alignment mark comprises a plurality of mark patterns.
Further, the formation region of the alignment mark is in a stripe shape.
Further, each of the mark patterns is arranged in a formation region of the alignment mark and constitutes the alignment mark.
Further, each of the mark patterns is in the shape of a bar.
The technical scheme at least comprises the following advantages:
in the embodiment of the application, in the method for detecting the depth of the STI trench, the STI depth is judged by collecting and analyzing the alignment signal, the alignment mark can be used for aligning, the STI depth can be obtained through optical path difference analysis, and the stability of the STI depth between different wafers is further analyzed.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart illustrating steps of a method for detecting STI trench depth according to an exemplary embodiment of the present application;
FIG. 2 is a graph showing the variation of the lithographic signal with STI depth according to the present invention.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 is a flowchart illustrating steps of a method for detecting STI trench depth according to an exemplary embodiment of the present application. Referring to fig. 1, a method of detecting a depth of an STI trench includes:
s11, placing a photoetching alignment mark in the scribing groove area;
s12, STI etching is carried out;
s13, collecting photoetching alignment signals;
and S14, detecting the STI depth by analyzing the photoetching alignment signals.
In order to more intuitively disclose the technical features of the present invention and to highlight the beneficial effects of the present invention, the working principle of the method for detecting the depth of the STI trench of the present invention will be explained with reference to the following embodiments. In the specific embodiments, the formation processes, methods, structural properties, dimensions, and the like of the functional layers are merely examples, and should not be construed as limiting the technical scope of the present invention. Conventional processes, materials, etc. in this field are not described in detail.
The alignment mark is suitable for the depth structure of various film layers, is not limited to a silicon substrate, and in the embodiment of the invention, a plurality of scribing grooves are arranged on the semiconductor substrate, and each scribing groove divides the semiconductor substrate into a plurality of regions to be manufactured.
In the embodiment of the invention, the alignment process in the STI etching process is aligned under the alignment condition of the alignment mark. The alignment mark is a zero-level alignment mark. The alignment mark comprises a plurality of mark patterns, the mark patterns are arranged in a forming area of the alignment mark and form the alignment mark, and the mark patterns are strip-shaped. When the photoetching machine carries out alignment by utilizing the photoetching alignment mark, the depth of the STI groove can be quickly detected by a signal fed back by the machine table.
Table one is a corresponding relationship between the STI depth and the lithography signal provided by the embodiment of the present invention.
Watch 1
Through the STI depth obtained by measurement in the table I and the analysis of the photoetching signal value, the linear change relation between the STI depth and the photoetching signal is obtained.
FIG. 2 is a graph showing the variation of the lithographic signal with STI depth according to the present invention. Referring to fig. 2, in a graph of a variation relationship between a lithography signal and an STI depth, an abscissa x represents the STI depth, y represents a lithography signal value, and a linear relationship between the x and the y is 0.0178x-55.109, so that the STI depth can be known only through alignment information obtained after lithography alignment, and meanwhile, the stability of the STI depth between different wafers can be monitored and judged according to the alignment signal value. The STI depth value can be obtained while photoetching, and compared with the traditional method in which an atomic force microscope is used for detecting the STI depth value, the method is simpler and more convenient, and the process steps are saved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (9)
1. A method for detecting STI trench depth, comprising:
placing a photoetching alignment mark in the scribing groove area;
performing STI etching;
collecting photoetching alignment signals;
and detecting the STI depth by analyzing the photoetching alignment signal.
2. The method of claim 1, wherein the alignment signal value varies linearly with the STI depth.
3. The method of claim 1, wherein the stability of the STI depth between different wafers is determined by monitoring the alignment signal values.
4. The method of claim 1, wherein the STI etching is performed, and an alignment process in the STI etching process is aligned under an alignment condition with the alignment mark.
5. The method of detecting STI trench depth of claim 1, wherein said alignment mark is a zero layer alignment mark.
6. The method of claim 1, wherein the alignment mark comprises a plurality of mark patterns.
7. The method of claim 6, wherein the alignment mark is formed in a stripe shape in the region where the alignment mark is formed.
8. The method of claim 7, wherein each of the mark patterns is arranged in a formation region of the alignment mark and constitutes the alignment mark.
9. The method of claim 8, wherein each of the mark patterns has a stripe shape.
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CN202111413873.1A CN114121707A (en) | 2021-11-25 | 2021-11-25 | Method for detecting STI trench depth |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI817917B (en) * | 2023-04-17 | 2023-10-01 | 南亞科技股份有限公司 | Method of overlay of litho mark and semiconductor structure |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI817917B (en) * | 2023-04-17 | 2023-10-01 | 南亞科技股份有限公司 | Method of overlay of litho mark and semiconductor structure |
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