CN102707215B - Testing method of wafer - Google Patents
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- CN102707215B CN102707215B CN201210161675.5A CN201210161675A CN102707215B CN 102707215 B CN102707215 B CN 102707215B CN 201210161675 A CN201210161675 A CN 201210161675A CN 102707215 B CN102707215 B CN 102707215B
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Abstract
The invention discloses a testing method of a wafer, comprising the following steps: buckling a probe on a wafer according to the relationship of every probe on a probe card and a testing weld point on every pipe core of the wafer; obtaining the position of every probe on the corresponding pipe core, measuring the distance between every probe and more than two border points in the corresponding testing weld point; when the distance is greater than the first threshold value and less than the corresponding second threshold value, the probe corresponding to the distance is located at the correct position; or, the probe corresponding to the distance is located at the wrong position. The testing method can improve the accuracy of detecting.
Description
Technical field
The present invention relates to the field tests of semiconductor device, more particularly, to a kind of method of testing of wafer.
Background technology
The whole manufacturing process of semiconductor device can be divided into wafer manufacture, wafer sort, wafer level packaging and last test
Deng step by step.
Described wafer manufacture refer on Silicon Wafer manufacture semiconductor device, complete semiconductor device manufacture it
Afterwards, Silicon Wafer can be formed the tube core of multiple repetitions（die）.In On-Wafer Measurement step, need described tube core is carried out electrically
Test, to guarantee before encapsulation, the tube core on Silicon Wafer is qualified product, and therefore wafer sort is to improve semiconductor device
One of committed step of yield.
Generally test equipment includes at least one probe（probe）, described probe touches tube core on wafer to carry out
Testing electrical property, specifically, described tube core is usually provided with one or more test solder joints（pad）, described probe and described survey
Test weld point needs to contact with each other, and just can complete testing electrical property.
In prior art, the distribution of the tube core on wafer is typically regularly arranged, with reference to Fig. 1, shows prior art
The schematic diagram of wafer one embodiment, wafer 11 includes multiple identical tube cores 12, and the plurality of tube core 12 is in matrix arrangement,
Multiple tube cores 12 have certain arrangement period in line direction, also have certain arrangement period in column direction.To the crystalline substance shown in Fig. 1
When circle 11 is tested, probe test corresponding with each tube core solder joint 13 is made by mobile wafer 11（Dashed region）Connect
Touch, to complete the test of full wafer wafer 11.
More information with regard to wafer sort refer to the Chinese patent literature of Publication No. CN101587165A.
In order to improve testing efficiency, prior art is all in probe station（prober）On simultaneously setting corresponding with wafer
Probe card（probe card）, with reference to shown in Fig. 2, probe card is provided with multiple probes 14, on each probe 14 and wafer 11
Each tube core 12 on test solder joint 13 corresponding.Under normal circumstances it should make each probe 14 prick in corresponding test weldering
In point 13 regions.
But due to can have thousands of probes 14 in probe card, the distance between two neighboring probe 14 is sometimes
Little to more than ten microns even several microns, therefore it is difficult to ensure that the distance between two neighboring probe 14 is completely the same.Now, reference
It is easy to part probe 15 occur prick region outside corresponding test solder joint 13, thus leading to the survey of this tube core shown in Fig. 3
Examination is unqualified so that final testing result malfunctions.
Test in solder joint region in order to ensure that probe is pricked corresponding, be all to be spot-check using artificial in prior art
Mode is detected, manually randomly chooses one or more probes from thousands of probes, checks this probe whether position
In the region that test solder joint is located.Other spies when the probe spot-check is all located at tram then it is assumed that in probe card
Pin is also all pricked in tram.But, the accuracy rate that this kind of mode detects is very low.When the probe card including 10,000 probes
During the malposition of upper only one of which probe, then the probability that can accurately spot-check this probe only has ten thousand/.Ultimately result in
Originally qualified tube core testing result is unqualified.
Therefore, the accuracy how improving wafer detection just becomes those skilled in the art's problem demanding prompt solution.
Content of the invention
The problem that the present invention solves is to provide a kind of method of testing of wafer, to improve the accuracy of detection.
For solving the above problems, the invention provides a kind of method of testing of wafer, including：
According to the corresponding relation that solder joint is tested on each tube core with wafer for probe each in probe card, probe card is pricked in wafer
On；
Obtain position on corresponding tube core for each probe, and measure each probe with corresponding test in solder joint two with
On the distance between boundary point；
When described distance is more than first threshold and is less than corresponding Second Threshold, then with described apart from corresponding probe position
In tram；Otherwise, it is located at errors present with described apart from corresponding probe.
Alternatively, described first threshold is the diameter of probe.
Alternatively, described test solder joint tested surface be rectangle, described Second Threshold be described rectangle in described distance
The parallel length of side in direction.
Alternatively, the tested surface of described test solder joint is circle, and described Second Threshold is described circular diameter.
Alternatively, when there being probe to be located at errors present, obtain be located at errors present the corresponding offset direction of probe and
Side-play amount, and calculate the quantity of the probe positioned at errors present.
Alternatively, when described quantity is one, calculate and so that all probes is moved to the contrary direction in described offset direction
After adjustment amount, if all probes are all located at tram, described adjustment amount is more than described side-play amount and is less than corresponding second
Threshold value；When described probe is all located at tram, from described wafer, take off described probe card, make described probe card to described
Adjustment amount is moved in the contrary direction in offset direction, and described probe card is pricked again on wafer；When at least there is a probe
Positioned at errors present when, described probe card is taken off from described wafer, make described in be in the probe of errors present to described skew
Adjustment amount is moved in direction in opposite direction, and described probe card is pricked again on wafer.
Alternatively, when the offset direction that described quantity is multiple and all probes positioned at errors present is identical, from position
Select a probe in multiple probes of errors present, according to the side-play amount of the probe selecting, calculating makes all probes to institute
After stating the mobile regulated quantity in the contrary direction in offset direction, if all probes are all located at tram, and described regulated quantity is more than choosing
The side-play amount of the probe selected and be less than corresponding Second Threshold；When at least there is a probe positioned at errors present, constantly weigh
Again from one probe of selection positioned at the remaining probe of errors present, and calculating is re-started according to the side-play amount of the probe selecting
Step, until making described probe be all located at tram to after the mobile adjustment amount in the contrary direction in described offset direction, or according to
, still at least there is probe and be located at error bit in all probes positioned at errors present of secondary selection and after carrying out corresponding calculating
Put；When described probe is all located at tram, from described wafer, take off described probe card, make described probe card to described partially
Move direction in opposite direction and move adjustment amount, and described probe card is pricked again on wafer；When still at least exist a probe
Positioned at errors present when, described probe card is taken off from described wafer, the probe being pointed to errors present is adjusted, and by institute
State probe card again to prick on wafer.
Alternatively, the method for testing of described wafer also includes：Record after all probes are mobile in each calculating process and correspond to
The number of probes positioned at errors present.
Alternatively, after selecting all probes positioned at errors present successively and carry out corresponding calculating, still at least exist
When one probe is located at errors present, be pointed to errors present probe be adjusted including：Relatively calculate anteposition in error bit
It is located at the number of probes of errors present, when minimum to wherein said number of probes pair in the number of probes put and each calculating process
Each probe being located at errors present answered is adjusted.
Alternatively, according to side-play amount from big to small from order from positioned at multiple probes of errors present select one spy
Pin, is calculated according to the side-play amount of the probe selecting.
Alternatively, when the offset direction that described quantity is probe that is multiple and being at least partially disposed at errors present is different,
Described probe card is taken off from described wafer, the probe being pointed to errors present is adjusted respectively, and by described probe card weight
Newly prick on wafer.
Alternatively, after described probe card is pricked on wafer again, each probe and corresponding test weldering are retested
The distance between plural boundary point in point, when all probes are all located at tram, is tested.
Alternatively, described distance is obtained by interference technique.
Alternatively, described distance is obtained by light distance-finding method.
Alternatively, the method for testing of described wafer also includes：When there being probe to be located at errors present, send alarm.
Compared with prior art, the present invention has advantages below：
1）The present invention by probe card prick on wafer after, by measure each probe with corresponding test solder joint in two
The distance between individual above boundary point, and then determine whether corresponding probe is located at tram according to the size of distance, its
It is achieved that detection to each probe compared with the mode of selective examination artificial in prior art, improve the accuracy rate of detection.
2）In alternative, when there being probe to be located at errors present, obtain the corresponding skew of probe being located at errors present
Direction and side-play amount, and calculate the quantity of the probe positioned at errors present, thus the quantity according to the probe positioned at errors present
And offset direction, adjustment probe card is located at the probe position on the probe card of errors present in the position of wafer or adjustment,
Make all probes be all located at tram eventually through the most simple and effective adjustment, further increase the accuracy of detection, and
Simple to operate, low cost.
3）In alternative, when being all located at tram after all probes described adjustment amount of adjustment, from described wafer
Take off described probe card, make described probe card move described adjustment amount, described probe card is pricked again on wafer, now permissible
Ensure that each probe is all located at tram, thus further ensuring the accuracy rate of detection.
4）In alternative, at least there is a probe after all probes adjust described adjustment amount and be located at errors present
When, described probe card is taken off from described wafer, adjustment probe card is in the position of the probe of errors present, thus ensureing each
Individual probe is all located at tram, thus further ensuring the accuracy rate of detection.
5), in alternative, described distance passes through interference technique or light distance-finding method obtains, thus simple to operate, accurately
Degree is high.
Brief description
Fig. 1 is the schematic diagram of prior art wafer one embodiment；
Fig. 2 is the schematic diagram that prior art middle probe card pricks the embodiment on wafer；
Fig. 3 is the schematic diagram that prior art middle probe card pricks another embodiment on wafer；
Fig. 4 is the schematic flow sheet of the method for testing of wafer in the embodiment of the present invention one；
Fig. 5 is that in embodiment one, test solder joint is the schematic diagram that rectangle and probe are located at during tram；
Fig. 6 is that in embodiment one, test solder joint is circular and probe is located at schematic diagram during tram；
Fig. 7 is that in embodiment one, test solder joint is the schematic diagram that rectangle and probe are located at during errors present；
Fig. 8 is that have probe to be located at schematic diagram during errors present in embodiment two；
Fig. 9 is the schematic diagram that in Fig. 8, each probe all adjusts to tram.
Specific embodiment
Understandable for enabling the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Elaborate a lot of details in the following description in order to fully understand the present invention, but the present invention is acceptable
To be implemented different from alternate manner described here using other, therefore the present invention is not limited by following public specific embodiment
System.
Just as described in the background section, the distance between each probe very little in probe card, it is difficult to ensure that each probe it
Between distance comply fully with requirement, thus when probe card is inserted on wafer, part probe is likely on corresponding tube core
Outside the region of test solder joint.Prior art be all detected by way of artificial selective examination each probe whether with each tube core pair
Should contact, thus the accuracy rate of detection is very low.Contact when probe and tube core be not corresponding, and do not spot-check then again, will be by this
Tube core that may be qualified is as defect ware.
For drawbacks described above, the invention provides a kind of method of testing of wafer, after probe card is pricked on wafer,
Test the distance between plural boundary point in solder joint by measuring each probe with corresponding, so big according to distance
Whether the corresponding probe of little determination is located at tram, and it is compared with the mode of selective examination artificial in prior art it is achieved that to every
The detection of individual probe, improves the accuracy rate of detection.
It is described in detail below in conjunction with the accompanying drawings.
Embodiment one
With reference to shown in Fig. 4, present embodiments provide a kind of method of testing of wafer, including：
Step S11, according to the corresponding relation testing solder joint on each tube core with wafer for probe each in probe card, by probe card
Prick on wafer；
Step S12, obtains position on corresponding tube core for each probe, and measures each probe and corresponding test solder joint
In the distance between plural boundary point；
Step S13, judges each described distance respectively whether more than first threshold and be less than corresponding Second Threshold, when being
When, then it is located at tram with described apart from corresponding probe；When no, then it is located at error bit with described apart from corresponding probe
Put.
The present embodiment can realize the detection to each probe in probe card, thus improve the accuracy rate of detection.
Step S11 is first carried out, probe card and wafer is provided, and probe card is pricked on wafer.
Include multiple probes on the present embodiment middle probe card, wafer includes multiple tube cores, each tube core includes one
Or multiple test solder joint, the quantity of probe and test solder joint, arrangement all same, the size of probe is much smaller than test solder joint
Size, as long as make the optional position that probe is inserted in corresponding test solder joint region can achieve detection.But due to adjacent
The distance between probe very little, it is difficult to ensure that the distance between adjacent probe is completely the same, thus lead to most of probe to be inserted into
When in corresponding test solder joint region, also have probe and be inserted into outside corresponding test solder joint region.
For simplicity, it is all so that a test solder joint is included on tube core as a example to illustrate below.
Specifically, the tested surface of described test solder joint can be rectangle or circle, can also be other shapes,
It does not limit the scope of the invention.
The described detailed process pricking probe card on wafer is same as the prior art, will not be described here.
Then execution step S12, obtains position on corresponding tube core for each probe, and measure each probe with corresponding
The distance between plural boundary point in test solder joint.
With reference to shown in Fig. 5, when the tested surface testing solder joint 23 is rectangle, the tested surface of tube core 22 is generally rectangular cross-section, visits
The corresponding surface of pin 24 is circle.At this point it is possible to measurement probe 24 and the vertical dimension testing each boundary line of solder joint 23.Specifically,
Vertical dimension between the low order end point of probe 24 and test solder joint 23 left side boundary line is defined as x1, when probe 24 is located at a left side
During the right of face boundary line, described just take apart from x1, when probe 24 is located at the left side of left side boundary line, described take apart from x1
Negative, just it is to the right；Vertical dimension between the high order end point of probe 24 and test solder joint 23 right side boundary line is defined as x2,
Just it is to the left；Vertical dimension between the bottom point of probe 24 and test solder joint 23 upper bounds line is defined as y1, downwards
For just；Vertical dimension between the top point of probe 24 and test solder joint 23 lower border wire is defined as y2, upwards for just.
Due to x1+x2=D1, y1+y2=D2, when x1 and y1 meet require when, x2 and y2 also meets requirement, therefore can only measure x1 or
X2 and y1 or y2.
With reference to shown in Fig. 6, when the tested surface testing solder joint 33 is circular, the tested surface of tube core 32 is generally rectangular cross-section, visits
The tested surface of pin 34 is circle.At this point it is possible in measurement probe 34 and test solder joint 33 between the above boundary point of any two
Distance.Specifically, the low order end point of probe 34 is defined as X1 with test solder joint 33 the distance between left side boundary point, to the right
For just；The high order end point of probe 34 is defined as X2 with test solder joint 33 the distance between right side boundary point, to the left for just；Will
The bottom point of probe 34 is defined as Y1 with testing the distance between solder joint 33 the top boundary point, is just downwards；By probe 34
The top point the distance between bottom boundary point is defined as Y2, upwards for just with test solder joint 33.
It should be noted that above-mentioned x1, x2, y1, y2, X1, X2, Y1 and Y2 are to be made with most distal point corresponding in probe
For one of location point.
Above-mentioned each distance can be obtained by interference technique, especially by observation interference fringe（interference
fringes）To realize, it will not be described here known to for those skilled in the art being.
Above-mentioned each distance can also be found range by light（light and dark elements）Method obtains, i.e. probe
Needle tracking be black in the case of light field, test spot area is white in the case of light field, can be arrived in vain by black back gauge
Color back gauge and obtain coverage value.In the case of details in a play not acted out on stage, but told through dialogues, vice versa.
It should be noted that above-mentioned each distance can also be measured using other distance-finding methods in prior art, it does not limit
Protection scope of the present invention.
Whether then execution step S13, judge each described distance more than first threshold and less than Second Threshold respectively.
Wherein, what shape the tested surface no matter testing solder joint is, described first threshold can be probe diameter, that is, when
When probe is located at tram, its distance away from test solder joint edge point needs more than probe diameter, thus probe is just located at
In test solder joint region.
When the tested surface of described test solder joint is rectangle, described Second Threshold can in described rectangle with described distance
The parallel length of side in direction.For the distance in different directions, the value of corresponding Second Threshold is different.
With reference to shown in Fig. 5, described vertical dimension x1 and x2 are all higher than probe diameter and are less than length of side D2, described vertical dimension
Y1 and y2 is all higher than probe diameter and is less than length of side D1, thus probe 24 is located in test solder joint 23 region, i.e. probe 24
Positioned at tram.
When the tested surface of described test solder joint is circular, described Second Threshold can be described circular diameter.
With reference to shown in Fig. 6, described it is all higher than probe diameter and the diameter less than probe diameter 33 apart from X1, X2, Y1 and Y2
D, thus probe 34 is located in test solder joint 33 region, that is, probe 34 is located at tram.
With reference to shown in Fig. 7, described vertical dimension y1 and y2 are all higher than probe diameter and are less than length of side D1, but vertical dimension
X1 is more than length of side D2, and vertical dimension x2 is less than probe diameter, thus x1 and x2 is undesirable, probe 44 is located at corresponding chip 42
Test solder joint 43 region outside.Now, probe 44 is in errors present.
Further, when there being one or more probes to be located at errors present, can be sent out alarm.Specifically, permissible
Send voice alarm, display alarm or light alarm, to remind tester to make adjustment in time, so that described probe is just located at
Really position.
When all probes are all located at tram, tested, specific test process is same as the prior art, here
Repeat no more.In practical application, positioned at errors present probe ratio not over 5/1000ths, therefore, several when having
When individual probe is located at errors present, probe card can be taken off from wafer, the probe being pointed to errors present is adjusted, with
Make again to prick all probes in the probe card on wafer and be all located at tram, finally ensure that the accuracy of detection.
Embodiment two
Present embodiments provide a kind of method of testing of wafer, when the method using embodiment one judges to learn each probe
After whether being located at tram, when there being probe to be located at errors present, the probe positioned at errors present can also be obtained further
Corresponding offset direction and side-play amount, and calculate the quantity of the probe positioned at errors present.
When described quantity is one, calculates and make all probes move adjustment amount to the contrary direction in described offset direction
Afterwards, if all probes are all located at tram, described adjustment amount is more than described side-play amount and is less than corresponding Second Threshold；
When described probe is all located at tram, from described wafer, take off described probe card, make described probe card to
Adjustment amount is moved in the contrary direction in described offset direction, and described probe card is pricked again on wafer；
When at least there is a probe positioned at errors present, taking off described probe card from described wafer, making described place
Probe in errors present moves adjustment amount to the contrary direction in described offset direction, and described probe card is pricked again in wafer
On.
Therefore, when the probe positioned at errors present is one, can be by adjusting probe card in the upper position of wafer
Or adjustment is located at the probe position on the probe card of errors present, all probes again pricked on wafer are made to be all located at
Tram.In practical application, in most cases can be so that again by adjusting position on wafer for the probe card
The all probes pricked on wafer are all located at tram, thus simple to operate.
Fig. 8 is a specific example.Include 8 tube cores on chip 110 shown in Fig. 8, be followed successively by tube core 121 ~ 128；Often
Individual tube core includes a test solder joint respectively, is followed successively by test solder joint 131 ~ 138；Each test solder joint corresponds to a probe, according to
Secondary the transverse width of each test solder joint is 10 microns, and longitudinally wide is 8 microns for probe 141 ~ 148, and probe diameter is 0.2
Micron.In conjunction with reference to shown in Fig. 5, successively by the low order end point of probe 141 ~ 148 away from the left boundary line testing solder joint 131 ~ 138
Distance definition be x11 ~ x88, by boundary line above the bottom point distance test solder joint 131 ~ 138 of probe 141 ~ 148
Distance definition is y11～y88, shown in concrete numerical value reference table 1.
Table 1
| Apart from title | Initial value | Value after 1 micron of adjustment to the left |
| x11 | 4.2 micron | 3.2 micron |
| x22 | 4.4 micron | 3.4 micron |
| x33 | 6.5 micron | 5.5 micron |
| x44 | 6.9 micron | 5.9 micron |
| x55 | 4.3 micron | 3.3 micron |
| x66 | 4.9 micron | 3.9 micron |
| x77 | 10.8 microns | 9.8 micron |
| x88 | 7.7 micron | 6.7 micron |
| y11 | 5.5 micron | 5.5 micron |
| y22 | 5.5 micron | 5.5 micron |
| y33 | 5.8 micron | 5.8 micron |
| y44 | 2.5 micron | 2.5 micron |
| y55 | 6.1 micron | 6.1 micron |
| y66 | 4.0 micron | 4.0 micron |
| y77 | 3.4 micron | 3.4 micron |
| y88 | 6.8 micron | 6.8 micron |
In analytical table 1, the initial value of each distance understands, probe 147 is located at errors present（X11 is more than 10 microns）, it is only
It is deviated to the right 0.8 micron, other probes are located at tram.So that all probes are all located at tram, institute can be made
Some probes are all moved to the left adjustment amount, and described adjustment amount is more than 0.8 micron and is less than 10 microns.The direction of described adjustment amount with
The probe positioned at errors present is made to adjust identical to the direction of tram.As：Probe positioned at errors present needs to the left
Tram can be located at, then the direction of adjustment amount is a left side.Specifically, all probes all 1 micron of left shift can be made, now may be used
Tram is all located at all of probe of guarantee（X11 ~ x88 after adjustment is all higher than 0.2 micron and is less than 10 microns, and y11～
Y88 is all higher than 0.2 micron and is less than 8 microns）, with specific reference to shown in Fig. 9.
In above-mentioned example, suitable adjustment amount can be found by calculating, so that after all probes described adjustment amount of adjustment all
Positioned at tram.Then probe card can be taken off from wafer, make probe card be moved to the left above-mentioned adjustment amount, and by described spy
Pin card is pricked again on wafer.
In other cases, if after calculating, still suffer from the situation that probe is located at errors present, then spy is taken off from wafer
Pin card, makes the probe being in errors present be moved to the left described adjustment amount, and described probe card is pricked again on wafer.
In order to improve the accuracy of test further, after described probe card is pricked on wafer again, can also be again
Test each probe and test the distance between plural boundary point in solder joint with corresponding, when all probes are all located at correctly
During position, tested.
When described quantity is multiple, can determine whether the offset direction of probe positioned at errors present whether with
To.
When the offset direction that described quantity is multiple and all probes positioned at errors present is identical, can be from positioned at mistake
By mistake select a probe in multiple probes of position, according to the side-play amount of the probe selecting, calculate make all probes to described partially
After moving the mobile regulated quantity in direction in opposite direction, if all probes are all located at tram, and described regulated quantity is more than selection
The side-play amount of probe and be less than corresponding Second Threshold；
When at least there is a probe positioned at errors present, constantly repeat from choosing positioned at the remaining probe of errors present
Select a probe, and the step that calculating is re-started according to the side-play amount of the probe selecting, until make described probe to described partially
Be all located at tram after moving the mobile adjustment amount in direction in opposite direction, or select successively all probes positioned at errors present and
After carrying out corresponding calculating, still at least there is a probe and be located at errors present；
When described probe is all located at tram, from described wafer, take off described probe card, make described probe card to
Adjustment amount is moved in the contrary direction in described offset direction, and described probe card is pricked again on wafer；
When still at least there is a probe positioned at errors present, taking off described probe card from described wafer, being pointed to
The probe of errors present is adjusted, and described probe card is pricked again on wafer.
Preferably, according to side-play amount from big to small from order from positioned at multiple probes of errors present select one spy
Pin, is calculated according to the side-play amount of the probe selecting, and can make all probes when calculating according to maximum side-play amount after adjustment
When being all located at tram, the calculating time can be reduced, improve efficiency.
The process being calculated according to the side-play amount of a certain probe and aforementioned basis are uniquely positioned at the probe of errors present
The process that calculated of side-play amount be similar to, will not be described here.
The present embodiment can also record the corresponding spy positioned at errors present after all probes movements in each calculating process
Pin quantity, thus after selecting all probes positioned at errors present successively and carry out corresponding calculating, still at least have one
Probe be located at errors present when, be pointed to errors present probe be adjusted including：Relatively calculate anteposition in errors present
It is located at the number of probes of errors present in number of probes and each calculating process, corresponding when minimum to wherein said number of probes
The probe that each is located at errors present is adjusted.
In a specific example, probe A, probe B and probe C left shift simultaneously, and the side-play amount of probe A is 2 micro-
Rice, the side-play amount of probe B is 3 microns, the side-play amount of probe C is 1 micron, and test solder joint is in the corresponding Second Threshold of left and right directions
For 9 microns.Because the side-play amount of probe B is maximum, therefore first all probes can be made all to offset to the right according to the side-play amount of probe B
Regulated quantity, described regulated quantity is more than 3 microns and is less than 9 microns, such as：4 microns, and then it is described to judge that all probes all move right
Whether it is all located at tram after regulated quantity.In this example, calculate and learn that all probes all move right after 4 microns although visiting
Pin B may be located at tram, but still has four probes to be located at errors present.Side-play amount then according to probe A makes to own
Probe all offset adjusted amounts to the right, described regulated quantity is more than 2 microns and is less than 9 microns, such as：2.5 microns, and then judge all spies
Pin all moves right whether be all located at tram after described regulated quantity.Now, calculate and learn that all probes all move right 2.5
After micron, only one of which probe D is located at errors present, and probe D offsets to the right 0.8 micron.Side-play amount then according to probe C
Make all probes all offset adjusted amounts to the right, described regulated quantity is more than 1 micron and is less than 9 microns, such as：1.6 microns, and then sentence
All probes that break all move right whether be all located at tram after described regulated quantity.Now, calculate learn all probes all to
After moving right 1.6 microns, two probes are had to be located at errors present.By above-mentioned three times calculate, when all probes all to the right
After mobile 2.5 microns, minimum positioned at the number of probes of errors present, therefore, probe card is taken off from wafer, adjust probe D
Position on the probe card, even if probe D is moved to the left 1 micron（The side-play amount of probe D when calculating more than second）, Ran Houzai
Probe card is pricked on wafer again, and makes present probe card move right 2.5 microns with respect to position when starting.This
When it is ensured that all probes are all located at tram.
When the offset direction that described quantity is probe that is multiple and being at least partially disposed at errors present is different, from described crystalline substance
Described probe card is taken off on circle, the probe being pointed to errors present is adjusted respectively, and described probe card is pricked again in crystalline substance
On circle.Now, described probe card is being pricked after on wafer again it is also possible to retest each probe and corresponding test weldering
The distance between plural boundary point in point, when all probes are all located at tram, is tested.
In a specific example, probe E offsets up 3 microns, and probe F offsets to the right 2.8 microns.Both spy can have been adjusted
Pin E and probe F position on the probe card, thus it is ensured that all spies on the premise of not changing probe card position on wafer
Pin is all located at tram；Adjustment probe card can also be calculated in crystalline substance according to the side-play amount of probe E or probe F and offset direction
Behind position on circle, positioned at the quantity of the probe of errors present, when described quantity is 1（I.e. probe G is located at errors present）,
Then probe G position on the probe card can be adjusted according to the offset direction of probe G and side-play amount, and according to skew when calculating
Amount, adjusts position on wafer for the probe card, thus ensureing that all probes are all located at tram.
Because the present embodiment can ensure that each probe is pricked respectively within corresponding test solder joint region, thus can
To ensure the accuracy of wafer sort.
Although the present invention is disclosed as above with preferred embodiment, the present invention is not limited to this.Any art technology
Personnel, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should
When being defined by claim limited range.
Claims (13)
1. a kind of method of testing of wafer is it is characterised in that include：
According to the corresponding relation that solder joint is tested on each tube core with wafer for probe each in probe card, probe card is pricked on wafer；
Obtain position on corresponding tube core for each probe, and it is plural with corresponding test solder joint to measure each probe
The distance between boundary point；
When described distance is more than first threshold and is less than corresponding Second Threshold, then just it is located at apart from corresponding probe with described
Really position；Otherwise, it is located at errors present with described apart from corresponding probe；
Wherein, when there being probe to be located at errors present, the corresponding offset direction of probe being located at errors present and side-play amount are obtained,
And calculate the quantity of the probe positioned at errors present；The skew being multiple and all probes positioned at errors present when described quantity
When direction is identical, from selecting a probe positioned at multiple probes of errors present, according to the side-play amount of the probe selecting, calculate
Make all probes to after the mobile regulated quantity in the contrary direction in described offset direction, if all probes are all located at tram, institute
State regulated quantity to be more than the side-play amount of probe of selection and be less than corresponding Second Threshold；
When at least there is a probe positioned at errors present, constantly repeat from selection one positioned at the remaining probe of errors present
Individual probe, and the step re-starting calculating according to the side-play amount of the probe selecting, until make described probe to described skew side
It is all located at tram after moving adjustment amount in the opposite direction, or select all probes positioned at errors present successively and carry out
After corresponding calculating, still at least there is a probe and be located at errors present；
When described probe is all located at tram, from described wafer, take off described probe card, make described probe card to described
Adjustment amount is moved in the contrary direction in offset direction, and described probe card is pricked again on wafer；
When still at least there is a probe positioned at errors present, taking off described probe card from described wafer, being pointed to mistake
The probe of position is adjusted, and described probe card is pricked again on wafer.
2. the method for testing of wafer as claimed in claim 1 is it is characterised in that described first threshold is the diameter of probe.
3. the method for testing of wafer as claimed in claim 1 or 2 is it is characterised in that the tested surface of described test solder joint is square
Shape, described Second Threshold is parallel with the direction of the described distance length of side in described rectangle.
4. the method for testing of wafer as claimed in claim 1 or 2 is it is characterised in that the tested surface of described test solder joint is circle
Shape, described Second Threshold is described circular diameter.
5. the method for testing of wafer as claimed in claim 1 is it is characterised in that when described quantity is one, calculating makes institute
There is probe to after the mobile adjustment amount in the contrary direction in described offset direction, if all probes are all located at tram, described tune
Whole amount is more than described side-play amount and is less than corresponding Second Threshold；
When described probe is all located at tram, from described wafer, take off described probe card, make described probe card to described
Adjustment amount is moved in the contrary direction in offset direction, and described probe card is pricked again on wafer；
When at least exist a probe be located at errors present when, take off described probe card from described wafer, make described in be in mistake
The probe of position moves adjustment amount to the contrary direction in described offset direction by mistake, and described probe card is pricked again on wafer.
6. the method for testing of wafer as claimed in claim 1 is it is characterised in that also include：Record institute in each calculating process
The corresponding number of probes positioned at errors present after having probe mobile.
7. wafer as claimed in claim 6 method of testing it is characterised in that ought select successively all positioned at errors present
Probe and after carrying out corresponding calculating, when still at least there is probe and being located at errors present, is pointed to the probe of errors present
Be adjusted including：
Relatively calculate the number of probes that anteposition is located at errors present in the number of probes and each calculating process of errors present, right
When wherein said number of probes is minimum, the corresponding probe that each is located at errors present is adjusted.
8. wafer as claimed in claim 1 method of testing it is characterised in that according to side-play amount from big to small from order from
Select a probe in multiple probes of errors present, calculated according to the side-play amount of the probe selecting.
9. the method for testing of wafer as claimed in claim 1 is it is characterised in that working as described quantity is multiple and at least part of positions
When the offset direction of the probe of errors present is different, takes off described probe card from described wafer, be pointed to errors present
Probe is adjusted respectively, and described probe card is pricked again on wafer.
10. the method for testing of the wafer as described in claim 1,5 or 9 is it is characterised in that again pricking described probe card
After on wafer, retest each probe and test the distance between plural boundary point in solder joint with corresponding, when all
When probe is all located at tram, tested.
The method of testing of 11. wafers as claimed in claim 1 is it is characterised in that described distance is obtained by interference technique.
The method of testing of 12. wafers as claimed in claim 1 is it is characterised in that described distance is obtained by light distance-finding method
Take.
The method of testing of 13. wafers as claimed in claim 1 is it is characterised in that also include：It is located at errors present when there being probe
When, send alarm.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210161675.5A CN102707215B (en) | 2012-05-22 | 2012-05-22 | Testing method of wafer |
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| CN201210161675.5A CN102707215B (en) | 2012-05-22 | 2012-05-22 | Testing method of wafer |
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| CN102707215B true CN102707215B (en) | 2017-02-22 |
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| CN104049197B (en) * | 2014-06-24 | 2017-12-15 | 上海集成电路研发中心有限公司 | Wafer permits Acceptance Tests system and Acceptable testing process |
| CN106783804B (en) * | 2016-12-21 | 2019-07-26 | 武汉新芯集成电路制造有限公司 | Test structure and the method using the test structure monitoring probe probe mark shift |
| CN108172154B (en) * | 2018-01-03 | 2021-03-19 | 惠科股份有限公司 | Test method and test equipment |
| CN111855663B (en) * | 2019-04-30 | 2023-06-27 | 芯恩（青岛）集成电路有限公司 | Equipment and method for detecting wafer defects |
| CN110703068B (en) * | 2019-11-21 | 2021-01-29 | 中芯集成电路制造(绍兴)有限公司 | Wafer needle pressure testing method and device, controller and wafer tester |
| CN115902327B (en) * | 2023-02-23 | 2023-05-26 | 长春光华微电子设备工程中心有限公司 | Calibration method for probe station positioning compensation and probe station |
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| US20020097062A1 (en) * | 2000-10-30 | 2002-07-25 | Strom John Timothy | Method and process of applying the analysis of scrub mark morphology and location to the evaluation and correction of semiconductor testing analysis, and manufacture |
| US8054097B2 (en) * | 2007-03-06 | 2011-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and system for automatically managing probe mark shifts |
| JP5197145B2 (en) * | 2008-05-14 | 2013-05-15 | 株式会社東京精密 | Probe position correcting method and prober |
| CN101587165A (en) * | 2008-05-23 | 2009-11-25 | 旺矽科技股份有限公司 | Wafer acceptance testing method, contact mat and probe card |
| CN102033142A (en) * | 2009-09-28 | 2011-04-27 | 旺矽科技股份有限公司 | Method for automatically positioning probe clamp |
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