CN116682728A - 隔离式iii-n族半导体装置 - Google Patents

隔离式iii-n族半导体装置 Download PDF

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CN116682728A
CN116682728A CN202310745649.5A CN202310745649A CN116682728A CN 116682728 A CN116682728 A CN 116682728A CN 202310745649 A CN202310745649 A CN 202310745649A CN 116682728 A CN116682728 A CN 116682728A
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layer
substrate
doped
gallium nitride
transistor
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纳维恩·蒂皮尔内尼
萨米尔·彭德哈卡
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

本申请涉及隔离式III‑N族半导体装置。本描述的实例包含一种半导体装置，其具有：衬底(22)；低缺陷层(32)，其经形成在相对于所述衬底(22)的固定位置中；及势垒层(34)，其包含形成在所述低缺陷层(32)上的III‑N族半导体材料且在所述低缺陷层(32)中形成电子气体。所述装置还具有：源极接触件(52)；漏极接触件(54)；及栅极接触件(56)，其用于接收电势，所述电势用于调整所述电子气体中及所述源极接触件与所述漏极接触件之间的导电路径。最后，所述装置具有所述势垒层(34)与所述衬底(22)之间的单侧PN结(22/24)。

Description

隔离式III-N族半导体装置
分案申请的相关信息
本申请是申请日为2016年11月25日、申请号为201680061341.7、发明名称为“隔离式III-N族半导体装置”的发明专利申请的分案申请。
技术领域
本发明大体上涉及半导体装置，且更具体来说涉及隔离式III-N族半导体装置。
背景技术
通常结合各种半导体材料形成集成电路装置。针对一些应用，这些材料包含化合物材料(例如已知III-N族半导体)，已知所述材料包含来自周期表的III族的元素组合。此类元素包含铝、镓、铟及可能硼，且作为III-N族半导体，其与氮组合，使得每个元素促成总体半导体材料。III-N族半导体材料的实例为氮化镓、氮化镓铝、氮化铟及氮化铟铝镓。再者，III-N族半导体装置可通过共享共同硅衬底或晶片包含其它硅基装置，其中因化合物半导体与下层硅衬底之间的差异做出对III-N族半导体装置的调整。
上述方法具有各种优点，例如与氮化镓(GaN)装置结合。例如，此类装置可包含发光二极管(LED)、太阳能电池、抗辐射装置及高温或高电压装置(通常包含晶体管)。但是，这些装置可存在某些缺点，包含在与基于结构或功能性的不同装置混合时的可能的不稳定性。
图1(现有技术)图示说明可使用GaN晶体管实施且如此实施可存在缺点的常规半桥10的示意图。具体来说，半桥10包含两个GaN晶体管T1及T2。众所周知，晶体管T1的漏极D(T1)经连接到第一干线电压(展示为Vline)，且晶体管T2的源极S(T2)经连接到第二干线电压(展示为ground(接地))。因此，晶体管T1称为高侧，且晶体管T2称为低侧。晶体管T1的源极S(T1)和晶体管T2的漏极D(T2)经连接且提供半桥10的输出Vout。晶体管栅极可经连接到通过使用通用输入块12的图示说明所展示的各种信号。特定信号对此讨论没有特殊意义，但其允许晶体管T1和T2以互补的方式操作，所以一个晶体管接通时另一个晶体管断开，反之亦然。最后，如在各种晶体管配置中常见，晶体管T1和T2的各者的源极经连接到相应晶体管的衬底，其中此连接有时称为背栅极。
在操作中，晶体管T1和T2一次接通一个且通常在百分之50的占空比，所以Vout在高侧晶体管T1接通时倾向于Vline且在低侧晶体管T2接通时倾向于接地。基于负载和输入电压，此电路可具有各种使用情况，包含例如转换器中的功率电子设备、开关等。半桥10具有各种使用情况且为人熟知，但是在理想情况下使用GaN技术来实施桥中可出现问题。具体来说，源极到背栅极连接可因连接到同一衬底的不同电压而造成泄漏、不稳定或其它性能降低问题。例如，考虑高电压应用，其中Vline为400伏特。当高侧晶体管T1接通时，Vline(减去跨晶体管T1的电压降)经连接到Vout。例如，如果所述电压降为1伏特，那么当晶体管T1接通时，Vout＝399伏特。因此，晶体管T1的源极到背栅极连接将背栅极耦合到399伏特，同时晶体管T2的源极到背栅极连接将背栅极耦合到接地，借此产生两个晶体管之间的相当大的泄漏路径。作为替代方案，背栅极连接代替地可通过将每个晶体管漏极连接到背栅极而实施。虽然替代方案逐渐降低泄漏问题，但是当高侧晶体管T1和低侧晶体管T2断开时，背栅极上的高电压将对给定设计导致更高表面场且导致更低的寿命，并借此降低晶体管可靠性。此方法的额外问题将包含封装技术需求(例如绝缘裸片附接的需求)中的附加复杂度。
发明内容
在所描述的实例中，一种半导体装置包含：衬底；低缺陷层，其经形成在相对于所述衬底的固定位置中；及势垒层，其包含形成在所述低缺陷层上的III-N族半导体材料且在所述低缺陷层中形成电子气体。所述装置还包含：源极接触件；漏极接触件；及栅极接触件，其用于接收电势，所述电势用于调整所述电子气体及所述源极接触件与所述漏极接触件之间的响应于所述电子气体且由所述电子气体形成的导电路径。最后，所述装置包含所述势垒层与所述衬底之间的单侧PN结。
在另一方面，第一电介质势垒及第二电介质势垒中的每一者沿着所述低缺陷层和所述势垒层的相应边缘对准，且在从所述低缺陷层向所述衬底的方向上进一步延伸并在一定程度上低于所述单侧PN结。
附图说明
图1(现有技术)图示说明常规半桥的示意图。
图2图示说明根据示例实施例的晶体管对(包含衬底和n+掺杂层)的形成的横截面图。
图3图示说明图2的晶体管对的形成的横截面图(附加失配隔离层及缓冲层)。
图4图示说明图3的晶体管对的形成的横截面图(附加电隔离层)。
图5图示说明图4的晶体管对的形成的横截面图(附加低缺陷层、势垒层、覆盖层和栅极电介质层)。
图6图示说明图5的晶体管对的形成的横截面图(附加沟槽和通孔)。
图7图示说明在形成电介质势垒、源极接触件、漏极接触件、栅极接触件及从源极到单侧PN结的n+层的电连接之后的图6的晶体管对的形成的横截面图。
图8图示说明当作为半桥电连接时的图7的晶体管对的横截面图。
图9图示说明晶体管对的替代示例实施例的横截面图，其中使用多个电介质部件来形成电介质势垒。
图10图示说明根据替代示例实施例的晶体管对(包含具有经蚀刻区的衬底)的形成的横截面图。
图11图示说明图10的晶体管对的形成的横截面图(附加沿着经蚀刻区表面形成的n+区)。
图12图示说明图11的晶体管对的形成的横截面图(附加在n+区内侧的区域内形成的各种GaN晶体管层)。
图13图示说明图12的晶体管对的形成的横截面图(附加源极、漏极和栅极接触件)。
图14图示说明图13的晶体管对的形成的横截面图(附加用于展开表面电场的电浮动区)。
具体实施方式
图2到9图示说明根据示例实施例的晶体管对20的形成的横截面图，晶体管对20包含两个GaN场效晶体管(FET)。省略某些材料、过程细节和尺寸，因为其以其它方式已知且不必示范示例实施例的范围。
参考图2，结合半导体衬底22(例如，硅晶片或适用于制造GaN FET的其它衬底)形成晶体管对20。在示例实施例中，衬底22是p半导体材料，意味着轻度掺杂的p-型半导体材料。例如，此掺杂浓度可在1e13/cm3到3e20/cm3的范围中。沿着衬底22的上表面形成(例如，生长或植入)与衬底22互补的半导体材料区或层24。在图示说明的实例中，因为衬底22是p型材料，所以层24是n型材料。再者，相对于衬底22，层24优选地经重掺杂，所以图2图示说明层24具有n+掺杂级。例如，此掺杂浓度可在1e18/cm3到1e21/cm3的范围中。因此，鉴于前文，较少掺杂衬底22和较大掺杂层24的组合提供单侧PN结，如下文描述。再者，此或相当的单侧PN结可通过在高度掺杂的p+衬底(1e18/cm3到3e21/cm3)上生长低掺杂n型硅(1e13/cm3到1e18/cm3)层或在高度掺杂的p+衬底(1e18/cm3到3e21/cm3)上生长低掺杂(1e13/cm3到1e18/cm3)p型硅层且随后在经生长的低掺杂硅薄膜的顶部上形成n+区(1e18/cm3到3e21/cm3)而形成。
参考图3，表示额外制造步骤及项目。具体来说，失配隔离层26经形成在层24上，并如此命名以建立隔离且处理半导体材料层24与将为包含层24上方的III-N族层的层之间的失配(例如在网格结构中)。例如，失配隔离层26可为10到1500纳米的氮化铝。在失配隔离层26上形成缓冲层28。例如，缓冲层28可为1到7微米厚，且包含若干层堆叠，所述堆叠从为具有较少镓的富含铝化合物的堆叠的底部层开始并向堆叠顶部转到一或多个层(即，具有更大量的镓和更少量的铝)。因此，在不限制元素的特定化学计量的情況下，这些材料可经指示为AlxGa1-xN，其中x向缓冲层28的上表面减小。
参考图4，表示额外制造步骤和对应项目。具体来说，在缓冲层28上形成电隔离层30。例如，电隔离层30可为50到4000纳米的半绝缘氮化镓。电隔离层30的半绝缘方面可提供电隔离层30下方的层和其上方的层之间的所要电隔离等级。或者，可使用n型或p型掺杂剂掺杂电隔离层30以降低电荷捕获对晶体管对20中的电流密度的非期望影响。
参考图5，表示额外制造步骤和对应项目。在电隔离层30上形成低缺陷层32。例如，低缺陷层32可为25到2000纳米的氮化镓。可形成低缺陷层32以最小化可对电子迁移率具有不良影响的晶体缺陷。形成低缺陷层32的方法可导致低缺陷层32使用碳、铁或其它掺杂剂物质掺杂(例如，使用低于1e17/cm3的掺杂密度)。
继续参考图5，在低缺陷层32上形成势垒层34。例如，势垒层34可为2到30纳米的：AlxGa1-xN；或通过包含铟而为2到30纳米的InxAlyGa1-x-yN。例如，势垒层34中的III族元素的组合物可为百分之15到35氮化铝及百分之85到65氮化镓。在低缺陷层32上形成势垒层34在紧接在势垒层34下方的低缺陷层32中产生具有电子密度(即，薄层电荷载子密度，例如1(10)12到2(10)13/cm2)的二维电子气体。在形成电隔离层30和/或低缺陷层32期间，添加n型掺杂剂，使得电隔离层30和低缺陷层32的薄层电荷载子密度为二维电子气体下方的捕获电荷和图像电荷提供筛网。例如，经添加的n型掺杂剂可主要包含硅和/或锗掺杂剂。经添加的n型掺杂剂可在电隔离层30和/或低缺陷层32的外延生长期间添加。或者，经添加的n型掺杂剂可通过在形成电隔离层30和/或低缺陷层32之后的离子植入而添加。例如，经添加的n型掺杂剂的平均掺杂密度可为1e16/cm3到1e17/cm3。经添加的n型掺杂剂的分布可基本是均匀的，或可经分级，使得掺杂密度在掺杂区的底部高于在掺杂区的顶部。
完成图5，可在势垒层34上形成可选覆盖层36。例如，覆盖层36可为1到5纳米的氮化镓。最后，可在势垒层34和覆盖层36(如果存在)上方形成栅极电介质层38，以提供所要的阈值电压。例如，栅极电介质层38可包含氮化硅。
参考图6，在预期形成额外结构中表示额外制造步骤。具体来说，在图6中，隔离沟槽40通过蚀刻孔穿过所有上文描述的层且部分到衬底22中而形成。可鉴于下文讨论的考虑进行沟槽40的尺寸的选择。沟槽40操作以提供相邻GaN FET晶体管之间的隔离。同样在图6中，通过蚀刻孔穿过两个最顶部层(即，覆盖层36和栅极电介质38)且进一步穿过势垒层34的大部分厚度，留下一定量的势垒层34以达成期望低接触阻力而形成源极蚀刻42。作为形成源极蚀刻42的相同蚀刻步骤的部分或作为单独蚀刻，从向下至层24的至少上表面的蚀刻42形成通孔44，回顾上文所述上表面是也连同p-衬底22形成的单侧PN结的n+部分；为了图示说明，此类通孔44展示为锥形横截面，但可接受替代方案将形成其具有(若干)垂直侧壁。最后，同样地作为形成源极蚀刻42的相同蚀刻步骤的部分或作为单独蚀刻，通过蚀刻孔穿过两个最顶部层(即，覆盖层36和栅极电介质38)且进一步穿过势垒层34的大部分厚度(优选地到与源极蚀刻42相同的深度)形成漏极蚀刻46。
参考图7，在预期形成额外结构中表示额外制造步骤。在图7中，使用电介质材料填充来自图6的沟槽40以形成电介质势垒48(例如，使用二氧化硅、氮化硅或聚酰胺作为电介质材料)。此外，使用相应导体50(例如金属或掺杂半导体)填充来自图6的通孔44，从而提供电接触到层24。仍进一步，使用导体(优选地为金属)填充来自图6的源极蚀刻42以形成源极接触件52。每个源极接触件52的底部延伸到势垒层34中(但不完全穿过)，以形成到低缺陷层32中的二维电子气体的穿隧连接。类似地，同样使用导体(优选地为金属)填充来自图6的漏极蚀刻46以形成延伸到势垒层34中(但不完全穿过)的漏极接触件54，以形成到低缺陷层32中的二维电子气体的穿隧连接。最后，在源极接触件52和漏极接触件54的每个相应组之间形成栅极导体56，其中每个此栅极导体56与栅极电介质层38接触。例如，栅极导体56中的每一者可包含III-N族半导体材料来提供耗尽模式FET，而其它类型的栅极在此实例的范围内。
给定图7的添加元件，晶体管对20包含两个GaN FET(一般展示为T’1和T’2)。再者，对应每个此FET，其栅极导体56可与其相应源极接触件52横向分离开(例如，500到5000纳米)，而每个栅极56与相应漏极接触件54之间的横向间距是取决于FET的最大操作电压的距离。例如，在针对200伏特的最大操作电压设计的GaN FET中，其漏极接触件54可与其栅极导体56横向分离开1到8微米。在针对600伏特的最大操作电压设计的GaN FET中，其漏极接触件54可与其栅极导体56横向分离开8到30微米。
图7还图示说明电介质势垒48的隔离效应的示例实施例。例如看晶体管T’1，在页面中间的电介质势垒48表示沿着晶体管的左侧边缘的第一电介质势垒，其中所述边缘跨多个不同层垂直出现(所述层包含势垒层34、低缺陷层32、电隔离层30、缓冲层28、失配隔离层26、n+掺杂层24)，且深入衬底22并低于在衬底22与层24之间形成的单侧PN结。类似地，在页面右侧的电介质势垒48表示沿着所述相同层的第二边缘的第二电介质势垒。因此，这些势垒用来通过中断层的连续性并且延伸到单侧PN结下方而隔离晶体管T’1，以及其它相当的隔离装置(如晶体管T’2)。同样在下文进一步讨论此隔离的益处。
图8重复图示说明来自图7的晶体管对20，但添加示意性连接的描绘，使得使用晶体管T’1和T’2形成半桥60。一般来说，来自半桥60的源极/漏极和栅极连接与来自图1的半桥10的源极/漏极和栅极连接相当，其中添加撇号来参考图8中的识别符以区分图8和图1。尽管如此，一般来说，容易理解半桥配置。但是，这些连接以外的进一步各种方面来源于图7和8的示例实施例结构。具体来说，在图8中，每个源极接触件52经电连接到层24，回顾上文，所述层24是与衬底22组合提供单侧PN结的n+掺杂层。如同各种半导体晶片通常的情况，衬底22经连接到接地。同样地，每个电介质势垒48提供晶体管和任何横向相邻的结构之间的隔离，其中在图8的中间展示的电介质势垒48将形成晶体管T’1的层与形成晶体管T’2的层分离。此类分离层包含层24。由于绝缘分离，且进一步归因于由从每个相应源极接触件52向下延伸的导体50提供的连接性，针对每个相应晶体管中的单侧PN结达成不同的PN偏压。更具体来说，针对晶体管T’1，层24的其相应片段接收Vout的偏压(来自其源极S(T’1))，而针对所述晶体管的电介质势垒48之间的半导体衬底22的部分接地。相反，针对晶体管T’2，层24的其相应片段接收接地的偏压(来自其源极S(T’2))，而针对所述晶体管的电介质势垒48之间的半导体衬底22的部分也接地。因此，当晶体管T’1接通时(例如当充当半桥60中的高侧时)，层24的其片段与衬底22之间的单侧PN结经非常强反向偏压，借此使晶体管免于出现且在上文描述的泄漏问题。同时，相对于晶体管T’2，其通过示例实施例结构隔离且已经接地连接到其隔离单侧PN结的两个侧，借此促进其的正确操作。
由示例实施例结构达成的隔离益处(包含每个相应晶体管的相应隔离单侧PN结)也将为每个电介质势垒48建议尺寸和变化。因此，给定预期或指定电压水平的情况下，选择此类尺寸来防止单侧PN结中的结击穿。例如，在图8的方法中，每个此势垒48可为V隔离/20V微米的一到三倍宽，其中V隔离是所需的隔离的量。此外，每个此势垒48优选地延伸到层24下方的在V隔离/20V微米的一到三倍的范围中的距离。实际上，这些考虑和尺寸表明，可在示例实施例内实施其它结构以达成其它方式相邻的GaN晶体管之间的垂直隔离。在此方面，图9再次图示说明来自图7的晶体管对20的横截面图，但使用多个电介质势垒48’来替换来自图7的每个电介质势垒48，其中图9的实例中的每个多数由四个垂直电介质势垒48’构成。同样，电介质材料可为聚酰胺、二氧化硅或氮化硅，但尺寸的不同之处在于每个电介质势垒48’可具有更小的宽度(例如1μm到10μm)且深入衬底22中的更小深度(例如，和针对图7中的电介质势垒48给定的深度比较，1μm到V隔离/20V微米宽的一到三倍的深度)。
图10到14图示说明形成额外替代示例实施例晶体管对20的横截面图，其再次将包含两个GaN FET。
参考图10，结合半导体衬底122(例如，硅晶片或适用于制造GaN FET的其它衬底)形成晶体管对20。在示例实施例中，衬底122是p-半导体材料(轻度掺杂的p型半导体材料)。再者，执行适当掩模及蚀刻(例如，<111>晶片的干蚀刻或<111>晶片的湿蚀刻)以形成部分到衬底122中的两个沟槽124。可鉴于下文讨论的考虑选择沟槽124的尺寸，但沟槽124操作以提供每个沟槽中形成的GaN FET晶体管之间的有效面积和一些隔离，如下文描述。同样地，沟槽124的侧壁可取决于蚀刻条件是垂直或倾斜的。
图11图示说明额外制造步骤和项目。具体来说，沿着每个沟槽124的上表面(即，平行于衬底122的平面)并且还沿着每个沟槽124的每个侧壁形成(例如，生长或植入)与衬底122互补的半导体材料区或层126。例如，可使用方形植入来交替定位衬底122，以沿着衬底122中的这些暴露沟槽表面植入层126，层126借此既沿着沟槽底部又向上朝向衬底122的上表面延伸。在图示说明的实例中，因为衬底122是p型材料，所以层126是n型材料。再者，相对于衬底122，层126优选地经重掺杂，所以图11图示说明层126具有n+掺杂级(例如，1e18/cm3到1e21/cm3)。因此，较少掺杂衬底122和较大掺杂层126的组合再次提供单侧PN结，如根据此文献中的教示进一步了解。如同其它示例实施例，此或相当的单侧PN结可通过在高度掺杂的p+衬底(1e18/cm3到3e21/cm3)上生长低掺杂n型硅(1e13/cm3到1e18/cm3)层或在高度掺杂的p+衬底(1e18/cm3到3e21/cm3)上生长低掺杂(1e13/cm3到1e18/cm3)p型硅层且随后在经生长的低掺杂硅薄膜的顶部上形成n+区(1e18/cm3到3e21/cm3)而形成。
参考图12，表示额外制造步骤及项目。具体来说，在图12中，沿着已经形成的层126，使用额外层填充来自沟槽124的剩余敞开区(见图10)直至最终形成每个沟槽中的相应GaN FET，其中在图12中重复来自其中详细描述此类层的图5的实施例的元件符号。因此，在图12中，此类层包含失配隔离层26、缓冲层28、电隔离层30、低缺陷层32、势垒层34、可选覆盖层36和栅极电介质层38。
参考图13，表示额外制造步骤。具体来说，沟槽(未展示)自图12中图示说明的上表面形成且使用导体(优选地金属)填充以形成源极接触件128。每个源极接触件128的底部延伸到势垒层34中(但不完全穿过)，以形成到低缺陷层32中的二维电子气体的穿隧连接。但是，每个源极接触件128也接触层126或(任选地通过中间导体(未展示))与层126电连通，并优选地连通到向上朝向衬底122的表面延伸的所述层的部分。但是，从电的观点来看，此连接性类似于在图7的实施例中展示的源极接触件52和导体50的组合，其中图13的实施例也将源极电势连接到GaN晶体管的底部处的单侧PN结。同样结合图13，在形成源极接触件128的相同(或相当)过程中，类似地使用导体(优选地为金属)填充漏极蚀刻(未展示)以形成延伸到势垒层34中(但不完全穿过)的漏极接触件130，以形成到低缺陷层32中的二维电子气体的穿隧连接。最后，在源极接触件128和漏极接触件130的每个相应组之间形成栅极导体132，其中每个此栅极导体132与栅极电介质层38接触。
图14图示说明添加到图13中展示的结构的最终示例实施例结构。具体来说，在图13中，形成具有适当掩模(未展示)的穿过衬底122的上表面的额外电浮动n+区134，其中在图示说明的实例中，在一般被指示为包含两个GaN FET(一般展示为T”1和T”2)的晶体管对20之间及其外边缘外侧形成三个此类区。电浮动n+区134操作以在耗尽发生且开始在表面扩大时展开电场，使得每个区可获得跨每个晶体管施加的电势之间的某一电压(例如，0到600伏特)。如此，表面场减小，使得低于针对装置可靠性所需的特定级别。
根据上文，各种实施例提供对III-N族半导体晶体管(例如GaN FET)的改进。虽然已经提供各种尺寸，但是可根据应用及其它考虑调整此类量度。例如，虽然已经描述示例实施例半桥，但是示例实施例结构可配合个别FET、其它配置中的FET和与除相对于同样衬底形成的FET外的装置组合的FET使用，但使用示例实施例教示将此FET与此类装置隔离。实际上，本文描述的各种晶体管组件也可在2014年6月24日发布的美国专利案第8,759,879号中找到，所述案借此以引用的方式并入本文中；此引用专利案包含也可和此文献的教示轻易组合的其它晶体管配置。另举一个例子，虽然已经关于衬底描述示例实施例单侧PN结作为结的部分，但是在另一示例实施例中，可使用与衬底脱离的GaN层达成所述结。例如，在p+硅或适当衬底的顶部上生长p型/SI-GaN或AlGaN层，其中接着通过外延或植入在所述p型或SI-GaN的表面上形成n+层。而后，所有其它层可类似于上文描述的所述层，其中在此替代方案中，将形成通孔来接触n+III族氮化物层。
在所描述实施例中的修改是可能的，且在权利要求书的范围内的其它实施例是可能的。

Claims (10)

1.一种半导体装置，其包括：
第一导电类型的衬底；
第二导电类型的掺杂层，其位于所述衬底上，所述第二导电类型与所述第一导电类型相反；
氮化镓层，其位于所述掺杂层上；
势垒层，其包含形成于所述氮化镓层上的III-N族半导体材料；
所述第二导电类型的第一掺杂区域，所述第一掺杂区域沿着所述氮化镓层的第一边缘和所述势垒层的第一边缘从所述衬底的表面延伸到所述掺杂层；
源极接触件，其部分地延伸穿过所述势垒层并连接到所述第一掺杂区域。
2.根据权利要求1所述的半导体装置，其进一步包括：
所述第二导电类型的第二掺杂区域，所述第二掺杂区域沿着所述氮化镓层的第二边缘和所述势垒层的第二边缘从所述衬底的所述表面延伸到所述掺杂层。
3.根据权利要求2所述的半导体装置，其中所述掺杂层和连接到所述掺杂层的所述第一和第二掺杂区域形成至少部分地环绕所述氮化镓层和所述势垒层的U形隔离结构。
4.根据权利要求2所述的半导体装置，其进一步包括：
漏极接触件；以及
栅极接触件，其位于所述源极接触件与所述漏极接触件之间；其中：
晶体管，其形成于所述第一掺杂区域和所述第二掺杂区域之间，所述晶体管包含所述源极接触件、所述漏极接触件以及所述栅极接触件。
5.根据权利要求4所述的半导体装置，其中所述掺杂层和连接到所述掺杂层的所述第一和第二掺杂区域在与所述衬底的界面处形成PN结，所述PN结能够经配置以在所述晶体管的操作期间反向偏压。
6.根据权利要求1所述的半导体装置，其中：
所述源极接触件延伸穿过所述势垒层的大部分厚度而不达到所述氮化镓层；以及
穿隧连接，其形成于所述源极接触件和所述氮化镓层中的二维电子气体之间。
7.根据权利要求1所述的半导体装置，其进一步包括：
所述第二导电类型的一或多个电浮动掺杂区域，其穿过所述衬底的所述表面设置。
8.一种半导体装置，其包括：
第一导电类型的衬底；
氮化镓层，其位于所述衬底上；
势垒层，其包含形成于所述氮化镓层上的III-N族半导体材料；
U形隔离结构，其至少部分地环绕所述氮化镓层和所述势垒层，其中所述U形隔离结构包含形成于所述U形隔离结构和所述衬底之间的PN结；以及
晶体管，其位于所述U形隔离结构内，所述晶体管包含：
源极接触件，其电耦合到所述U形隔离结构；
漏极接触件；以及
栅极接触件，其位于所述源极接触件和所述漏极接触件之间，其中：
所述源极接触件延伸穿过所述势垒层的大部分厚度而不达到所述氮化镓层；以及
穿隧连接，其形成于所述源极接触件和所述氮化镓层中的二维电子气体之间。
9.根据权利要求8所述的半导体装置，其中所述PN结能够经配置以在所述晶体管的操作期间反向偏压。
10.根据权利要求8所述的半导体装置，其中U形隔离结构包括：
第二导电类型的掺杂层，其接触所述衬底，所述氮化镓层位于所述掺杂层上；
所述第二导电类型的第一掺杂区域，所述第一掺杂区域沿着所述氮化镓层的第一边缘和所述势垒层的第一边缘从所述衬底的表面延伸到所述掺杂层；以及
所述第二导电类型的第二掺杂区域，所述第二掺杂区域沿着所述氮化镓层的第二边缘和所述势垒层的第二边缘从所述衬底的所述表面延伸到所述掺杂层。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10453824B1 (en) * 2018-05-08 2019-10-22 International Business Machines Corporation Structure and method to form nanosheet devices with bottom isolation
JP7426786B2 (ja) * 2019-05-30 2024-02-02 ローム株式会社 窒化物半導体装置
TW202111949A (zh) * 2019-09-04 2021-03-16 聯華電子股份有限公司 增強型高電子遷移率電晶體
US11296190B2 (en) * 2020-01-15 2022-04-05 Globalfoundries U.S. Inc. Field effect transistors with back gate contact and buried high resistivity layer
US11251294B2 (en) * 2020-03-24 2022-02-15 Infineon Technologies Austria Ag High voltage blocking III-V semiconductor device
WO2021243654A1 (en) * 2020-06-04 2021-12-09 Innoscience (Zhuhai) Technology Co., Ltd. Semiconductor device and manufacturing method thereof
FR3111738B1 (fr) 2020-06-19 2022-08-05 Commissariat Energie Atomique Dispositif micro-électronique à substrat isolé, et procédé de fabrication associé
US11515397B2 (en) 2020-07-21 2022-11-29 Globalfoundries U.S. Inc. III-V compound semiconductor layer stacks with electrical isolation provided by a trap-rich layer
US11469225B2 (en) 2020-10-16 2022-10-11 Globalfoundries U.S. Inc. Device integration schemes leveraging a bulk semiconductor substrate having a <111 > crystal orientation
US11569374B2 (en) 2020-12-02 2023-01-31 Globalfoundries U.S. Inc. Implanted isolation for device integration on a common substrate
US20240047451A1 (en) * 2021-08-06 2024-02-08 Innoscience (Suzhou) Technology Co., Ltd. Nitride-based semiconductor ic chip and method for manufacturing the same

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276340A (en) * 1989-11-21 1994-01-04 Fujitsu Limited Semiconductor integrated circuit having a reduced side gate effect
US5077231A (en) * 1991-03-15 1991-12-31 Texas Instruments Incorporated Method to integrate HBTs and FETs
US7030428B2 (en) * 2001-12-03 2006-04-18 Cree, Inc. Strain balanced nitride heterojunction transistors
JP4449467B2 (ja) * 2004-01-28 2010-04-14 サンケン電気株式会社 半導体装置
US8575651B2 (en) * 2005-04-11 2013-11-05 Cree, Inc. Devices having thick semi-insulating epitaxial gallium nitride layer
US7466212B2 (en) * 2006-06-16 2008-12-16 Semiconductor Components Industries, L. L. C. Semiconductor filter structure and method of manufacture
WO2010001607A1 (ja) * 2008-07-03 2010-01-07 パナソニック株式会社 窒化物半導体装置
US20100117118A1 (en) * 2008-08-07 2010-05-13 Dabiran Amir M High electron mobility heterojunction device
US8564020B2 (en) * 2009-07-27 2013-10-22 The Hong Kong University Of Science And Technology Transistors and rectifiers utilizing hybrid electrodes and methods of fabricating the same
WO2011061573A1 (en) * 2009-11-19 2011-05-26 Freescale Semiconductor, Inc. Vertical power transistor device, semiconductor die and method of manufacturing a vertical power transistor device
JP2011165749A (ja) * 2010-02-05 2011-08-25 Panasonic Corp 半導体装置
DE112011104408T5 (de) * 2010-12-15 2013-10-24 Efficient Power Conversion Corporation Halbleitervorrichtungen mit rückseitiger Isolierung
US8536674B2 (en) * 2010-12-20 2013-09-17 General Electric Company Integrated circuit and method of fabricating same
CN104395993B (zh) * 2012-06-20 2017-09-19 独立行政法人产业技术综合研究所 半导体装置
US8933461B2 (en) * 2012-08-09 2015-01-13 Texas Instruments Incorporated III-nitride enhancement mode transistors with tunable and high gate-source voltage rating
US9202906B2 (en) * 2013-03-14 2015-12-01 Northrop Grumman Systems Corporation Superlattice crenelated gate field effect transistor
US9035318B2 (en) * 2013-05-03 2015-05-19 Texas Instruments Incorporated Avalanche energy handling capable III-nitride transistors
US8759879B1 (en) * 2013-05-03 2014-06-24 Texas Instruments Incorporated RESURF III-nitride HEMTs
KR20150011238A (ko) * 2013-07-22 2015-01-30 삼성전자주식회사 질화물계 반도체 장치
US9997507B2 (en) * 2013-07-25 2018-06-12 General Electric Company Semiconductor assembly and method of manufacture
JP6143598B2 (ja) * 2013-08-01 2017-06-07 株式会社東芝 半導体装置
JP2015060920A (ja) * 2013-09-18 2015-03-30 株式会社デンソー 半導体装置およびその製造方法
WO2015125492A1 (ja) * 2014-02-24 2015-08-27 パナソニック株式会社 半導体装置

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