CN116679789A - Band-gap reference voltage source adopting second-order temperature compensation and working method thereof - Google Patents
Band-gap reference voltage source adopting second-order temperature compensation and working method thereof Download PDFInfo
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Abstract
A band-gap reference voltage source adopting second-order temperature compensation and a working method thereof are provided, wherein a bias circuit comprises a positive-pressure bias current generating circuit, a core reference circuit comprises a feedback control operational amplifier circuit, and the feedback control operational amplifier circuit comprises a positive-pressure generating circuit and a negative-pressure generating circuit; the difference value between the base-emitter voltages of two triodes in the positive voltage generating circuit is a first voltage difference, and the first voltage difference carries out first-order compensation on the negative temperature coefficient voltage generated by the triodes in the negative voltage generating circuit; the difference value between the base-emitter voltages of two triodes in the positive-voltage bias current generating circuit generates bias current with positive temperature coefficient on a resistor; the bias current generates a second voltage difference when flowing through a resistor in the positive voltage generating circuit, and the second voltage difference performs second-order temperature compensation on the negative temperature coefficient voltage after the first-order compensation, wherein the first voltage difference and the second voltage difference are both positive temperature coefficient voltages. The application obtains the reference voltage with lower temperature drift coefficient through secondary temperature compensation.
Description
Technical Field
The application belongs to the technical field of integrated circuit band-gap reference voltage sources, and particularly relates to a band-gap reference voltage source adopting second-order temperature compensation and a working method thereof.
Background
The bandgap reference voltage source is one of the most basic and important modules in a digital-to-analog circuit, and is mainly used for providing stable bias voltage for the circuit. Therefore, the performance of the bandgap reference voltage source has a crucial impact on the performance and accuracy of the circuit.
With the wide application of electronic products in the life of people, the band gap reference voltage source serving as a chip core module is also increasingly demanded. In addition, the environmental temperature at which the chip is located can also vary greatly due to the environmental temperature variation and the heat generated by the electronic system. In order to ensure that the circuit can stably work within a certain temperature range, a band gap reference voltage source circuit with a low temperature drift coefficient is an integral part of the current chip field.
In the prior art, most band gap reference voltage source devices adopt a first-order temperature compensation principle, a band gap reference voltage source with the first-order temperature compensation comprises a clamping operational amplifier circuit and a positive and negative voltage generating circuit, wherein the positive and negative voltage generating circuit comprises a resistor and two triodes, and under the same current density, the voltage difference delta V between the base electrodes and the emitter electrodes of the two triodes BE Base-emitter voltage V of single triode as positive temperature coefficient voltage BE Is a voltage with negative temperature coefficient by adjusting the voltage delta V with positive temperature coefficient BE And the coefficient value of the voltage regulator is offset with the negative temperature coefficient voltage, and finally a low-temperature drift reference voltage is obtained and is used as the reference voltage of the whole circuit. In the existing products, the temperature drift coefficient of the reference voltage of most of the first-order compensated band-gap reference voltage sources is 5-10 ppm/DEG C, and more stable reference voltage can be output in a certain temperature range, however, in the application fields with larger temperature change, such as the thermoelectric energy collection field, the industrial field and the like, band-gap reference voltage sources with lower temperature drift coefficients are needed. Because the first-order temperature compensation circuit in the prior art has a complex structure, if temperature compensation is to be further realized, other circuits are needed to be additionally arranged, meanwhile, the output end of the first-order compensated band-gap reference voltage source is common source output, the output impedance of the circuit is extremely high, the band-gap reference voltage source has extremely weak carrying capacity, once the band-gap reference voltage source carries, the reference voltage value can change greatly and cannot be kept stable, so that the band of the first-order compensation is providedThe bandgap reference voltage source does not have the load capability.
Disclosure of Invention
In order to solve the defects existing in the prior art, the application provides a band-gap reference voltage source adopting second-order temperature compensation and a working method thereof, and the voltage difference delta V between the base electrode and the emitter electrode of a triode is based on the existing first-order compensation BE Generating bias current with positive temperature coefficient, performing secondary temperature compensation on the band gap reference voltage source, further reducing the temperature drift coefficient of the reference voltage source, obtaining reference voltage with lower temperature drift coefficient, and stably outputting the reference voltage value in the temperature range of-20 ℃ to 130 ℃.
The application adopts the following technical scheme.
The application provides a band-gap reference voltage source adopting second-order temperature compensation, which comprises: a start-up circuit, a bias circuit, and a core reference circuit;
the bias circuit comprises a positive pressure bias current generating circuit, the core reference circuit comprises a feedback control operational amplifier circuit, and the feedback control operational amplifier circuit comprises a positive pressure generating circuit and a negative pressure generating circuit;
the positive voltage generating circuit comprises two triodes and a resistor, and the negative voltage generating circuit comprises a triode; the difference value between the base-emitter voltages of two triodes in the positive voltage generating circuit is a first voltage difference, and the first voltage difference carries out first-order compensation on the negative temperature coefficient voltage generated by the triodes in the negative voltage generating circuit; the positive-pressure bias current generating circuit comprises two triodes and a resistor, wherein the difference value between the base-emitter voltages of the two triodes in the positive-pressure bias current generating circuit generates bias current with positive temperature coefficient on the resistor; the bias current generates a second voltage difference when flowing through a resistor in the positive voltage generating circuit, and the second voltage difference performs second-order temperature compensation on the negative temperature coefficient voltage after the first-order compensation, wherein the first voltage difference and the second voltage difference are both positive temperature coefficient voltages.
The triode at the output end of the reference voltage source adopts a common collector wiring.
The starting circuit comprises: first to fifth MOS transistors M1, M2, M3, M4, M5, a first capacitor C1; the source electrode of M1 is connected with the power supply VDD, the drain electrode of M1 is connected with the source electrode of M2, the drain electrode of M2 is connected with the source electrode of M3, the grid electrodes of M1, M2 and M3 are all grounded, one end of C1 is connected with the drain electrode of M3, the other end of C1 is grounded, the source electrode of M4 is connected with the power supply VDD, the grid electrode of M4 is grounded, the drain electrode of M4 is connected with the source electrode of M5, the grid electrode of M5 is connected with the drain electrode of M3, and the drain electrode of M5 is connected with the bias circuit.
The starting circuit only works in the starting process of the band-gap reference voltage source, and is completely turned off after the band-gap reference voltage source is started.
The bias circuit includes: sixteenth to sixteenth MOS transistors M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, first to fourth transistors Q1, Q2, Q3, Q4, first to third resistors R1, R2, R3; wherein M11, M12, M13, M14, M15, M16 and R3 form a mirror circuit. The source electrode of M6 is connected with the source electrode of the power supply VDD, the drain electrode of M6 is connected with the source electrode of M7, the gate electrode of M6 is connected with the gate electrode of M9, the gate electrode of M7 is connected with the gate electrode of M10, the drain electrode of M7 is connected with the source electrode of M8, the drain electrode of M8 is connected with the drain electrode of M5 in the starting circuit, the drain electrode of M8 is connected with the collector electrode of Q1, the base electrode of Q1 is connected with the collector electrode of Q1, the emitter electrode of Q1 is connected with the collector electrode of Q2, the emitter electrode of Q2 is grounded, the base electrode of Q2 is connected with the collector electrode of Q4, the source electrode of M9 is connected with the power supply VDD, the drain electrode of M9 is connected with the source electrode of M10, the gate electrode of M9 is connected with the drain electrode of M10, the drain electrode of M10 is connected with one end of R1, the other end of R1 is connected with the collector electrode of Q3, the base electrode of Q3 is connected with the base electrode of Q1, the base of Q4 is connected with the collector of Q2, the emitter of Q4 is connected with one end of R2, the other end of R2 is grounded, the source of M11 is connected with the power supply VDD, the gate of M11 is connected with the gate of M9, the drain of M11 is connected with the drain of M12, the gate of M12 is connected with the drain of M12, the source of M12 is connected with the drain of M13, the gate of M13 is connected with the gate of M12, the source of M13 is grounded, the source of M14 is connected with the power supply VDD, the gate of M14 is connected with the core reference circuit after being short-circuited, one end of R3 is connected with the drain of M14, the other end of R3 is connected with the drain of M15, the gate of M15 is connected with the gate of M13, the source of M15 is connected with the drain of M16, the gate of M16 is connected with the gate of M13 and is connected with the core reference circuit, and the source of M16 is grounded.
A bias circuit for generating a positive temperature coefficient bias current Ibias across the resistor R2 using the difference between the base-emitter voltage differences of the transistors Q2, Q4 in the bias circuit.
The core reference circuit includes: seventeenth to twenty-third MOS transistors M17, M18, M19, M20, M21, M22, M23, fifth to thirteenth transistors Q5, Q6, Q7, Q8, Q9, Q10, fourth to eighth resistors R4, R5, R6, R7, R8, and a second capacitor C2; the source electrode of M17 is connected with the power supply VDD, the grid electrode of M17 is short-circuited with the drain electrode, the drain electrode of M17 is connected with the collector electrode of Q5, the base electrode of Q5 is connected with one end of R7, the emitter electrode of Q5 is connected with the drain electrode of M18, the grid electrode of M18 is connected with the grid electrode of M16 in the starting circuit, the source electrode of M18 is grounded, the source electrode of M19 is connected with the power supply VDD, the grid electrode of M19 is connected with the grid electrode of M17, the drain electrode of M19 is connected with the collector electrode of Q6, the base electrode of Q6 is connected with one end of R8, the emitter electrode of Q6 is connected with one end of R4, the other end of R4 is connected with the drain electrode of M18, the source electrode of M20 is connected with the grid electrode of M114, the drain electrode of M20 is connected with one end of R5, the other end of R5 is connected with the collector electrode of Q7 and the base electrode of Q7, the base electrode of Q7 is in short circuit with the collector electrode of Q7, the base and collector of Q8 are short-circuited, the emitter of Q8 is connected with the drain of M21, the gate of M21 is connected with the collector of Q6, the source of M21 is grounded, one end of C2 is connected with the gate of M21, the other end of C2 is connected with the drain of M21, the source of M22 is connected with the power supply VDD, the gate of M22 is connected with the gate of M20, the drain is connected with the collector of Q9, the base of Q9 is connected with the drain of M20, the emitter of Q9 is connected with the drain of M23, the gate of M23 is connected with the gate of M16 in the starting circuit, the source of M23 is grounded, R6, R7 and R8 are connected in series, one end of R6 is connected with the emitter of Q9 and is also the output end of a reference voltage source, one end of R8 is connected with the base and collector of Q10, the base and collector of Q10 are short-circuited, and the emitter of Q10 is grounded.
In the core reference circuit, the bias current Ibias and the compensation resistor R4 carry out second-order compensation on the band-gap reference voltage source.
In the core reference circuit, M17, M19, M18, R4, Q5, and Q6 constitute a first stage feedback control amplifier, Q5, and Q6 constitute a differential input pair, M20, M21, R5, C2, Q7, and Q8 constitute a second stage feedback control amplifier, and M22, M23, R6, R7, R8, Q9, and Q10 constitute a third stage feedback control amplifier.
Q9 employs a common collector approach.
M13 and M18 form a current mirror structure, and M17 and M19 also form a current mirror structure.
The application also provides a working method of the band-gap reference voltage source adopting the second-order temperature compensation, which comprises the following steps:
step 1, after a starting circuit is conducted, a power supply charges a bias circuit and a core reference circuit;
step 2, in the positive voltage generating circuit, the difference between the base-emitter voltages of the two triodes Q5 and Q6 is a first voltage difference, and the output voltage of the reference voltage source is formed by the divided voltage of the first voltage difference on R6, R7 and R8 and the collector voltage of Q10; wherein the first voltage difference is a positive temperature coefficient voltage and the collector voltage of Q10 is a negative temperature coefficient voltage;
step 3, in the bias circuit, the difference between the base-emitter voltages of the two triodes Q2, Q4 generates a bias current with positive temperature coefficient on the resistor R2; generating a second voltage difference when the bias current flows through a resistor R4 in the positive voltage generating circuit, wherein the second voltage difference is positive temperature coefficient voltage; and the second voltage difference carries out second-order temperature compensation on the negative temperature coefficient voltage after the first-order compensation to obtain the reference voltage output by the band-gap reference voltage source.
When the bias current is established, the core reference circuit starts to work and outputs a reference voltage. At this time, C1 is charged to the power supply voltage VDD, M5 is turned off, and the start-up circuit stops operating.
Based on the current mirror structure in the bias circuit and the core reference circuit, the current flowing through the emitter of Q6 under the action of the first voltage difference is the bias currentMultiple, where M is the ratio of the aspect ratio of M17 to M19 in the current mirror structure, N 3 Is the ratio of the aspect ratio of M18 to M13 in the current mirror structure.
The band-gap reference voltage source has the beneficial effects that the circuit structure of the band-gap reference voltage source with the first-order temperature compensation is not changed, other circuits are not needed to be added, and the band-gap reference voltage source with a simpler structure is realized by combining the clamping operational amplifier, the positive and negative voltage generating circuit and the second-order temperature compensation circuit in the core reference circuit.
The application provides a band gap structure for carrying out temperature compensation on a triode source electrode at an operational amplifier input end, which realizes second-order compensation on a band gap reference voltage source, and realizes stable output of reference voltage within a wide temperature range of-20 ℃ to 130 ℃, wherein the temperature drift coefficient is only 1.572ppm/°c.
The curve of the reference voltage output by the band gap reference voltage source along with the temperature change is similar to a sine function curve.
The output end of the reference voltage source provided by the application adopts a common collector connection method, the output impedance of the circuit is extremely low, the carrying capacity is relatively strong, and the stability of the output voltage is not affected.
The band-gap reference voltage source adopts a low-power-consumption design, the starting circuit only works in the starting process of the band-gap reference voltage source, and the starting circuit is completely turned off after the band-gap reference voltage source is started, so that zero power consumption is realized, and the power consumption of the whole circuit is reduced.
Drawings
FIG. 1 is a schematic diagram of a low temperature drift band gap reference voltage source employing second order temperature compensation according to the present application;
FIG. 2 is a schematic diagram of a start-up circuit of a low temperature drift bandgap reference voltage source employing second order temperature compensation in accordance with the present application;
FIG. 3 is a schematic diagram of a bias circuit of a low temperature drift bandgap reference voltage source employing second order temperature compensation in accordance with the present application;
FIG. 4 is a diagram of a core reference circuit of a low temperature drift bandgap reference voltage source employing second order temperature compensation in accordance with the present application;
FIG. 5 is a timing diagram of the output voltage set up when the power supply VDD is powered up according to an embodiment of the application;
FIG. 6 is a graph of the output voltage of a second order temperature compensated bandgap reference voltage source with temperature change in an embodiment of the application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. The described embodiments of the application are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art without inventive faculty, are within the scope of the application, based on the spirit of the application.
The present application provides a bandgap reference voltage source employing second order temperature compensation, as shown in fig. 1, the reference voltage source comprising: the device comprises a starting circuit, a biasing circuit, a core reference circuit and a mirror circuit. The bias circuit comprises a positive pressure bias current generating circuit, the core reference circuit comprises a feedback control operational amplifier circuit, and the feedback control operational amplifier circuit comprises a positive pressure generating circuit and a negative pressure generating circuit.
The positive voltage generating circuit comprises two triodes and a resistor, and the negative voltage generating circuit comprises a triode; the difference value between the base-emitter voltages of two triodes in the positive voltage generating circuit is a first voltage difference, and the first voltage difference carries out first-order compensation on the negative temperature coefficient voltage generated by the triodes in the negative voltage generating circuit; the positive-pressure bias current generating circuit comprises two triodes and a resistor, wherein the difference value between the base-emitter voltages of the two triodes in the positive-pressure bias current generating circuit generates bias current with positive temperature coefficient on the resistor; the bias current generates a second voltage difference when flowing through a resistor in the positive voltage generating circuit, and the second voltage difference performs second-order temperature compensation on the negative temperature coefficient voltage after the first-order compensation, wherein the first voltage difference and the second voltage difference are both positive temperature coefficient voltages.
The triode at the output end of the reference voltage source adopts a common collector wiring.
The clamping operational amplifier and the positive and negative voltage generating circuit are fused to obtain the feedback control operational amplifier circuit, and the positive temperature coefficient positive pressure bias current generating circuit is designed in the bias circuit to obtain the band gap reference voltage source with a brand new structure. The band gap reference voltage source provided by the application does not need an external circuit, realizes the combination of the clamping operational amplifier, the positive and negative voltage generating circuit and the second-order temperature compensation circuit, has simpler structure, and can obtain the reference voltage with lower temperature drift coefficient. And the output end of the band gap reference voltage source adopts a common collector connection method, so that the band gap reference voltage source has stronger carrying capacity.
Specifically, as shown in fig. 2, the start-up circuit includes: first to fifth MOS transistors M1, M2, M3, M4, M5, and a first capacitor C1. The source of M1 is connected to the power supply VDD (as shown in FIG. 3), the drain of M1 is connected to the source of M2, the drain of M2 is connected to the source of M3, and the gates of M1, M2 and M3 are all grounded. One end of C1 is connected with the drain electrode of M3, and the other end of C1 is grounded. The source electrode of M4 is connected with the power supply VDD, the grid electrode of M4 is grounded, the drain electrode of M4 is connected with the source electrode of M5, the grid electrode of M5 is connected with the drain electrode of M3, and the drain electrode of M5 is connected with the bias circuit.
The starting circuit only works in the starting process of the band-gap reference voltage source, and is completely turned off after the band-gap reference voltage source is started, so that zero power consumption is realized, and the power consumption of the whole circuit is reduced.
As shown in fig. 3, the bias circuit includes: sixth to sixteenth MOS transistors M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, first to fourth transistors Q1, Q2, Q3, Q4, and first to third resistors R1, R2, R3. The source electrode of M6 is connected with the power supply VDD, the drain electrode of M6 is connected with the source electrode of M7, and the grid electrode of M6 is connected with the grid electrode of M9. The grid electrode of M7 is connected with the grid electrode of M10, the drain electrode of M7 is connected with the source electrode of M8, the drain electrode of M8 is connected with the drain electrode of M5 in the starting circuit, the drain electrode of M8 is connected with the collector electrode of Q1, the base electrode of Q1 is connected with the collector electrode of Q1, the emitter electrode of Q1 is connected with the collector electrode of Q2, the emitter electrode of Q2 is grounded, and the base electrode of Q2 is connected with the collector electrode of Q4. The source of M9 is connected with the power supply VDD, the drain of M9 is connected with the source of M10, and the gate of M9 is connected with the drain of M10. The drain electrode of M10 is connected with one end of R1, the grid electrode of M10 is connected with the other end of R1, and the other end of R1 is connected with the collector electrode of Q3. The base of Q3 is connected with the base of Q1, the emitter of Q3 is connected with the collector of Q4, the base of Q4 is connected with the collector of Q2, the emitter of Q4 is connected with one end of R2, the other end of R2 is grounded, when current flows through Q2 and Q4, the voltage difference between the base-emitter voltage difference of Q2 and the base-emitter voltage difference of Q4 generates bias current Ibias on R2. The source electrode of M11 is connected with the power supply VDD, the grid electrode of M11 is connected with the grid electrode of M9, the drain electrode of M11 is connected with the drain electrode of M12, the grid electrode of M12 is connected with the drain electrode of M12, the source electrode of M12 is connected with the drain electrode of M13, the grid electrode of M13 is connected with the grid electrode of M12, and the source electrode of M13 is grounded. The source electrode of M14 is connected with a power supply VDD, the grid electrode and the drain electrode of M14 are connected with a core reference circuit after being short-circuited, one end of R3 is connected with the drain electrode of M14, the other end of R3 is connected with the drain electrode of M15, the grid electrode of M15 is connected with the grid electrode of M13, the source electrode of M15 is connected with the drain electrode of M16, the grid electrode of M16 is connected with the grid electrode of M13 and is connected with the core reference circuit, and the source electrode of M16 is grounded; m11, M12, M13, M14, M15, M16 and R3 form a mirror circuit.
A bias circuit for generating a positive temperature coefficient bias current Ibias across the resistor R2 using the difference between the base-emitter voltage differences of the transistors Q2, Q4 in the bias circuit.
Wherein the area ratio of the emitting junctions of the triodes Q4 and Q2 is N 1 。
Specifically, as shown in fig. 4, the core reference circuit includes: seventeenth to twenty-third MOS transistors M17, M18, M19, M20, M21, M22, M23, fifth to thirteenth transistors Q5, Q6, Q7, Q8, Q9, Q10, fourth to eighth resistors R4, R5, R6, R7, R8, and a second capacitor C2. The source electrode of M17 is connected with the power supply VDD, the grid electrode of M17 is short-circuited with the drain electrode, the drain electrode of M17 is connected with the collector electrode of Q5, the base electrode of Q5 is connected with one end of R7, the emitter electrode of Q5 is connected with the drain electrode of M18, the grid electrode of M18 is connected with the grid electrode of M16 in the starting circuit, and the source electrode of M18 is grounded. The source of M19 is connected to the power supply VDD, the gate of M19 is connected to the gate of M17, and the drain of M19 is connected to the collector of Q6. The base of Q6 is connected with one end of R8, the emitter of Q6 is connected with one end of R4, and the other end of R4 is connected with the drain electrode of M18. The source electrode of M20 is connected with the power supply VDD, the grid electrode of M20 is connected with the grid electrode of M114, the drain electrode of M20 is connected with one end of R5, the other end of R5 is connected with the collector electrode and the base electrode of Q7, the base electrode and the collector electrode of Q7 are in short circuit, the emitter electrode of Q7 is connected with the base electrode and the collector electrode of Q8, the base electrode and the collector electrode of Q8 are in short circuit, the emitter electrode of Q8 is connected with the drain electrode of M21, the grid electrode of M21 is connected with the collector electrode of Q6, and the source electrode of M21 is grounded. One end of C2 is connected with the grid electrode of M21, and the other end of C2 is connected with the drain electrode of M21. The source electrode of M22 is connected with the power supply VDD, the grid electrode of M22 is connected with the grid electrode of M20, the drain electrode is connected with the collector electrode of Q9, the base electrode of Q9 is connected with the drain electrode of M20, the emitter electrode of Q9 is connected with the drain electrode of M23, the grid electrode of M23 is connected with the grid electrode of M16 in the starting circuit, and the source electrode of M23 is grounded. R6, R7 and R8 are connected in series, one end of R6 is connected with the emitter of Q9 and is also the output end of a reference voltage source, the reference voltage VREF is output, one end of R8 is connected with the base electrode and the collector electrode of Q10, the base electrode and the collector electrode of Q10 are short-circuited, and the emitter of Q10 is grounded.
In the core reference circuit, the bias current Ibias and the compensation resistor R4 carry out second-order temperature compensation on the band-gap reference voltage source, so that the output voltage of the band-gap reference voltage source is more stable than that of a first-order band-gap reference voltage source in a wider temperature range.
The core reference circuit is formed by fusing a positive pressure generating circuit and a negative pressure generating circuit into a traditional secondary clamping operational amplifier circuit to obtain a feedback control operational amplifier circuit, wherein the core reference circuit with a first-order temperature compensation band gap reference voltage source in the prior art consists of the secondary clamping operational amplifier circuit and a positive and negative pressure generating circuit, and the secondary clamping operational amplifier circuit and the positive and negative pressure generating circuits are separated and independent and are not fused. Therefore, the core reference circuit provided by the application can realize a simpler circuit structure without an additional circuit structure on the basis of realizing second-order temperature compensation.
In the embodiment of the application, a positive pressure generating circuit and a negative pressure generating circuit are fused into a traditional two-stage clamping operational amplifier circuit to obtain a feedback control operational amplifier circuit, which comprises the following steps: m17, M19, M18, Q5 and Q6 form a first stage feedback control amplifier, and Q5 and Q6 form a differential input pair. M20, M21, R5, C2, Q7 and Q8 constitute a second stage feedback control amplifier, and M22, M23, R6, R7, R8, Q9 and Q10 constitute a third stage feedback control amplifier.
Q9 at the output end of the band-gap reference voltage source adopts a common collector connection method, and the output impedance is extremely small, so that the band-gap reference voltage source has relatively strong load capacity.
Further, the area ratio of the emission junctions of Q6 and Q5 is N 2 。
Further, M13 and M18 form a current mirror structure, and the ratio of the width to length of M18 to M13 is N 3 M17 and M19 also form a current mirror structure, and the ratio of the width to length of M17 to M19 is M.
The application also provides a working method of the band-gap reference voltage source adopting the second-order temperature compensation, which comprises the following steps:
and step 1, after the starting circuit is conducted, the power supply charges the bias circuit and the core reference circuit.
Specifically, as shown in fig. 2, when the start-up circuit is just powered on, the gates of M1, M2, M3, and M4 are all grounded, M1, M2, M3, and M4 are all turned on, and C1 starts charging. The gate of M5 is connected to one end of C1, and initially the gate of M5 is low, M5 is turned on, and power supply VDD begins to charge the parasitic capacitance from the collector of Q1 to ground.
Step 2, in the positive voltage generating circuit, the difference between the base-emitter voltages of the two triodes Q5 and Q6 is a first voltage difference, and the output voltage of the reference voltage source is formed by the divided voltage of the first voltage difference on R6, R7 and R8 and the collector voltage of Q10; wherein the first voltage difference is a positive temperature coefficient voltage and the collector voltage of Q10 is a negative temperature coefficient voltage;
specifically, as shown in FIG. 4, the base-emitter voltage difference DeltaV of Q5 BE5 Base-emitter voltage difference DeltaV with Q6 BE6 A first voltage difference DeltaV between BE5-6 The following are provided:
ΔV BE5-6 ＝AV BE5 -ΔV BE6 ＝V T ln(N 2 M)+I 6 *R4
in the method, in the process of the application,
V T in the form of a thermal voltage, the temperature of the fluid is,
N 2 the ratio of the emitter junction areas of Q6 to Q5,
m is the ratio of the width to length ratio of the MOS transistors M17 and M19,
I 6 for the current flowing through the emitter of transistor Q6,
r4 is the resistance value of resistor R4.
Specifically, as shown in FIG. 4, the reference voltage VREF is composed of the voltages on R6, R7, and R8 and the collector voltage V of Q10 BE10 Composition is prepared. The current flowing through R6, R7, R8 and transistor Q10 is a first voltage difference DeltaV BE5-6 The action is formed on R7, so the reference voltages are as follows:
in the method, in the process of the application,
r6, R7, R8 are the resistance values of the resistors R6, R7, R8, respectively.
The first voltage difference performs first-order compensation on the negative temperature coefficient voltage generated by the triode Q10 in the negative voltage generating circuit.
Step 3, in the bias circuit, the difference between the base-emitter voltages of the two triodes Q2, Q4 generates a bias current with positive temperature coefficient on the resistor R2; the bias current flows through a resistor R4 in the positive voltage generating circuit to generate a second voltage difference, and the second voltage difference performs second-order temperature compensation on the negative temperature coefficient voltage after the first-order compensation, wherein the second voltage difference is positive temperature coefficient voltage.
Specifically, as shown in FIG. 3, the collector of Q1 is raised, when the potential of Q1 is greater than the threshold voltage 0.7V, the branch where Q1 is located is turned on, while the branch where Q3 is located is turned on, and when current flows through Q2 and Q4, the base-emitter voltage difference DeltaV of Q2 BE Base-emitter voltage difference DeltaV with Q4 BE4 A second voltage difference DeltaV therebetween BE2-4 Generating a bias current Ibias at the resistor R2 due to the second voltage difference DeltaV BE2-4 Is a positive temperature coefficient, so the generated bias current is proportional to temperature, as follows:
in the method, in the process of the application,
N 1 is the ratio of the emitter junction areas of transistors Q4 and Q2,
V T in the form of a thermal voltage, the temperature of the fluid is,
q is the electric quantity of electrons,
k is the boltzmann constant,
t is the thermodynamic temperature of the mixture,
r2 is the resistance value of resistor R2.
Based on the current mirror structure in the bias circuit and the core reference circuit, the current flowing through the emitter of Q6 under the action of the first voltage difference is the bias currentMultiple of, wherein M is currentRatio of width-length ratio of mirror structure MOS tube M17 to M19, N 3 Is the ratio of the width to length ratio of the MOS transistors M18 and M13 with the current mirror structure.
Specifically, as shown in fig. 3 and 4, M13 and M18 form a current mirror structure, and M17 and M19 also form a current mirror structure, so that a current I flows through the emitter of Q6 6 Is the current flowing through M13Multiple times.
The reference voltage is converted into:
in the expression of VREF, V T Positively correlated with temperature, V BE10 Inversely related to temperature. Therefore, the reference voltage derives the temperature as follows:
in the method, in the process of the application,
N 2 is the ratio of the emitter junction areas of transistors Q6 and Q5,
N 3 is the ratio of the width to length ratio of the MOS transistors M18 and M13 of the current mirror structure,
R eq for the resistance ratio, the following is satisfied:the resistance ratio is small relative to the temperature change and can be ignored.
Is a positive temperature coefficient term, ">Is a negative temperature coefficient term, ">Is a quadratic term with respect to temperature.
Specifically, when the positive temperature coefficient term and the negative temperature coefficient term are equal, the value of the reference voltage VREF derived from temperature is 0, and the reference voltage is independent of temperature change, and the circuit output obtains a voltage value which is stable and does not change with temperature in a wider temperature range. Meanwhile, under the combined action of the resistor R4 and the bias current Ibias, a quadratic term related to the variable temperature T is introduced into the output voltage to further compensate the negative temperature coefficient term, and in the first-order temperature compensated band gap reference voltage source, the quadratic term related to the temperature cannot be provided.
Thus, by reasonably setting the proportionality coefficient M, N 1 、N 2 、N 3 The band-gap reference voltage source provided by the application can realize temperature complete compensation by the values of the resistors R4, R6, R7 and R8.
Further, when the bias current establishment is completed, the core reference circuit starts to operate, outputting a reference voltage. At this time, C1 is charged to the power supply voltage VDD, M5 is turned off, and the start-up circuit stops operating.
As shown in fig. 5, a timing chart is established for the output voltage when the power supply VDD is powered on, in the figure, VDD represents the power supply voltage, VC1 represents the voltages at two ends of C1, vq1—c represents the collector voltage of the triode Q1, VREF represents the output reference voltage, and it can be seen from fig. 5 that the bandgap reference voltage source provided by the present application realizes the reference voltage output of low temperature drift.
Fig. 6 is a graph showing the output voltage of the bandgap reference voltage source according to the present application with temperature. The bandgap reference output voltage VREF is stable around 1.26V over a temperature range of-20 deg.C to 130 deg.C. By introducing a resistor R4 and a positive temperature coefficient bias current Ibias, a quadratic term with respect to the variable temperature T is introduced in the output voltage, further compensating the negative term. Compared with a first-order temperature compensated band-gap reference voltage source, the curve of the output voltage of the band-gap reference voltage source along with the temperature change is similar to a sine function curve, and has lower temperature drift coefficient, and the temperature drift coefficient is as follows:
in the method, in the process of the application,
max VREF (T), min VREF (T) represent the maximum and minimum values respectively on the curve of the output voltage with temperature change,
tmax and Tmin are the maximum and minimum temperature values respectively,
average [ VREF (T) ] is the average value of the output voltage over temperature.
As shown in the simulation results of FIG. 6, the temperature drift coefficient was 1.572 ppm/. Degree.C.over the temperature range of-20℃to 130 ℃.
Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present application and not for limiting the same, and although the present application has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that: modifications and equivalents may be made to the specific embodiments of the application without departing from the spirit and scope of the application, which is intended to be covered by the claims.
Claims (15)
1. A bandgap reference voltage source employing second order temperature compensation, comprising: the starting circuit, bias circuit, core reference circuit, mirror image circuit, its characterized in that:
the bias circuit comprises a positive pressure bias current generating circuit, the core reference circuit comprises a feedback control operational amplifier circuit, and the feedback control operational amplifier circuit comprises a positive pressure generating circuit and a negative pressure generating circuit;
the positive voltage generating circuit comprises two triodes and a resistor, and the negative voltage generating circuit comprises a triode; the difference value between the base-emitter voltages of two triodes in the positive voltage generating circuit is a first voltage difference, and the first voltage difference carries out first-order compensation on the negative temperature coefficient voltage generated by the triodes in the negative voltage generating circuit; the positive-pressure bias current generating circuit comprises two triodes and a resistor, wherein the difference value between the base-emitter voltages of the two triodes in the positive-pressure bias current generating circuit generates bias current with positive temperature coefficient on the resistor; the bias current generates a second voltage difference when flowing through a resistor in the positive voltage generating circuit, and the second voltage difference performs second-order temperature compensation on the negative temperature coefficient voltage after the first-order compensation, wherein the first voltage difference and the second voltage difference are both positive temperature coefficient voltages.
2. The bandgap reference voltage source with second order temperature compensation of claim 1, wherein:
the triode at the output end of the reference voltage source adopts a common collector wiring.
3. The bandgap reference voltage source with second order temperature compensation of claim 1, wherein:
the starting circuit comprises: first to fifth MOS transistors M1, M2, M3, M4, M5, a first capacitor C1; the source electrode of M1 is connected with the power supply VDD, the drain electrode of M1 is connected with the source electrode of M2, the drain electrode of M2 is connected with the source electrode of M3, the grid electrodes of M1, M2 and M3 are all grounded, one end of C1 is connected with the drain electrode of M3, the other end of C1 is grounded, the source electrode of M4 is connected with the power supply VDD, the grid electrode of M4 is grounded, the drain electrode of M4 is connected with the source electrode of M5, the grid electrode of M5 is connected with the drain electrode of M3, and the drain electrode of M5 is connected with the bias circuit.
4. A bandgap reference voltage source as claimed in claim 3, wherein the second order temperature compensation is employed, and wherein:
the starting circuit only works in the starting process of the band-gap reference voltage source, and is completely turned off after the band-gap reference voltage source is started.
5. A bandgap reference voltage source as claimed in claim 3, wherein the second order temperature compensation is employed, and wherein:
the bias circuit includes: sixteenth to sixteenth MOS transistors M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, first to fourth transistors Q1, Q2, Q3, Q4, first to third resistors R1, R2, R3; the source electrode of M6 is connected with the source electrode of the power supply VDD, the drain electrode of M6 is connected with the source electrode of M7, the gate electrode of M6 is connected with the gate electrode of M9, the gate electrode of M7 is connected with the gate electrode of M10, the drain electrode of M7 is connected with the source electrode of M8, the drain electrode of M8 is connected with the drain electrode of M5 in the starting circuit, the drain electrode of M8 is connected with the collector electrode of Q1, the base electrode of Q1 is connected with the collector electrode of Q1, the emitter electrode of Q1 is connected with the collector electrode of Q2, the emitter electrode of Q2 is grounded, the base electrode of Q2 is connected with the collector electrode of Q4, the source electrode of M9 is connected with the power supply VDD, the drain electrode of M9 is connected with the source electrode of M10, the gate electrode of M9 is connected with the drain electrode of M10, the drain electrode of M10 is connected with one end of R1, the other end of R1 is connected with the collector electrode of Q3, the base electrode of Q3 is connected with the base electrode of Q1, the base of Q4 is connected with the collector of Q2, the emitter of Q4 is connected with one end of R2, the other end of R2 is grounded, the source of M11 is connected with the power supply VDD, the gate of M11 is connected with the gate of M9, the drain of M11 is connected with the drain of M12, the gate of M12 is connected with the drain of M12, the source of M12 is connected with the drain of M13, the gate of M13 is connected with the gate of M12, the source of M13 is grounded, the source of M14 is connected with the power supply VDD, the gate of M14 is connected with the core reference circuit after being short-circuited, one end of R3 is connected with the drain of M14, the other end of R3 is connected with the drain of M15, the gate of M15 is connected with the gate of M13, the source of M15 is connected with the drain of M16, the gate of M16 is connected with the gate of M13 and is connected with the core reference circuit, and the source of M16 is grounded.
6. The bandgap reference voltage source with second order temperature compensation of claim 5, wherein:
m11, M12, M13, M14, M15, M16 and R3 form a mirror circuit.
7. The bandgap reference voltage source with second order temperature compensation of claim 5, wherein:
a bias circuit for generating a positive temperature coefficient bias current Ibias across the resistor R2 using the difference between the base-emitter voltage differences of the transistors Q2, Q4 in the bias circuit.
8. The bandgap reference voltage source with second order temperature compensation of claim 5, wherein:
the core reference circuit includes: seventeenth to twenty-third MOS transistors M17, M18, M19, M20, M21, M22, M23, fifth to thirteenth transistors Q5, Q6, Q7, Q8, Q9, Q10, fourth to eighth resistors R4, R5, R6, R7, R8, and a second capacitor C2; the source electrode of M17 is connected with the power supply VDD, the grid electrode of M17 is short-circuited with the drain electrode, the drain electrode of M17 is connected with the collector electrode of Q5, the base electrode of Q5 is connected with one end of R7, the emitter electrode of Q5 is connected with the drain electrode of M18, the grid electrode of M18 is connected with the grid electrode of M16 in the starting circuit, the source electrode of M18 is grounded, the source electrode of M19 is connected with the power supply VDD, the grid electrode of M19 is connected with the grid electrode of M17, the drain electrode of M19 is connected with the collector electrode of Q6, the base electrode of Q6 is connected with one end of R8, the emitter electrode of Q6 is connected with one end of R4, the other end of R4 is connected with the drain electrode of M18, the source electrode of M20 is connected with the grid electrode of M114, the drain electrode of M20 is connected with one end of R5, the other end of R5 is connected with the collector electrode of Q7 and the base electrode of Q7, the base electrode of Q7 is in short circuit with the collector electrode of Q7, the base and collector of Q8 are short-circuited, the emitter of Q8 is connected with the drain of M21, the gate of M21 is connected with the collector of Q6, the source of M21 is grounded, one end of C2 is connected with the gate of M21, the other end of C2 is connected with the drain of M21, the source of M22 is connected with the power supply VDD, the gate of M22 is connected with the gate of M20, the drain is connected with the collector of Q9, the base of Q9 is connected with the drain of M20, the emitter of Q9 is connected with the drain of M23, the gate of M23 is connected with the gate of M16 in the starting circuit, the source of M23 is grounded, R6, R7 and R8 are connected in series, one end of R6 is connected with the emitter of Q9 and is also the output end of a reference voltage source, one end of R8 is connected with the base and collector of Q10, the base and collector of Q10 are short-circuited, and the emitter of Q10 is grounded.
9. The bandgap reference voltage source with second order temperature compensation as claimed in claim 8, wherein:
in the core reference circuit, the bias current Ibias and the compensation resistor R4 carry out second-order compensation on the band-gap reference voltage source.
10. The bandgap reference voltage source with second order temperature compensation as claimed in claim 8, wherein:
in the core reference circuit, M17, M19, M18, R4, Q5, and Q6 constitute a first stage feedback control amplifier, Q5, and Q6 constitute a differential input pair, M20, M21, R5, C2, Q7, and Q8 constitute a second stage feedback control amplifier, and M22, M23, R6, R7, R8, Q9, and Q10 constitute a third stage feedback control amplifier.
11. The bandgap reference voltage source with second order temperature compensation as claimed in claim 8, wherein:
q9 employs a common collector approach.
12. The bandgap reference voltage source with second order temperature compensation as claimed in claim 8, wherein:
m13 and M18 form a current mirror structure, and M17 and M19 also form a current mirror structure.
13. A method for operating a bandgap reference voltage source using second order temperature compensation, suitable for use in a bandgap reference voltage source as claimed in any one of claims 1 to 12, comprising:
the working method comprises the following steps:
step 1, after a starting circuit is conducted, a power supply charges a bias circuit and a core reference circuit;
step 2, in the positive voltage generating circuit, the difference between the base-emitter voltages of the two triodes Q5 and Q6 is a first voltage difference, and the output voltage of the reference voltage source is formed by the divided voltage of the first voltage difference on R6, R7 and R8 and the collector voltage of Q10; wherein the first voltage difference is a positive temperature coefficient voltage and the collector voltage of Q10 is a negative temperature coefficient voltage;
step 3, in the bias circuit, the difference between the base-emitter voltages of the two triodes Q2, Q4 generates a bias current with positive temperature coefficient on the resistor R2; generating a second voltage difference when the bias current flows through a resistor R4 in the positive voltage generating circuit, wherein the second voltage difference is positive temperature coefficient voltage; and the second voltage difference carries out second-order temperature compensation on the negative temperature coefficient voltage after the first-order compensation to obtain the reference voltage output by the band-gap reference voltage source.
14. The method of claim 13, wherein the second order temperature compensated bandgap reference voltage source is configured to:
when the bias current is established, the core reference circuit starts to work and outputs a reference voltage. At this time, C1 is charged to the power supply voltage VDD, M5 is turned off, and the start-up circuit stops operating.
15. The method of claim 13, wherein the second order temperature compensated bandgap reference voltage source is configured to:
based on the current mirror structure in the bias circuit and the core reference circuit, the current flowing through the emitter of Q6 under the action of the first voltage difference is the bias currentMultiple, where M is the ratio of the aspect ratio of M17 to M19 in the current mirror structure, N 3 Is the ratio of the aspect ratio of M18 to M13 in the current mirror structure.
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