CN101840240A - Adjustable multi-value output reference voltage source - Google Patents
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Abstract
The invention discloses an adjustable multi-value output reference voltage source. The voltage source comprises a reference generating circuit and a reference voltage output circuit, wherein a starting circuit and a mirror current source negative feedback loop are connected between the reference generating circuit and the reference voltage output circuit; one end of the starting circuit is connected with the reference generating circuit, while the other end is connected with the mirror current source negative feedback loop; and the other end of the mirror current source negative feedback loop is connected with the reference voltage output circuit. The adjustable multi-value output reference voltage source has the advantages of low circuit power consumption, low temperature drift and high power supply inhibiting capacity. In the adjustable multi-value output reference voltage source of the invention, the mirror current source negative feedback loop is used by replacing a high voltage gain amplifier, so that a circuit structure is simpler; a source follower connected with the output end of the mirror current source negative feedback loop provides a bipolar transistor basis voltage and generates a band gap reference voltage at the same time; and simultaneously an output voltage value with a small temperature coefficient can be obtained.
Description
Technical Field
The invention relates to a reference voltage source used by an integrated circuit, in particular to a bandgap (bandgap) reference voltage source.
Background
A reference voltage source generally refers to a highly stable voltage source that is used as a reference in a circuit. With the high-speed development of integrated circuits, the system structure is further complicated, higher requirements are put on basic modules of analog circuits, such as an A/D, D/A converter, a voltage detection comparison circuit and the like, and high precision, high stability and low power consumption are the mainstream of design. For these modules, the voltage reference is a very important module, and the stability of the reference voltage source is directly related to the working state of the circuit and the working performance of the circuit. A good voltage reference requires a small temperature coefficient and a strong power supply rejection capability.
The working principle of the band-gap reference is that V is utilized according to the characteristic that the band-gap voltage of the silicon material is independent of the power supply voltage and the temperatureBEPositive temperature coefficient and bipolar transistor VBEThe negative temperature coefficients are mutually offset, and the low-temperature drift and high-precision reference voltage is realized. Bipolar transistor providing an emitter bias voltage VBEFrom V between two transistorsBEGenerating VTV is connected through a resistor networkTAmplifying several times, adding two voltages
The appropriate multiple is chosen such that the temperature drift coefficients of the two voltages cancel each other out, resulting in a zero temperature coefficient voltage reference at a certain temperature, typically 1.25V.
In the BUCK type LED driving circuit, the voltage fed back by the current detection resistor is an extremely low voltage value, and we determine the on-off state of power mos of the driving circuit by comparing the voltage value fed back by the current detection resistor. The stability of the reference voltage for comparison is important. The general bandgap reference voltage source cannot directly meet the requirement, and other voltage conversion circuits need to be designed to reduce the value of the output reference voltage, which also greatly increases the design difficulty.
Chinese patent application No. 200710303891.8, whose publication No. is CN101470458A, discloses a bandgap reference voltage reference circuit, which includes: the VBE voltage generator comprises a self-bias current source used for generating the two-branch reference circuit and a bias generator coupled to the self-bias current source and used for generating two-branch VBE voltages; the reference voltage regulator comprises an operational transconductance amplifier and a reference voltage regulating unit, and is used for generating a constant reference voltage. The scheme needs to use an operational transconductance amplifier, so that the circuit is complex and the cost is high.
The Chinese invention patent with the granted publication number of CN100459197C and the patent number of ZL200510120849.3 discloses a low-temperature coefficient band gap reference voltage source, which comprises the following circuits: a PTAT current generating circuit for generating a PTAT current IPTAT; the reference voltage starting circuit is connected with the PTAT current generating circuit and used for overcoming a zero current working point of the PTAT current generating circuit and ensuring that the PTAT current IPTAT can be generated; the reference voltage synthesis circuit is connected with the output end of the PTAT current generation circuit and is used for generating reference voltage; the base current counteracting circuit is connected with the reference voltage synthesizing circuit and is used for counteracting extra base current generated by a transistor in the reference voltage synthesizing circuit so as to ensure the correct generation of reference voltage; the low-temperature coefficient band-gap reference voltage source also comprises a second-order temperature compensation current generating circuit, wherein the second-order temperature compensation current generating circuit is connected with the first current mirror circuit and the reference voltage synthesizing circuit, IPTAT current and band-gap reference voltage are input, second-order compensation current is generated by utilizing the square relation between drain-source current of an MOS (metal oxide semiconductor) tube and grid-source voltage difference and is output to the reference voltage synthesizing circuit to generate second-order compensation voltage, the second-order temperature coefficient of the reference voltage is compensated, and reference voltage of an extremely low-temperature coefficient is generated. On one hand, the scheme can not realize a multi-value output mode; on the other hand, the mode of generating the band-gap reference voltage is complex, the power consumption, the temperature drift and the power supply inhibition capability are not ideal, the current mirror composed of MN1, MN2, MP1 and MP2 is used for enabling the currents flowing through MN1 and MN2 to be the same, so that the source voltages of MN1 and MN2 are the same, and further two ends of R1 are obtained
The positive temperature coefficient voltage is obtained, so that PTAT current flowing through R1 is obtained, and the positive temperature coefficient voltage V is obtained on a resistor R2 through circuit mirror imageR2And the negative temperature coefficient voltage is V of the bipolar transistors P3, P4beThe added structure can be seen from the figure, the band gap reference voltage is
Wherein,
m is the base area ratio of the bipolar transistors P2 and P1.
Disclosure of Invention
The invention aims to provide a reference voltage source with adjustable multi-value output, which has the advantages of low circuit power consumption, low temperature drift and strong power supply inhibition capability.
In order to achieve the purpose, the invention designs an adjustable multi-value output reference voltage source, which comprises a reference generating circuit and a reference voltage output circuit, wherein a starting circuit and a mirror current source negative feedback loop are connected between the reference generating circuit and the reference voltage output circuit, one end of the starting circuit is connected with the reference generating circuit, the other end of the starting circuit is connected with the mirror current source negative feedback loop, and the other end of the mirror current source negative feedback loop is connected with the reference voltage output circuit.
The mirror current source negative feedback loop comprises PMOS tubes MP5, MP6, NMOS tubes MN1 and MN2, the grid electrode of the PMOS tube MP5 is connected with a reference generation circuit, the source electrode of the MP5 is connected with VDD, the drain electrode of the MP5 is connected with the drain electrode of the NMOS tube MN2, the source electrode of the NMOS tube MN2 is grounded, the grid electrode of the NMOS tube MN2 is connected with the grid electrode of the NMOS tube MN1, the drain electrode of the NMOS tube MN1 is connected with the drain electrode of the PMOS tube MP6, the grid electrode of the PMOS tube MP6 is connected with the reference generation circuit, the source electrode of the PMOS tube MP6 is connected with VDD, and the drain electrode of the PMOS tube MP6 is connected with.
The starting circuit comprises PMOS tubes MP3 and MP4 and bipolar transistors Q3 and Q4, wherein the source end of the PMOS tube MP3 is connected with VDD, the drain end of the PMOS tube MP3 is connected with the source end of the PMOS tube MP4, the grids of the PMOS tubes MP3 and MP4 are connected and then grounded, the drain end of the PMOS tube MP4 is connected with the collector of the bipolar transistor Q4, the emitter of the bipolar transistor Q4 is grounded, the collector and the base of the bipolar transistor Q4 are in short circuit connection and are simultaneously connected with the base of the bipolar transistor Q3, and the emitter and the collector of the bipolar transistor Q3 are respectively connected with the reference generating.
The reference voltage output circuit is a multi-value reference voltage output circuit and comprises a source follower Q5, a voltage division resistor R4, R5 and R6, wherein the base electrode of the source follower Q5 is connected with the drain electrode of a PMOS tube MP6 in a negative feedback loop of a mirror current source, the collector electrode of Q5 is connected with VDD, the emitter electrode is connected with a resistor R6 and leads out the output end of reference voltage V2, the other end of a resistor R6 is connected with the resistor R5 and a reference generating circuit, a band gap reference voltage VREF output end is led out between the resistor R6 and the R5, the other end of the resistor R5 is connected with the resistor R4, a reference voltage V1 output end is led out between the resistors R5 and R4, and the other end of the resistor R4 is grounded.
The reference generating circuit comprises PMOS tubes MP1, MP2, bipolar transistors Q1, Q2, resistors R1, R2 and R3, wherein the sources of the PMOS tubes MP1 and MP2 are connected with VDD, the gates of the PMOS tubes MP1 and MP2 are in short circuit, the drain of the PMOS tube MP1 is connected with the collector of the bipolar transistor Q1 and the gate of a PMOS tube MP5 in a mirror current source negative feedback loop, the drain of the PMOS tube MP2 is connected with the collector of the bipolar transistor Q2 and the gate of a PMOS tube MP6 in the mirror current source negative feedback loop, one end of the resistor R3 is connected with the base of the bipolar transistor Q2, the other end of the resistor R8658 is connected with the base of the bipolar transistor Q1 and the resistor R6 in the reference voltage output circuit, the resistor R2 is connected with the emitter of the bipolar transistor Q2 and the emitter of the Q2, and the resistor R2 is connected between the common point and.
The adjustable multi-value output reference voltage source uses the mirror current source negative feedback loop to replace a high-voltage gain operational amplifier, so that the circuit structure is simpler, the source follower connected with the output end of the mirror current source negative feedback loop provides the bias voltage of the bipolar transistor and simultaneously generates the band-gap reference voltage, and the connection of the circuit is optimized, so that the output voltage value with a smaller temperature coefficient can be obtained when the adjustable multi-value output reference voltage source works. Meanwhile, according to the needs of the system, multiple paths of reference voltage outputs can be obtained simultaneously. The adjustable multi-value output reference voltage source has the characteristics of low circuit power consumption, low temperature drift and strong power supply inhibition capability.
Description of the drawings:
FIG. 1 is a schematic block diagram of a reference voltage source with adjustable multi-valued output according to the present invention;
FIG. 2 is a circuit diagram of a reference voltage source with adjustable multi-valued output according to the present invention.
Detailed Description
For the understanding of those skilled in the art, the structural principles of the present invention will be described in further detail below with reference to specific embodiments and the attached drawings:
as shown in fig. 1, an adjustable multi-value output reference voltage source, and an adjustable multi-value output reference voltage source include a reference generating circuit and a reference voltage output circuit, a starting circuit and a mirror current source negative feedback loop are connected between the reference generating circuit and the reference voltage output circuit, one end of the starting circuit is connected with the reference generating circuit, the other end of the starting circuit is connected with the mirror current source negative feedback loop, and the other end of the mirror current source negative feedback loop is connected with the reference voltage output circuit.
As shown in fig. 2, the mirror current source negative feedback loop includes PMOS transistors MP5, MP6, NMOS transistors MN1, MN2, the gate of the PMOS transistor MP5 is connected to the reference generating circuit, the source of the MP5 is connected to VDD, the drain of the MP5 is connected to the drain of the NMOS transistor MN2, the source of the NMOS transistor MN2 is grounded, the gate of the NMOS transistor MN2 is connected to the gate of the NMOS transistor MN1, the drain of the NMOS transistor MN1 is connected to the drain of the PMOS transistor MP6, the gate of the PMOS transistor MP6 is connected to the reference generating circuit, the source of the PMOS transistor MP6 is connected to VDD, and the drain of the PMOS transistor MP6 is connected to the reference voltage output circuit.
The starting circuit comprises PMOS tubes MP3 and MP4 and bipolar transistors Q3 and Q4, wherein the source end of the PMOS tube MP3 is connected with VDD, the drain end of the PMOS tube MP3 is connected with the source end of the PMOS tube MP4, the grids of the PMOS tubes MP3 and MP4 are connected and then grounded, the drain end of the PMOS tube MP4 is connected with the collector of the bipolar transistor Q4, the emitter of the bipolar transistor Q4 is grounded, the collector and the base of the bipolar transistor Q4 are in short circuit connection and are simultaneously connected with the base of the bipolar transistor Q3, and the emitter and the collector of the bipolar transistor Q3 are respectively connected with the reference generating.
The reference voltage output circuit is a multi-value reference voltage output circuit and comprises a source follower Q5, a voltage division resistor R4, R5 and R6, wherein the base electrode of the source follower Q5 is connected with the drain electrode of a PMOS tube MP6 in a negative feedback loop of a mirror current source, the collector electrode of Q5 is connected with VDD, the emitter electrode is connected with a resistor R6 and leads out the output end of reference voltage V2, the other end of a resistor R6 is connected with the resistor R5 and a reference generating circuit, a band gap reference voltage VREF output end is led out between the resistor R6 and the R5, the other end of the resistor R5 is connected with the resistor R4, a reference voltage V1 output end is led out between the resistors R5 and R4, and the other end of the resistor R4 is grounded.
The reference generating circuit comprises PMOS tubes MP1, MP2, bipolar transistors Q1, Q2, resistors R1, R2 and R3, wherein the sources of the PMOS tubes MP1 and MP2 are connected with VDD, the gates of the PMOS tubes MP1 and MP2 are in short circuit, the drain of the PMOS tube MP1 is connected with the collector of the bipolar transistor Q1 and the gate of a PMOS tube MP5 in a mirror current source negative feedback loop, the drain of the PMOS tube MP2 is connected with the collector of the bipolar transistor Q2 and the gate of a PMOS tube MP6 in the mirror current source negative feedback loop, one end of the resistor R3 is connected with the base of the bipolar transistor Q2, the other end of the resistor R8658 is connected with the base of the bipolar transistor Q1 and the resistor R6 in the reference voltage output circuit, the resistor R2 is connected with the emitter of the bipolar transistor Q2 and the emitter of the Q2, and the resistor R2 is connected between the common point and.
The output end of a negative feedback loop of the mirror current source is connected with the reference voltage output circuit, the reference voltage output circuit is a multi-value reference voltage output circuit, and a source follower contained in the reference voltage output circuit provides base bias for the bipolar transistor on one hand and outputs a plurality of reference voltages through a divider resistor on the other hand.
The invention uses the negative feedback loop of the mirror current source to replace the high-voltage gain operational amplifier, so that the circuit structure is simpler. As shown in particular in figure 2. In fig. 2, all NMOS transistors have the same aspect ratio, and all PMOS transistors have the same aspect ratio. The current in the branches MP1 and Q1 is mirrored to the branches MN1 and MP6 by mirroring of MP1, MP5, MN2 and MN1, and meanwhile, the saturation current flowing in the branch MP2 is equal to the saturation current flowing in the branch MP1 by mirroring of the branches MP1 and MP2, when the bandgap reference voltage is output, the branches MP1, MP2, MP6 and MN1 all work in the saturation region, the currents flowing in the branches MP1, MP2 and MP6 are equal, VGSMP1 ═ VGSMP6, namely VDSMP1 ═ VDSMP2, the mirror current loss caused by MOSFET secondary effect is eliminated, and the mirror current matching caused by MOSFET secondary effect is ensured
The source electrode of the PMOS tube MP2 is connected with VDD, the grid electrode is in short circuit with the PMOS tube MP1, the drain electrode is connected with the grid electrode of the PMOS tube MP5, the source electrode of the PMOS tube MP5 is connected with VDD, the drain electrode is connected with the drain electrode of the NMOS tube MN2, the source electrode of the NMOS tube MN2 is grounded, the grid electrode is connected with the grid electrode of the NMOS tube MN1, and the drain electrode of the NMOS tube MN1 is connected with the drain electrode of the PMOS tube MP 6. The source end of the PMOS tube MP1 is connected with VDD, the grid drain of the PMOS tube MP1 is connected with the grid of the PMOS tube MP6 in a short circuit mode, and the source electrode of the PMOS tube MP6 is connected with VDD. The source follower bipolar transistor Q5 is used as a source follower, the collector of the source follower bipolar transistor Q5 is connected with VDD, the base of the source follower bipolar transistor Q5 is connected with the drain terminal of the PMOS transistor MP6, and the emitter of the source follower bipolar transistor Q5 is connected with the current input terminal of the resistor R6 and outputs the reference voltage V2. The current output end of the resistor R6 is connected with the current input end of the resistor R5 and provides base bias for the bipolar transistors Q1 and Q2 to generate a band-gap reference voltage VREF. The current output end of the resistor R5 is connected with the current input end of the resistor R4 and generates a reference voltage V1. The current output terminal of the resistor R4 is connected to ground.
In the circuit of the invention, PMOS tubes MP3 and MP4 and bipolar transistors Q3 and Q4 form a starting circuit. The source end of the PMOS tube MP3 is connected to VDD, the drain end is connected to the source end of the PMOS tube MP4, and the PMOS tubes MP3 and MP4 are connected to ground. The drain terminal of the PMOS transistor MP4 is connected to the collector of the bipolar transistor Q4. The emitter of bipolar transistor Q4 is grounded and its collector and base are shorted while the base of bipolar transistor Q3 is connected. The emitter of the bipolar transistor Q3 is connected to the current input terminal of the resistor R1, and the collector of the bipolar transistor Q3 is connected to the drain of the MP 2. When the circuit is powered on, the base-emitter voltage difference of the bipolar transistors Q3 and Q4 generates a current starting circuit on the resistor R1.
In the present invention, the positive temperature coefficient is determined by the bipolar transistors Q1, Q2
And (4) generating. The collector of the bipolar transistor Q1 is connected with the drain of the PMOS tube MP1, the base is connected with the current output end of the resistor R6, and the emitter is connected with the current input end of the resistor R1. The collector of the bipolar transistor Q2 is connected with the drain of the PMOS tube MP2, the base is connected with the current output end of the resistor R3, the current input end of the resistor R3 is connected with the current output end of the resistor R6, the emitter is connected with the current input end of the resistor R2, the current output end of the resistor R2 is connected with the current input end of the resistor R1, and the current output end of the resistor R1 is grounded.
As shown by the formula, the resistor R3 can correct the positive temperature coefficient voltage, and the resistor R3 can be converted into R2. The temperature coefficient of the reference voltage is derived in detail below. We can derive from fig. 2:
wherein, VBE1The relationship with temperature is as follows:
the coupling formulae (1), (2) and (3) can be obtained
According to the expression of the formula (4), it can be obtained that the emitter area ratio of the bipolar transistors Q1, Q2 and the ratio of the resistors R1, R2 can be set appropriately, and at a specific temperature T0A zero temperature coefficient is obtained. The base current of bipolar transistor Q2 flows into resistor R2 and contributes to the positive temperature coefficient voltage. Since the collector currents flowing through the bipolar transistors Q1 and Q2 are small, β increases with increasing temperature, and it can be known from equation (2) that the second order term of the reference voltage can be compensated for at higher temperatures.
As shown in fig. 1 and fig. 2, the output end of the source follower connected to the output end of the negative feedback loop of the mirror current source is subjected to voltage division, on one hand, base bias is provided for the bipolar transistor, and on the other hand, a plurality of reference voltages are output through the voltage division resistor. Wherein
From the formula, we can see that by setting the ratio between the resistances, we can obtain a wide range of reference voltage values. On the branch where R1, R2 and R3 are located, we can subdivide the three resistance values, i.e. by multiple resistorsThe resistors achieve the same series resistance value, and then another reference voltage can be obtained between the resistors. Such as: we get
A reference voltage can be output between R11 and R12.
Since a part of the current flowing through the resistor R3 is the base current of the bipolar transistors Q1 and Q2, the current is equal to the reference voltage V2There is a trade-off between accuracy of.
In summary, the present invention can output a plurality of reference voltages. When a reference voltage of 200mV is output within-40 ℃ to +125 ℃, the temperature drift is lower than 0.5mV
The adjustable multi-value output reference voltage source of the invention enables collector currents flowing through bipolar transistors Q1 and Q2 to be equal through a negative feedback loop (consisting of MP1, MP2, MP5, MP6, MN1, MN2, Q5, R6, R3, Q1 and Q2 which are the structural basis of multi-value output) with a current mirror, and further generates positive temperature coefficient voltage on a resistor R2
The negative temperature coefficient voltage is V of the bipolar transistor Q1beAs can be seen from the figure, the band gap reference voltage is
Wherein,
m is the base area ratio of the bipolar transistors Q2, Q1. The Q1, Q2, MP1, MP2, R2 branches produce PTAT current, while a bandgap reference voltage is generated at the base of Q1.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the embodiments of the present invention, and those skilled in the art should make appropriate changes or modifications based on the concept of the present invention, which fall within the scope of the present invention.
Claims (3)
1. An adjustable multi-value output reference voltage source comprises a reference generating circuit and a reference voltage output circuit, and is characterized in that: a starting circuit and a mirror current source negative feedback loop are connected between the reference generating circuit and the reference voltage output circuit, one end of the starting circuit is connected with the reference generating circuit, the other end of the starting circuit is connected with the mirror current source negative feedback loop, and the other end of the mirror current source negative feedback loop is connected with the reference voltage output circuit.
2. The reference voltage source of claim 1, wherein: the mirror current source negative feedback loop comprises PMOS tubes MP5, MP6, NMOS tubes MN1 and MN2, the grid electrode of the PMOS tube MP5 is connected with a reference generation circuit, the source electrode of the MP5 is connected with VDD, the drain electrode of the MP5 is connected with the drain electrode of the NMOS tube MN2, the source electrode of the NMOS tube MN2 is grounded, the grid electrode of the NMOS tube MN2 is connected with the grid electrode of the NMOS tube MN1, the drain electrode of the NMOS tube MN1 is connected with the drain electrode of the PMOS tube MP6, the grid electrode of the PMOS tube MP6 is connected with the reference generation circuit, the source electrode of the PMOS tube MP6 is connected with VDD, and the drain electrode of the PMOS tube MP6 is connected with.
3. The reference voltage source according to claim 1 or 2, characterized in that: the reference voltage output circuit is a multi-value reference voltage output circuit and comprises a source follower Q5, a voltage division resistor R4, R5 and R6, wherein the base electrode of the source follower Q5 is connected with the drain electrode of a PMOS tube MP6 in a negative feedback loop of a mirror current source, the collector electrode of Q5 is connected with VDD, the emitter electrode is connected with a resistor R6 and leads out the output end of reference voltage V2, the other end of a resistor R6 is connected with the resistor R5 and a reference generating circuit, a band gap reference voltage VREF output end is led out between the resistor R6 and the R5, the other end of the resistor R5 is connected with the resistor R4, a reference voltage V1 output end is led out between the resistors R5 and R4, and the other end of the resistor R4 is grounded.
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| CN101226414A (en) * | 2008-01-30 | 2008-07-23 | 北京中星微电子有限公司 | Method for dynamic compensation of reference voltage and band-gap reference voltage source |
| CN101644938A (en) * | 2008-08-06 | 2010-02-10 | 上海华虹Nec电子有限公司 | Safety starter circuit of low-voltage bandgap reference source |
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