CN108279733B - Current limit reference generation circuit and setting circuit - Google Patents
Current limit reference generation circuit and setting circuit Download PDFInfo
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- CN108279733B CN108279733B CN201810140115.9A CN201810140115A CN108279733B CN 108279733 B CN108279733 B CN 108279733B CN 201810140115 A CN201810140115 A CN 201810140115A CN 108279733 B CN108279733 B CN 108279733B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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Abstract
The invention provides a current limit reference generating circuit and a setting circuit, which comprise an on-chip circuit and an off-chip circuit; the off-chip circuit comprises a current limit setting circuit; the on-chip circuit comprises an enabling circuit, a first current limit reference generating circuit and a second current limit reference generating circuit; the enabling circuit is an enabling circuit of a gating current limit reference scheme; through the clamping effect and the comparison effect of the first current limit reference generating circuit, current is mirrored to the first current limit reference output end and the enabling circuit, when the current mirror in the enabling circuit has current, the second current limit reference generating circuit is closed, when the application condition needs the selectable current limit setting scheme, different current limit setting schemes can be controlled and selected through the programmable GPIO signal ports, meanwhile, fewer GPIO ports are used, an off-chip switch structure is not used, and cost is controlled. Compared with the traditional current limit setting scheme, the invention provides a low-cost solution while the current limit setting is programmable.
Description
Technical Field
The invention relates to a current limit reference generating circuit and a setting circuit, and relates to the field of integrated circuits.
Background
In the current integrated circuit technology, a circuit protection mechanism is an important function of all power related circuits, wherein a current limiting technology relates to important factors such as whether the whole circuit can safely operate or not, has great influence, and is a problem of current extensive research. In the current limiting technology, the requirements on current limitation are often different under different application conditions, so that a current limit setting scheme which can be customized or programmable is often required.
The current limit reference current is typically generated by dividing a fixed reference voltage by a resistor. By changing or adjusting the resistance, different current limit reference currents can be obtained. However, in practical engineering application, the set resistor in the circuit is usually difficult to directly replace, so that the preset multipath resistor can be gated by the general purpose input/output GPIO signal obtained through programming. In this way, different current limit references can be obtained according to different needs, but in practical application, the cost of the GPIO signal ports is higher, especially when a plurality of GPIO ports are used, and meanwhile, a certain cost is required for the switch structure for gating controlled by the GPIO signals outside the chip. Therefore, conventional current limit setting methods either can only provide a single current limit or are costly.
Disclosure of Invention
The invention provides a high-efficiency current limit reference generating circuit which has the characteristics that different current limits can be generated only by gating control signals according to one current limit, and the preset multipath resistors are conveniently gated by general purpose input/output GPIO signals obtained through programming.
The invention also provides a current limit setting circuit which is matched with the current limit reference generating circuit, has the characteristics of programmability and low cost, and can generate different current limits only by one path of current limit gating control signals.
The current limit reference generating circuit provided by the invention is characterized in that: the circuit comprises an enabling circuit, a first current limit reference generating circuit and a second current limit reference generating circuit; the enabling circuit is an enabling circuit of a gating current limit reference scheme;
the first current limit reference generating circuit comprises a first current mirror circuit, a first clamping circuit, a current limit gating control signal input end and a first current limit signal output end; the first clamping circuit comprises a first operational amplifier OP1 and a first NMOS tube MN1; the non-inverting input end of the first operational amplifier OP1 is connected with a first reference voltage VREF1, and the inverting input end of the first operational amplifier OP1 is connected with the source electrode of the first NMOS tube MN1 and is connected to the current limit gating control signal input end; the first current mirror circuit is configured to mirror the drain current of the first NMOS MN1 to the mirror current output; the mirror current output end comprises a first current limit signal output end;
the enabling circuit comprises an image current circuit, a bias current source circuit and an inverter; the mirror current circuit is matched with the first current mirror circuit to obtain the mirror current of the first mirror circuit; the bias power supply circuit is connected with the current output end of the mirror current circuit and is connected with bias voltage to generate bias current; the input end of the inverter is connected with the current output end of the mirror current circuit;
the second current limit reference generating circuit comprises a circuit enabling end, a second current mirror circuit, a second clamping circuit and a second current limit signal output end; the circuit enabling end is connected with the output end of the phase inverter; the second clamping circuit comprises a second operational amplifier OP2 and a third NMOS tube MN3; the non-inverting input end of the second operational amplifier OP2 is connected with the second reference voltage VREF1, and the inverting input end of the second operational amplifier OP2 is connected with the source electrode of the third NMOS tube MN3 and is grounded through a second resistor R2; the second current mirror circuit is configured to mirror the drain current of the third NMOS MN3 to the mirror current output; the mirror current output terminal includes a second current limit signal output terminal.
The bias current source circuit comprises a second NMOS tube MN2, the drain electrode of the second NMOS tube is connected with the current output end of the mirror current circuit, the grid electrode of the second NMOS tube is connected with bias voltage Vbias, and the source electrode of the second NMOS tube is grounded.
The first current mirror circuit comprises a first PMOS tube MP1 and a third PMOS tube MP3; the source electrode of the first PMOS tube MP1 is connected with the power supply VDD, and the drain electrode and the grid electrode are in short circuit and are respectively connected to the drain electrode of the first NMOS tube MN1 and the grid electrode of the third PMOS tube MP3; the source electrode of the third PMOS tube MP3 is connected with the power supply VDD, and the drain electrode is connected with the first current limit signal output end.
The mirror current circuit comprises a second PMOS tube MP2, a source electrode is connected with a power supply VDD, a grid electrode is connected with a grid electrode of the first PMOS tube MP1, and a drain electrode is connected with a current output end of the mirror current circuit.
The second current mirror circuit comprises a fourth PMOS tube MP4 and a fifth PMOS tube MP5; the source electrode of the fourth PMOS tube MP4 is connected with the power supply VDD, and the drain electrode and the grid electrode are in short circuit and are respectively connected to the drain electrode of the third NMOS tube MN3 and the grid electrode of the fifth PMOS tube MP5; the source electrode of the fifth PMOS tube MP5 is connected with the power supply VDD, and the drain electrode is connected with the second current limit signal output end.
The enabling circuit, the first current limit reference generating circuit and the second current limit reference generating circuit are all arranged in the chip; the chip is an integrated circuit chip.
A current limit setting circuit, which is matched with the current limit reference generating circuit, characterized in that: comprises a first resistor R1; one end of the first resistor R1 is connected with the GPIO signal control end, and the other end of the first resistor R1 is connected with the current limit gating control signal input end.
The current limit setting circuit is arranged outside the chip, and the current limit reference generating circuit is arranged in the chip; the chip is an integrated circuit chip.
Compared with the prior art, the invention has the beneficial effects that: when the application condition needs the alternative current limit setting scheme, different current limit setting schemes can be controlled and selected through the programmable GPIO signal ports, meanwhile, fewer GPIO ports are used, an off-chip switch structure is not used, and the cost is controlled. Compared with the traditional current limit setting scheme, the invention provides a low-cost solution while the current limit setting is programmable.
Drawings
Fig. 1 is a schematic diagram of a current limit reference generating circuit according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a second current limit reference generating circuit according to an embodiment of the invention.
Fig. 3 is an example of a current mirror circuit.
Fig. 4 is an example of a current mirror circuit.
Fig. 5 is a schematic diagram of a current limit reference generating circuit and a current limit setting circuit matched with the current limit reference generating circuit according to an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a conventional structure of a current limit setting scheme.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Any feature disclosed in this specification (including abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. That is, each feature is one example only of a generic series of equivalent or similar features, unless expressly stated otherwise.
According to the invention, a current limit reference generating circuit is provided, as shown in fig. 1, and comprises an enabling circuit 3, a first current limit reference generating circuit 1 and a second current limit reference generating circuit 2; the enabling circuit 3 is an enabling circuit of a gating current limit reference scheme;
the first current limit reference generating circuit 1 comprises a first current mirror circuit, a first clamping circuit, a current limit gating control signal input end and a first current limit signal output end; the first clamping circuit comprises a first operational amplifier OP1 and a first NMOS tube MN1; the non-inverting input end of the first operational amplifier OP1 is connected with a first reference voltage VREF1, and the inverting input end of the first operational amplifier OP1 is connected with the source electrode of the first NMOS tube MN1 and is connected to the current limit gating control signal input end; the first current mirror circuit is configured to mirror the drain current of the first NMOS MN1 to the mirror current output; the mirror current output end comprises a first current limit signal output end;
the enabling circuit comprises an image current circuit, a bias current source circuit and an inverter INV1; the mirror current circuit is matched with the first current mirror circuit to obtain the mirror current of the first mirror circuit; the bias power supply circuit is connected with the current output end of the mirror current circuit and is connected with bias voltage to generate bias current; the input end of the inverter is connected with the current output end of the mirror current circuit;
as shown in fig. 2, the second current limit reference generating circuit includes a circuit enable terminal Ven (the signal intelligently enables or turns off the part of the circuit, not limited to a specific position of the circuit content), a second current mirror circuit, a second clamping circuit and a second current limit signal output terminal; the circuit enabling end is connected with the output end of the phase inverter; the second clamping circuit comprises a second operational amplifier OP2 and a third NMOS tube MN3; the non-inverting input end of the second operational amplifier OP2 is connected with the second reference voltage VREF1, and the inverting input end of the second operational amplifier OP2 is connected with the source electrode of the third NMOS tube MN3 and is grounded through a second resistor R2; the second current mirror circuit is configured to mirror the drain current of the third NMOS MN3 to the mirror current output; the mirror current output terminal includes a second current limit signal output terminal.
The first NMOS MN1 is used as a follower of the first OP1, and when the voltage VREF1 of the non-inverting input terminal of the first OP1 is not lower than the voltage of the inverting input terminal, the voltage of the inverting input terminal is equal to VREF1, i.e. the voltage of the source terminal of MN1 is VREF1. When the external GPIO signal of the matched current limit setting circuit is low level 0, the voltage drop across the first resistor R1 connected in series with the input end of the GPIO signal is VREF1, so that the current I can be generated on the first resistor R1 0 ，I 0 Is VREF1/R1; current I 0 After flowing through the first NMOS tube MN1, the first current limit reference I is obtained by mirroring the current output end of the mirror current circuit through a current mirror limit1 . At this time, the enable circuit 3 also obtains the image current I of the first image circuit 1 The bias power supply in the enabling circuit 3 enables the bias circuit I through the set bias power supply Vbase bias Less than current I 1 . Thus, when the enable circuit mirrors current, because I 1 >I bias The voltage at the point a of the input end of the inverter INV1 is pulled up to the high level, so that the output end enable signal Ven of the INV1 is at the low level, and the second current limit reference generating circuit 2 does not operate. Thus, when programming the external GPIO signal to low level 0, a current limit setting scheme one is obtained: the first current limit reference generating circuit generates a first current limit reference I limit1 The method comprises the steps of carrying out a first treatment on the surface of the The second current limit reference generating circuit does not operate.
When the external GPIO signal of the matched current limit setting circuit is high level 1 and the high level is larger than VREF1 by a certain amplitude, the first operational amplifier OP1 is used as a comparator at the moment, and the comparator outputs low level to enable the first NMOS tube MN1 to be turned off because the input voltage of the inverting input end is higher than the input voltage of the non-inverting input end, and the current I is at the moment 0 For 0, obtaining no current output of the first current limit reference generation circuit, and enabling the current I in the circuit 1 Also 0, the voltage at point A is biased by the current I of the current source bias Pull down to low to enable the output enable signal Ven of the inverter INV1 to be high, enabling the second current limit reference I limit1 Obtaining a second current limit setting scheme: the first current limit reference generating circuit does not operate; the second current limit reference generating circuit generates a second current limit reference I limit2 。
On the basis of the circuit structure of the current limit reference generating circuit, only one GIPO signal input end and one current limiting resistor (first resistor R1) are required to be arranged, any type of switch structure is not required to be contained outside, and the function of generating different current limits according to one current limit gating control signal is realized, and the programmable current limit generating circuit is convenient for gating preset multipath resistors through general purpose input/output GPIO signals obtained through programming. Therefore, the current limit reference generating circuit is convenient for realizing the function of generating different current limits only by gating control signals according to one current limit, and is convenient for gating the preset multipath resistors through the general purpose input/output GPIO signals obtained through programming.
As an embodiment of the present invention, the bias current source circuit includes a second NMOS transistor MN2, a drain connected to a current output terminal of the mirror current circuit, a gate connected to the bias voltage Vbias, and a source grounded. The bias current source MN2 makes the bias current I pass through the set bias voltage Vbase bias Less than current I 1 。
As an embodiment of the present invention, the first current mirror circuit includes a first PMOS transistor MP1 and a third PMOS transistor MP3; the source electrode of the first PMOS tube MP1 is connected with the power supply VDD, and the drain electrode and the grid electrode are in short circuit and are respectively connected to the drain electrode of the first NMOS tube MN1 and the grid electrode of the third PMOS tube MP3; the source electrode of the third PMOS tube MP3 is connected with the power supply VDD, and the drain electrode is connected with the first current limit signal output end. In this embodiment, the mirror ratio is 1 to 1, to obtain a first current limit reference I limit1 =vref 1/R1. When GPIO is low level 0, current I 0 After passing through the first NMOS MN1, the current mirror MP1 mirrors the current mirror MP3, and at this time, a first current limit reference can be obtained at the drain terminal of MP 3.
As one embodiment of the present invention, the mirror current circuit comprises a second PMOS transistor MP2 having a source connected to the power supply VDD, a gate connected to the gate of the first PMOS transistor MP1, and a drain connected toThe current output of the mirror current circuit. In this particular embodiment, the mirror ratio is a 1 to 1 relationship. When GPIO is low level 0, current I 0 After passing through the first NMOS transistor MN1, mirror-image is carried out on MP2 through a current mirror MP1, and I is obtained at the moment 1 = I 0 。
As an embodiment of the present invention, the second current mirror circuit includes a fourth PMOS transistor MP4 and a fifth PMOS transistor MP5; the source electrode of the fourth PMOS tube MP4 is connected with the power supply VDD, and the drain electrode and the grid electrode are in short circuit and are respectively connected to the drain electrode of the third NMOS tube MN3 and the grid electrode of the fifth PMOS tube MP5; the source electrode of the fifth PMOS tube MP5 is connected with the power supply VDD, and the drain electrode is connected with the second current limit signal output end. In this particular embodiment, the mirror ratio is a 1 to 1 relationship. When receiving the high level enable signal, the second current limit reference I limit2 The generation circuit 4 of (2) starts to operate; when the voltage VREF2 at the positive input end of the second operational amplifier OP2 is not lower than the voltage at the negative input end, the second operational amplifier OP2 plays a role in clamping, so that the voltage at the negative end is equal to VREF2, namely the voltage at the source end of MN3 is VREF2. At this time, the voltage drop across the second resistor R2 is VREF2, and the current flowing through R2 is: i limit2 =VREF2/R2。
The mirror circuit is not limited to the mirror circuit configuration and the mirror ratio in the above-described embodiment. In addition to the above-described current mirror structure, as shown in fig. 3, the current mirror adopts a cam structure. The structure of the current mirror is composed of MP10, MP11, MP20, MP21, MP30 and MP 31. The gates of MP21 and MP31 are connected with the gate of MP11, and the gates of MP20 and MP30 are connected with the gate of MP 10. The drain of MP11 is connected to the source of MP10, the drain of MP21 is connected to the source of MP20, and the drain of MP31 is connected to the source of MP 30. The proportional relation of the mirror images of the current mirror is determined by the width-to-length ratio of MP11, MP31 and MP 21. As shown in fig. 4, the current mirror is another form of a cascode structure. The current mirror is composed of MP100, MP110, MP200, MP210, MP300, MP 310. The gate of MP110 is connected to the drain of MP100, one end of resistor R4 is connected to the drain of MP100, and the gate of MP100 is connected to the other end of the resistor. The gates of MP210, MP310 are connected to the gate of MP110, and the gates of MP200, MP300 are connected to the gate of MP 100. The drain of MP110 is connected to the source of MP100, the drain of MP201 is connected to the source of MP200, and the drain of MP310 is connected to the source of MP 300. The proportional relationship of the current mirror images is determined by the width-to-length ratios of MP110, MP310, MP 210. Those skilled in the art can flexibly set according to their own needs.
The enabling circuit, the first current limit reference generating circuit and the second current limit reference generating circuit are all arranged in the chip; the chip is an integrated circuit chip.
As shown in fig. 5, a current limit setting circuit, which is matched with the current limit reference generating circuit, comprises a first resistor R1; one end of the first resistor R1 is connected with the GPIO signal control end, and the other end of the first resistor R1 is connected with the current limit gating control signal input end.
The current limit setting circuit is arranged outside the chip, and the current limit reference generating circuit is arranged in the chip; the chip is an integrated circuit chip. In the off-chip outpide part, the GPIO signal terminal is a programmable signal, and different current limit setting schemes can be selected by giving a high level or a low level. And the on-chip INSIDE part generates different current limit references according to the high point level of the GPIO signal.
The benefits and advantages of the present invention are further illustrated by comparing it to a conventional current limit setting scheme.
As shown in fig. 6, the off-chip current limit setting section 5 has 2 GPIO signal control terminals, 2 current limiting resistors, and 2 MOS transistors for switching. The on-chip current limit reference generation circuit 6 includes a clamp OP3 and source follower MN6, and a pair of current mirrors MP6 and MP7.
When the voltage VREF3 of the non-inverting input end of the operational amplifier OP3 is not lower than the voltage of the inverting input end, the operational amplifier is clamped, so that the inverting voltage of the operational amplifier is equal to VREF3, namely the voltage of the source end of MN6 is VREF3.
When GPIO1 is high and GPIO2 is low, MOS tube MN4 is opened and MN5 is closed, at the moment, the branch where the on-chip external sorting is conducted with R3 is located, so that the current flowing through MN6 is VREF3/R5, and therefore the current limit reference obtained by mirror image of the current mirror is: i limit3 = VREF3/R5；
When GPIO1 is low and GPIO2 is high, MOS transistor MN4 is turned off and MN5 is turned on, and the external switch is selected from the branch where R4 is locatedTherefore, the current flowing through MN6 is VREF3/R6, and thus the current limit reference obtained by mirroring the current mirror is: i limit4 = VREF3/R6。
As can be seen from the above, the conventional current limit setting scheme can also provide various current limit references, but two GPIO signal control terminals, two current limiting resistors and two MOS transistors as switching tubes are required for the off-chip portion when two schemes are provided. In contrast, the structure provided by the invention only needs one current limiting resistor and one GPIO signal control terminal at the same time of providing two current limiting solutions. In circuits, the switching tubes and the excessive GPIO ports of the off-chip portion add additional design costs.
Claims (6)
1. A current limit reference generation circuit, characterized in that: the circuit comprises an enabling circuit, a first current limit reference generating circuit and a second current limit reference generating circuit; the enabling circuit is an enabling circuit of a gating current limit reference scheme;
the first current limit reference generating circuit comprises a first current mirror circuit, a first clamping circuit, a current limit gating control signal input end and a first current limit signal output end; the first clamping circuit comprises a first operational amplifier OP1 and a first NMOS tube MN1; the non-inverting input end of the first operational amplifier OP1 is connected with a first reference voltage VREF1, and the inverting input end of the first operational amplifier OP1 is connected with the source electrode of the first NMOS tube MN1 and is connected to the current limit gating control signal input end; the first current mirror circuit is configured to mirror the drain current of the first NMOS MN1 to the mirror current output; the mirror current output end comprises a first current limit signal output end;
the enabling circuit comprises an image current circuit, a bias current source circuit and an inverter; the mirror current circuit is matched with the first current mirror circuit to obtain the mirror current of the first mirror circuit; the bias current source circuit is connected with the current output end of the mirror current circuit and is connected with bias voltage to generate bias current; the input end of the inverter is connected with the current output end of the mirror current circuit;
the second current limit reference generating circuit comprises a circuit enabling end, a second current mirror circuit, a second clamping circuit and a second current limit signal output end; the circuit enabling end is connected with the output end of the phase inverter; the second clamping circuit comprises a second operational amplifier OP2 and a third NMOS tube MN3; the non-inverting input end of the second operational amplifier OP2 is connected with the second reference voltage VREF2, and the inverting input end of the second operational amplifier OP2 is connected with the source electrode of the third NMOS tube MN3 and is grounded through a second resistor R2; the second current mirror circuit is configured to mirror the drain current of the third NMOS MN3 to the mirror current output; the mirror current output end comprises a second current limit signal output end;
the bias current source circuit comprises a second NMOS tube MN2, the drain electrode of the second NMOS tube is connected with the current output end of the mirror current circuit, the grid electrode of the second NMOS tube is connected with bias voltage Vbias, and the source electrode of the second NMOS tube is grounded;
the mirror current circuit comprises a second PMOS tube MP2, a source electrode is connected with a power supply VDD, a grid electrode is connected with a grid electrode of the first PMOS tube MP1, and a drain electrode is connected with a current output end of the mirror current circuit.
2. The current limit reference generation circuit of claim 1, wherein: the first current mirror circuit comprises a first PMOS tube MP1 and a third PMOS tube MP3; the source electrode of the first PMOS tube MP1 is connected with the power supply VDD, and the drain electrode and the grid electrode are in short circuit and are respectively connected to the drain electrode of the first NMOS tube MN1 and the grid electrode of the third PMOS tube MP3; the source electrode of the third PMOS tube MP3 is connected with the power supply VDD, and the drain electrode is connected with the first current limit signal output end.
3. The current limit reference generation circuit of claim 1, wherein: the second current mirror circuit comprises a fourth PMOS tube MP4 and a fifth PMOS tube MP5; the source electrode of the fourth PMOS tube MP4 is connected with the power supply VDD, and the drain electrode and the grid electrode are in short circuit and are respectively connected to the drain electrode of the third NMOS tube MN3 and the grid electrode of the fifth PMOS tube MP5; the source electrode of the fifth PMOS tube MP5 is connected with the power supply VDD, and the drain electrode is connected with the second current limit signal output end.
4. A current limit reference generating circuit according to any one of claims 1 to 3, wherein: the enabling circuit, the first current limit reference generating circuit and the second current limit reference generating circuit are all arranged in the chip; the chip is an integrated circuit chip.
5. A current limit setting circuit, in cooperation with the current limit reference generating circuit according to any one of claims 1 to 4, characterized in that: comprises a first resistor R1; one end of the first resistor R1 is connected with the GPIO signal control end, and the other end of the first resistor R1 is connected with the current limit gating control signal input end.
6. The current limit setting circuit according to claim 5, wherein: the current limit setting circuit is arranged outside the chip, and the current limit reference generating circuit is arranged in the chip; the chip is an integrated circuit chip.
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| CN201810140115.9A CN108279733B (en) | 2018-02-11 | 2018-02-11 | Current limit reference generation circuit and setting circuit |
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| CN201810140115.9A CN108279733B (en) | 2018-02-11 | 2018-02-11 | Current limit reference generation circuit and setting circuit |
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