CN108279733A - A kind of electric current limit reference generating circuit and initialization circuit - Google Patents
A kind of electric current limit reference generating circuit and initialization circuit Download PDFInfo
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- G—PHYSICS
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
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Abstract
The present invention provides a kind of electric current limit reference generating circuit and initialization circuits, including core on-chip circuit and off-chip circuitry；The off-chip circuitry includes electric current limit initialization circuit；The core on-chip circuit includes that enabled circuit, the first electric current limit reference generating circuit and the second electric current limit reference generating circuit；The enabled circuit is the enabled circuit that gated current limits reference scheme；Reference generating circuit clamping action and the effect of comparing are limited by the first electric current, current mirror to the first electric current is limited into reference output and enabled circuit, when the current mirror in enabled circuit has electric current, close the second electric current limit reference generating circuit, when application conditions need optional electric current to limit setting scheme, the different electric current of control selections can be carried out by programmable GPIO signal ports and limits setting scheme, while using less GPIO port and without using the switch class formation outside piece, controlling cost.Compared with traditional electric current limit setting scheme, the invention is programmable simultaneously in electric current limit setting, provides the solution of low cost.
Description
Technical field
The present invention relates to a kind of electric current limit reference generating circuit and initialization circuits, are related to integrated circuit fields.
Background technology
In current integrated circuit technique, circuit protection mechalusm is the critical function that all power supply interlock circuits have,
Wherein current limit technical relation has significant impact to key factors such as entire circuit safety works, is extensive at present
The problem of research.In current limit technology, often under different application conditions, the requirement to current limit is different, thus often
Often need can self-defined or programmable electric current limit setting scheme.
Electric current limits the generation of reference current, can generally be obtained by a fixed reference voltage divided by a resistance.It is logical
It crosses and this resistance is altered or modified, you can obtain different electric current limit reference currents.But in practical engineering application, in circuit
The resistance set is generally difficult to directly replace, therefore can export GPIO signals to default by programmable obtained universal input
Good multichannel resistance is gated.By such mode, can with according to different needs, obtaining different electric currents limits benchmark, but
In practical application, the cost of GPIO signal ports is higher, especially true when using multiple GPIO ports, meanwhile, outside chip
Construction of switch of the portion by the control of GPIO signals for gating is also required to certain cost.Therefore, traditional electric current limit setting method is wanted
Single electric current limit or with high costs can only be provided.
Invention content
The present invention provides a kind of efficient electric currents to limit reference generating circuit, has and only needs according to the limit gating of electric current all the way
Signal is controlled, different electric current limits can be generated, and convenient for exporting GPIO signals to default by programmable obtained universal input
The feature that good multichannel resistance is gated.
The present invention also provides a kind of electric currents to limit initialization circuit, matches, has with above-mentioned electric current limit reference generating circuit
It is programmable, it is at low cost, it is only necessary to which that electric current limits gate control signal all the way, it will be able to generate the feature of different electric current limits.
According to a kind of electric current limit reference generating circuit provided by the invention, it is characterised in that：Including enabled circuit, the first electricity
Ductility limit reference generating circuit and the second electric current limit reference generating circuit；The enabled circuit is that gated current limits making for reference scheme
It can circuit；
The first electric current limit reference generating circuit includes the first current mirroring circuit, the first clamp circuit, electric current limit gating control
Signal input part and the first electric current limit signal output end；First clamp circuit includes the first amplifier OP1 and the first NMOS tube
MN1；The normal phase input end of the first amplifier OP1 meets the first reference voltage VREF1, inverting input and the first NMOS tube MN1
Source electrode be connected, and be connected to electric current limit gate control signal input terminal；First current mirroring circuit is used for the first NMOS tube
The drain terminal current mirror of MN1 is to image current output end；The image current output end includes that the first electric current limits signal output end；
The enabled circuit includes circuit mirror current, bias current source circuit and phase inverter；The circuit mirror current and institute
The cooperation of the first current mirroring circuit is stated, the image current of the first mirror image circuit is obtained；The bias power supply circuit and image current electricity
The current output terminal on road is connected, and connects bias voltage, generates bias current；The inverter input connects circuit mirror current
Current output terminal；
Second electric current limit reference generating circuit includes circuit Enable Pin, the second current mirroring circuit, the second clamp circuit and the
Two electric currents limit signal output end；The output end of the enabled termination phase inverter of the circuit；Second clamp circuit includes the
Two amplifier OP2 and third NMOS tube MN3；The normal phase input end of the second amplifier OP2 connects the second reference voltage VREF1, reverse phase
Input terminal is connected with the source electrode of third NMOS tube MN3, and is grounded by second resistance R2；Second current mirroring circuit is used for will
The drain terminal current mirror of third NMOS tube MN3 is to image current output end；The image current output end is limited including the second electric current
Signal output end.
The bias current source circuit includes the second NMOS tube MN2, the current output terminal phase to drain with circuit mirror current
Even, grid connects bias voltage Vbias, source electrode ground connection.
First current mirroring circuit includes the first PMOS tube MP1 and third PMOS tube MP3；The first PMOS tube MP1
Source electrode meet power vd D, drain electrode is with grid short circuit and is respectively connected to drain electrode and the third PMOS tube MP3 of the first NMOS tube MN1
Grid；The source electrode of the third PMOS tube MP3 meets power vd D, and drain electrode connects the first electric current limit signal output end.
The circuit mirror current includes the second PMOS tube MP2, and source electrode meets power vd D, and grid connects the first PMOS tube MP1's
Grid, drain electrode connect the current output terminal of circuit mirror current.
Second current mirroring circuit includes the 4th PMOS tube MP4 and the 5th PMOS tube MP5；The 4th PMOS tube MP4
Source electrode meet power vd D, drain electrode is with grid short circuit and is respectively connected to drain electrode and the 5th PMOS tube MP5 of third NMOS tube MN3
Grid；The source electrode of the 5th PMOS tube MP5 meets power vd D, and drain electrode connects the second electric current limit signal output end.
The enabled circuit, the first electric current limit reference generating circuit and the second electric current limit reference generating circuit are all set to
In chip；The chip is IC chip.
A kind of electric current limit initialization circuit is matched with above-mentioned electric current limit reference generating circuit, it is characterised in that：Including first
Resistance R1；The one end the first resistor R1 is connected with GPIO signal control terminals, and the other end is for connecting the electric current limit gating control
Signal input part processed.
The electric current limit initialization circuit is set to outside chip, and electric current limit reference generating circuit is set in chip；The core
Piece is IC chip.
Compared with prior art, the beneficial effects of the invention are as follows：Optional electric current is needed to limit setting scheme in application conditions
When, the different electric current of control selections can be carried out by programmable GPIO signal ports and limits setting scheme, while using less
GPIO port and without using the switch class formation outside piece, controls cost.Compared with traditional electric current limit setting scheme, the invention
It is programmable simultaneously in electric current limit setting, provide the solution of low cost.
Description of the drawings
Fig. 1 is the theory structure schematic diagram that electric current of the present invention limits one embodiment of reference generating circuit.
Fig. 2 is the theory structure schematic diagram that the second electric current of the invention limits one embodiment of reference generating circuit.
Fig. 3 is a kind of example of current mirroring circuit.
Fig. 4 is a kind of example of current mirroring circuit.
Fig. 5 is the principle that electric current of the present invention limits reference generating circuit and the electric current coordinated with it limit one embodiment of initialization circuit
Structural schematic diagram.
Fig. 6 is a kind of theory structure schematic diagram for traditional structure that electric current limits setting scheme.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that described herein, specific examples are only used to explain the present invention, not
For limiting the present invention.
This specification（Including abstract and attached drawing）Disclosed in any feature unless specifically stated can be equivalent by other
Or the alternative features with similar purpose are replaced.That is, unless specifically stated, each feature is a series of equivalent or class
Like an example in feature.
According to a kind of electric current limit reference generating circuit provided by the invention, as shown in Figure 1, including the 3, first electricity of enabled circuit
Ductility limit reference generating circuit 1 and the second electric current limit reference generating circuit 2；The enabled circuit 3 is that gated current limits reference scheme
Enabled circuit；
The first electric current limit reference generating circuit 1 includes the first current mirroring circuit, the first clamp circuit, electric current limit gating control
Signal input part and the first electric current limit signal output end；First clamp circuit includes the first amplifier OP1 and the first NMOS tube
MN1；The normal phase input end of the first amplifier OP1 meets the first reference voltage VREF1, inverting input and the first NMOS tube MN1
Source electrode be connected, and be connected to electric current limit gate control signal input terminal；First current mirroring circuit is used for the first NMOS tube
The drain terminal current mirror of MN1 is to image current output end；The image current output end includes that the first electric current limits signal output end；
The enabled circuit includes circuit mirror current, bias current source circuit and phase inverter INV1；The circuit mirror current
Coordinate with first current mirroring circuit, obtains the image current of the first mirror image circuit；The bias power supply circuit and mirror image electricity
The current output terminal of current circuit is connected, and connects bias voltage, generates bias current；The inverter input connects image current electricity
The current output terminal on road；
As shown in Fig. 2, the second electric current limit reference generating circuit includes circuit Enable Pin Ven（The signal intelligent allows the part
Circuit is enabled or turns off, and is not limited to the specific position of circuit content）, the second current mirroring circuit, the second clamp circuit and second electricity
Ductility limit signal output end；The output end of the enabled termination phase inverter of the circuit；Second clamp circuit includes the second fortune
Put OP2 and third NMOS tube MN3；The normal phase input end of the second amplifier OP2 connects the second reference voltage VREF1, anti-phase input
End is connected with the source electrode of third NMOS tube MN3, and is grounded by second resistance R2；Second current mirroring circuit is used for third
The drain terminal current mirror of NMOS tube MN3 is to image current output end；The image current output end includes that the second electric current limits signal
Output end.
First NMOS tube MN1 as the first amplifier OP1 with source device, when the normal phase input end voltage of the first amplifier OP1
When VREF1 is not less than anti-phase input terminal voltage, anti-phase input terminal voltage is equal to VREF1, i.e. MN1 source voltage terminals are VREF1.When
When GPIO signals are low level 0 outside matched electric current limit initialization circuit, with the concatenated first resistor of GPIO signal input parts
The pressure drop at the both ends R1 is VREF1, therefore electric current I can be generated on first resistor R10, I0Value be VREF1/R1；Electric current I0Stream
After the first NMOS tube MN1, by the current output terminal of current mirror mirror image to circuit mirror current, the first electric current limit benchmark is obtained
Ilimit1.At this point, enabled circuit 3 is similarly obtained the image current I of the first mirror image circuit1, enable bias supply in circuit 3 and pass through
The bias supply Vbisa set so that biasing circuit IbiasLess than electric current I1.Therefore, when enabled current mirror has electric current,
Because of I1>Ibias, the input terminal A point voltages of phase inverter INV1 can be pulled to high level so that the output end enable signal of INV1
Ven is low level, and the second electric current limit reference generating circuit 2 does not work at this time.Therefore, external GPIO signals are being programmed for low electricity
When flat 0, electric current limit setting scheme one is obtained：First electric current limits reference generating circuit and generates the first electric current limit benchmark Ilimit1；Second
Electric current limit reference generating circuit does not work.
GPIO signals are high level 1 outside matched electric current limit initialization circuit, and high level is more than mono- tenterings of VREF1
When spending, the first amplifier OP1 is used as comparator at this time, since inverting input input voltage is higher than normal phase input end input voltage,
Comparator exports low level so that the first NMOS tube MN1 is turned off, at this time electric current I0It is 0, obtains the first electric current limit benchmark and generate electricity
Road no current output, enables in circuit, electric current I10, A point voltages are similarly by the electric current I of bias current sourcesbiasIt is pulled down to low electricity
Position so that the output enable signal Ven of phase inverter INV1 is height, enables the second electric current limit benchmark Ilimit1, obtain electric current limit setting
Scheme two：First electric current limit reference generating circuit does not work；Second electric current limits reference generating circuit and generates the second electric current limit benchmark
Ilimit2。
On the basis of electric current limits the circuit structure of reference generating circuit, it is only necessary to which a GIPO signal input part and one are set
A current-limiting resistance（First resistor R1）, outside need not include any type of switch class formation, you can realizing has only needs
Gate control signal is limited according to electric current all the way, generates different electric current limits, and convenient for passing through programmable obtained universal input output
The function that GPIO signals gate the multichannel resistance preset.Therefore, the electric current of the present patent application limits reference generating circuit
It is easy to implement and only needs, according to the limit gate control signal of electric current all the way, different electric current limits can be generated, and convenient for by programmable
The function that obtained universal input output GPIO signals gate the multichannel resistance preset.
As an embodiment of the present invention, the bias current source circuit includes the second NMOS tube MN2, drain electrode and mirror image
The current output terminal of current circuit is connected, and grid connects bias voltage Vbias, source electrode ground connection.Bias current sources MN2 is by setting
Bias voltage Vbisa so that bias current IbiasLess than electric current I1。
As an embodiment of the present invention, first current mirroring circuit includes the first PMOS tube MP1 and the 3rd PMOS
Pipe MP3；The source electrode of the first PMOS tube MP1 connects power vd D, drain electrode and grid short circuit and is respectively connected to the first NMOS tube
The grid of the drain electrode and third PMOS tube MP3 of MN1；The source electrode of the third PMOS tube MP3 meets power vd D, and drain electrode connects the first electricity
Ductility limit signal output end.In this embodiment, mirroring ratios are that 1 to 1 relationship limits benchmark I to get to the first electric currentlimit1=
VREF1/R1.When GPIO is low level 0, electric current I0After the first NMOS tube MN1, by current mirror MP1 mirror images to MP3, this
When, the first electric current can be obtained in the drain terminal of MP3 and limit benchmark.
As an embodiment of the present invention, the circuit mirror current includes the second PMOS tube MP2, and source electrode connects power supply
VDD, grid connect the grid of the first PMOS tube MP1, and drain electrode connects the current output terminal of circuit mirror current.In this specific embodiment
In, mirroring ratios are 1 to 1 relationship.When GPIO is low level 0, electric current I0After the first NMOS tube MN1, pass through current mirror MP1
Mirror image obtains I at this time to MP21= I0。
As an embodiment of the present invention, second current mirroring circuit includes the 4th PMOS tube MP4 and the 5th PMOS
Pipe MP5；The source electrode of the 4th PMOS tube MP4 connects power vd D, drain electrode and grid short circuit and is respectively connected to third NMOS tube
The drain electrode of MN3 and the grid of the 5th PMOS tube MP5；The source electrode of the 5th PMOS tube MP5 meets power vd D, and drain electrode connects the second electricity
Ductility limit signal output end.In this embodiment, mirroring ratios are 1 to 1 relationship.When receiving high level enable signal,
Second electric current limits benchmark Ilimit2Generation circuit 4 start to work；The positive input terminal voltage VREF2 of second amplifier OP2 is not less than negative
When input terminal voltage, clamping action is played, its negative terminal voltage is made to be equal to VREF2, is i.e. MN3 source voltage terminals are VREF2.At this point, second
The pressure drop at the both ends resistance R2 is VREF2, and the electric current for flowing through R2 is：Ilimit2=VREF2/R2。
Mirror image circuit structure and mirroring ratios in above-described embodiment are not limited to for mirror image circuit.Except above-mentioned current mirror
Outside structure, as shown in figure 3, current mirror uses cascode structures.The structure of current mirror by MP10, MP11, MP20, MP21,
MP30, MP31 are formed.MP11 and MP10 grid leak short circuits, the grid of MP21, MP31 are connected with the grid of MP11, MP20, MP30's
Grid is connected with the grid of MP10.The drain electrode of MP11 is connected with the source electrode of MP10, and the drain electrode of MP21 is connected with the source electrode of MP20,
The drain electrode of MP31 is connected with the source electrode of MP30.The proportionate relationship of current mirror mirror image is determined by the breadth length ratio of MP11, MP31, MP21.
As shown in figure 4, current mirror is another form of cascode structures.Current mirror by MP100, MP110, MP200, MP210,
MP300, MP310 are formed.The grid of MP110 is connected to the drain terminal of MP100, and mono- ends resistance R4 are connected on the drain electrode of MP100, MP100's
Grid is connected in the other end of the resistance.The grid of MP210, MP310 are connected with the grid of MP110, the grid of MP200, MP300 with
The grid of MP100 is connected.The drain electrode of MP110 is connected with the source electrode of MP100, and the drain electrode of MP201 is connected with the source electrode of MP200,
The drain electrode of MP310 is connected with the source electrode of MP300.The proportionate relationship of current mirror mirror image, by the breadth length ratio of MP110, MP310, MP210
It determines.Those skilled in the art can be flexibly arranged according to the demand of oneself.
The enabled circuit, the first electric current limit reference generating circuit and the second electric current limit reference generating circuit are all set to
In chip；The chip is IC chip.
As shown in figure 5, a kind of electric current limits initialization circuit, matched with above-mentioned electric current limit reference generating circuit, including first
Resistance R1；The one end the first resistor R1 is connected with GPIO signal control terminals, and the other end is for connecting the electric current limit gating control
Signal input part processed.
The electric current limit initialization circuit is set to outside chip, and electric current limit reference generating circuit is set in chip；The core
Piece is IC chip.The outer parts OUTSIDE of piece, GPIO signal ends are programmable signal, can by provide high level or
Low level selects the different electric current to limit setting scheme.The parts INSIDE in piece generate not according to the high level point of GPIO signals
Same electric current limits benchmark.
Scheme comparison, the benefit that the present invention is further explained are set below by by the present invention and a kind of traditional electric current limit
With advantage.
As shown in fig. 6, piece dispatch from foreign news agency ductility limit setting section 5 has 2 GPIO signals control terminals, 2 current-limiting resistances and 2 conducts
The metal-oxide-semiconductor of switch.Electric current limit reference generating circuit 6 in piece includes the amplifier OP3 and source follower MN6 of a clamping action,
And a pair of of current mirror MP6 and MP7.
When the normal phase input end voltage VREF3 of amplifier OP3 is not less than anti-phase input terminal voltage, clamping action is played, keeps it anti-
Phase voltage is equal to VREF3, i.e. MN6 source voltage terminals are VREF3.
When GPIO1 is height, and GPIO2 is low, metal-oxide-semiconductor MN4 is opened and MN5 is turned off, this time slice outer portion gates where R3
Branch, therefore the electric current for flowing through MN6 is VREF3/R5, therefore the electric current limit benchmark that current mirror mirror image obtains is：Ilimit3= VREF3/
R5；
When GPIO1 is low, when GPIO2 is high, metal-oxide-semiconductor MN4 is turned off and MN5 is opened, this time slice outer portion gates branch where R4
Road, therefore the electric current for flowing through MN6 is VREF3/R6, therefore the electric current limit benchmark that current mirror mirror image obtains is：Ilimit4= VREF3/
R6。
From the foregoing, it can be seen that traditional electric current limit setting scheme can also provide a variety of electric current limit benchmark, but providing two kinds
Scheme time slice outer portion needs two GPIO signal control terminals, two current-limiting resistances and two metal-oxide-semiconductors effective as switch.With
Comparison, the structure given by the present invention, while proposing that two kinds of electric currents limit solution, piece outer portion only needs a limit
Leakage resistance and a GPIO signal control terminal.In circuit, the switching tube of piece outer portion and excessive GPIO port can increase additionally
Design cost.
Claims (8)
1. a kind of electric current limits reference generating circuit, it is characterised in that：Including enabled circuit, the first electric current limit reference generating circuit and
Second electric current limits reference generating circuit；The enabled circuit is the enabled circuit that gated current limits reference scheme；
The first electric current limit reference generating circuit includes the first current mirroring circuit, the first clamp circuit, electric current limit gating control
Signal input part and the first electric current limit signal output end；First clamp circuit includes the first amplifier OP1 and the first NMOS tube
MN1；The normal phase input end of the first amplifier OP1 meets the first reference voltage VREF1, inverting input and the first NMOS tube MN1
Source electrode be connected, and be connected to electric current limit gate control signal input terminal；First current mirroring circuit is used for the first NMOS tube
The drain terminal current mirror of MN1 is to image current output end；The image current output end includes that the first electric current limits signal output end；
The enabled circuit includes circuit mirror current, bias current source circuit and phase inverter；The circuit mirror current and institute
The cooperation of the first current mirroring circuit is stated, the image current of the first mirror image circuit is obtained；The bias power supply circuit and image current electricity
The current output terminal on road is connected, and connects bias voltage, generates bias current；The inverter input connects circuit mirror current
Current output terminal；
Second electric current limit reference generating circuit includes circuit Enable Pin, the second current mirroring circuit, the second clamp circuit and the
Two electric currents limit signal output end；The output end of the enabled termination phase inverter of the circuit；Second clamp circuit includes the
Two amplifier OP2 and third NMOS tube MN3；The normal phase input end of the second amplifier OP2 connects the second reference voltage VREF1, reverse phase
Input terminal is connected with the source electrode of third NMOS tube MN3, and is grounded by second resistance R2；Second current mirroring circuit is used for will
The drain terminal current mirror of third NMOS tube MN3 is to image current output end；The image current output end is limited including the second electric current
Signal output end.
2. electric current according to claim 1 limits reference generating circuit, it is characterised in that：The bias current source circuit includes
Second NMOS tube MN2, drain electrode are connected with the current output terminal of circuit mirror current, and grid meets bias voltage Vbias, and source electrode connects
Ground.
3. electric current according to claim 1 limits reference generating circuit, it is characterised in that：First current mirroring circuit includes
First PMOS tube MP1 and third PMOS tube MP3；The source electrode of the first PMOS tube MP1 connects power vd D, drain electrode and grid short circuit
And it is respectively connected to the grid of the drain electrode and third PMOS tube MP3 of the first NMOS tube MN1；The source electrode of the third PMOS tube MP3
Power vd D is met, drain electrode connects the first electric current limit signal output end.
4. electric current according to claim 1 limits reference generating circuit, it is characterised in that：The circuit mirror current includes the
Two PMOS tube MP2, source electrode meet power vd D, and grid connects the grid of the first PMOS tube MP1, and drain electrode connects the electric current of circuit mirror current
Output end.
5. electric current according to claim 1 limits reference generating circuit, it is characterised in that：Second current mirroring circuit includes
4th PMOS tube MP4 and the 5th PMOS tube MP5；The source electrode of the 4th PMOS tube MP4 connects power vd D, drain electrode and grid short circuit
And it is respectively connected to drain electrode and the grid of the 5th PMOS tube MP5 of third NMOS tube MN3；The source electrode of the 5th PMOS tube MP5
Power vd D is met, drain electrode connects the second electric current limit signal output end.
6. the electric current according to one of claim 1 to 5 limits reference generating circuit, it is characterised in that：The enabled circuit,
One electric current limits reference generating circuit and the second electric current limit reference generating circuit is all set in chip；The chip is integrated electricity
Road chip.
7. a kind of electric current limits initialization circuit, matched with above-mentioned electric current limit reference generating circuit, it is characterised in that：Including the first electricity
Hinder R1；The one end the first resistor R1 is connected with GPIO signal control terminals, and the other end is for connecting the electric current limit gating control
Signal input part.
8. electric current according to claim 1 limits initialization circuit, it is characterised in that：The electric current limit initialization circuit is set to core
Outside piece, electric current limit reference generating circuit is set in chip；The chip is IC chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810140115.9A CN108279733B (en) | 2018-02-11 | 2018-02-11 | Current limit reference generation circuit and setting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810140115.9A CN108279733B (en) | 2018-02-11 | 2018-02-11 | Current limit reference generation circuit and setting circuit |
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| CN108279733A true CN108279733A (en) | 2018-07-13 |
| CN108279733B CN108279733B (en) | 2023-12-05 |
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| CN201810140115.9A Active CN108279733B (en) | 2018-02-11 | 2018-02-11 | Current limit reference generation circuit and setting circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113571011A (en) * | 2021-08-11 | 2021-10-29 | 中科芯集成电路有限公司 | Current mirror circuit with built-in resistance type LED display driving chip |
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| CN108279733B (en) | 2023-12-05 |
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