CN103647543A - High-speed data transceiver - Google Patents
High-speed data transceiver Download PDFInfo
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- CN103647543A CN103647543A CN201310612084.XA CN201310612084A CN103647543A CN 103647543 A CN103647543 A CN 103647543A CN 201310612084 A CN201310612084 A CN 201310612084A CN 103647543 A CN103647543 A CN 103647543A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
A high-speed data transceiver is provided. A driving stage includes a bias voltage regulator and is a drive stage of each transceiver and adjusts a base drive, and achieves rapid and stable delay spread under different supply voltage and temperature. An input capacitor which is connected on a voltage bias input line provides instant base driving to an output drive such that fast switching on can be realized without direct current added. Two pairs of miller capacitance transceivers are connected between a driving stage data input end of a transceiver and the collector of the output drive and control the output conversion rate of the drives. A discharge capacitance-type network is connected to the base of the output drive and provides an instant discharge path when the drive is disabled. At a receiving end, an ECC-TTL conversion stage lowers node capacitance so as to realize fast switching on. When a receiver is in a high-impedance state, a TTL output buffer region is logically grounded through using a backplane transceiver, and at this moment, ground consumes no power.
Description
Technical field:
The present invention relates to line interface equipment, relate in particular to the data collector of a high speed.
Background technology:
Data collector (emitter/receiver) is a read/write terminal, can be from transmission medium transmission information and reception information.Transceiver generally includes circuit driving stage and a receiver level.This line driver is the output of amplifier digital signal from computer system, and signal can be transmitted exactly on transmission medium.Traditional line driver generally includes level conversion ability, and for example, compatibility from different integrated circuit techniques (TTL) is provided, and may be used in computer-internal logic.Receiver is a differential amplifier normally, receives the signal on transmission medium, and an output is provided, the digital information that representative receives from medium.
Transceiver circuit can be designed as general application program, also can be designed to a data communication configuration that meets more specifically industrial standard.
Figure 1 shows that the hierarchical structure of available bus level.
Figure 2 shows that the location of the data collector between core bus and the data/address bus of processor inside, to promote the communication between processor and system remainder.
Although the version of the integrated circuit of data collector is provided, the driving stage of these transceivers and receiver have all shown weak point.As for driving stage, the transceiver in past shows asymmetric deflection, that is to say, the conversion of high to Low level is too fast, and the conversion of low to high level is too slow.In addition, traditional driving stage shows poor temperature and power source performance, consumes too much power.At receiving terminal, traditional transceiver has shown huge ground spring, follows the problem of stability and skew.
Therefore, have an available data collector, and provide transfer ratio to control, have better temperature and exchange performance with power supply, consume power still less, this is in demand.
Summary of the invention:
The invention provides Backplane Transceiver, logical data transceiver.
Technical solution of the present invention:
High-speed multiple channel data collector in the present invention, wherein driving stage comprises bias voltage pressurizer, the driving stage adjusting base drive for each transceiver, under different supply voltages and temperature conditions, realizes quick and stable propagation delay.Be connected to the input capacitance of voltage bias incoming line, provide instant base drive to output driver, in the situation that not adding direct current, open fast output driver.Two pairs of miller capacitance transceivers, are connected between the data input pin of transceiver driving stage and the collector electrode of output driver, control the output transfer ratio of driver.A discharge capacity formula network, is connected to the base stage of output driver, when driver is disabled, provides an instant discharge path.
At receiving terminal, ECC-TTL switching stage reduces node capacitor, and Quick shut-off device is provided.When receiver is during in high impedance status, the power of TTL output buffer consumption is zero.
By reference to the detailed description and the accompanying drawings below, wherein set forth an illustrative embodiment of utilizing feature of the present invention.This can be understood the feature and advantage of the data collector in the present invention better.
The high-speed data transceiver device 201120269780.1 of mono-kind of patent documentation: CN202178760U of contrast based on PCIE
Accompanying drawing explanation:
Figure 1 shows that the picture specification of the hierarchical structure of bus level in system.
Figure 2 shows that between the data/address bus of the processor in a core bus and system the block diagram of the placement of data collector.
Figure 3 shows that one according to the present invention the block diagram of the data collector of the high speed of principle.
Fig. 4 A and Fig. 4 B are depicted as two in the data collector shown in Fig. 3, spendable driving stage circuit diagram.
Fig. 5 be one in the data collector shown in Fig. 3, spendable voltage offset electric circuit schematic diagram.
Fig. 6 A-6C is depicted as three in the data collector shown in Fig. 3, spendable acceptor circuit schematic diagram.
Fig. 7 A-7B is depicted as two in the data collector shown in Fig. 3, spendable CD and T/A circuit diagram.
Fig. 8 be one in the data collector shown in Fig. 3, the spendable circuit diagram that arranges.
Fig. 9 be one in the data collector shown in Fig. 3, spendable band-gap circuit schematic diagram.
Embodiment:
Figure 3 shows that one according to the present invention the block diagram of the data collector 10 of the high speed of principle.Transceiver 10 comprises nine passage 1-9, and each passage has a pair of driver 12 and receiver 14.(T/R & CD) sending/receiving control piece 16 of a chip forbidding, can enable and forbid driver 12 and receiver 14, and this has more detailed description below.Piece 18 is set and guarantees that the output of driver 12 and receiver 14 is noiseless between charging and turnoff time.Band gap reference voltage piece 20(V
ref) provide reference voltage to be input to all receivers 14.Principle aspect according to the present invention, just as described in more detail below, biased electrical briquetting 22(V
biasing) be that each driver 12 regulates base drive, under different power supplys and temperature operation condition, realize quick and stable propagation delay.
Fig. 4 A and 4B are depicted as the embodiment of a drive circuit 12 of principle according to the present invention.Driver 12 is a frequency converter substantially, can be at its output B
ncollect 80 milliamperes, V
olbe less than 1.1 volts of IEEE PI194.1(BTL standards).As described below, driver 12 has been shown the low deflection time (being typically for 2 nanoseconds), controls the rise/fall time (2-5 nanosecond), and fast propagation postpones (4-5 nanosecond).
As shown in Figure 4, when being connected to the data input pin of driver 12 and being low level, transistor Q
q4with transistor Q
q4aclose.Therefore, owing to lacking base drive, output transistor Q
q8keep closed condition.As data input pin A
nwhile becoming high level, transistor Q
q4with transistor Q
q4aprovide ideal base drive current to output transistor Q
q8, make the collector electrode Q of output transistor
q8from its load, at least collect 80mA electric current.
Capacitor Q 155 provides instant base drive, opens fast output transistor Q
q8, without increasing more direct current (DC power supply).In addition, the two couples of miller capacitance transistor Q167/Q168 and Q163/Q164 are used for controlling the output transfer ratio of driver.
Be connected to the V of driver 12
biasingsignal remains at the above 4V in ground
bE.With reference to Fig. 5, no matter supply voltage V
cClevel, when temperature uprises, V
biasingreduce, vice versa.More particularly, Figure 5 shows that a voltage offset electric circuit 22, comprise the character string of a serial, this character string comprises the transistor Q that diode connects
qs0-Q
qs4, and the 2K resistor R of
rsthey are connected to supply voltage V
cCand between ground.Be connected in V in parallel
cCand be a resistor network (R between ground
121, R
121A, R
r13, R
r13A), they have resistor R
rs1/8 resistance.Therefore, the output voltage V of voltage offset electric circuit 22
biasingequal supply voltage V
cCdeduct dividing potential drop X/8X and the npn output transistor Q of parallel network
q2voltage drop V
bE.Be equivalent to following formula:
Output transistor Q in driving stage 10
q8ideal base drive current I
bby following formula, provided:
Ideal base drive current I
balong with the rising of temperature, reduce, when temperature raises, I
bprovide less base drive to output transistor Q
q8.Due to transistor Q
q8memory time with temperature, increase, above-mentioned voltage bias scheme can postpone the dependence phenomenon to temperature.
Drive the down periods, by input Schottky gesture diode D
d1, diode Q
q4/ Q
q4acan close rapidly.But, the stored charge Q of output transistor
q8can only discharge by resistance R 176/R177/R178 and Schottky gesture diode D139.
About the problem of opening and turn-offing controllable transfer ratio, with reference to figure 4A.As shown in FIG., as input signal A
nwhile being applied to the base stage of NPN transistor Q10, transistor Q10 conducting, and from the base stage Q of output transistor
q8(seeing Fig. 4 B) provides a kind of discharge path fast.A capacitive discharge network, comprises capacitor Q 159, is connected to the base stage Q of output transistor
q8and between ground, when driver is disabled, provide instant discharge path.In addition, miller capacitance Q155 and Q184, be connected between the data input pin and output transistor Qq8 of driving stage, controls the output transfer ratio of driver.
As input signal A
nbe low level and transistor Q10 while closing, electric capacity Q159 is output transistor Q
q8transient switching electric current is provided.Electric current flows to the base stage of transistor Qq8 from capacitor Q 155 and Q184, make its transient switching.The trailing edge of output signal is by electric capacity Q163, Q164, and the Miller capacitor that Q167 and Q168 provide is controlled.Resistor R176, R177 and R178 are the rising edges for control output end.
By opening transistor Q10, capacitor triode Q159 provide the path that sparks.
The receiver 14 of transceiver 10, is an embodiment shown in Fig. 6, comprises two input stages, an ECL-TTL switching stage and a TTL output buffer.
As further shown in Figure 6, Schottky gesture diode D35/D36, when it is grounded, is used for stoping flowing to power supply V
cCcurrent path.The second input stage has increased extra gain.
In ECL-TTL switching stage, ECL-TTL speed-up condenser transistor Q6 is connected to the base stage of transistor Q12, rather than is connected in a usual manner the collector electrode of transistor Q15.This scheme has reduced the capacitance relevant to dividing mutually transistor Q95.
At p channel transistor M104, in "off" state, N channel transistor M108 is in "open" state, and under such tri-state environment, output TTL buffer is consumes zero power substantially.
The inhibit signal of three-state control signal in Fig. 6 A provides, as Fig. 6 A, and shown in 6B and 6C, the open/close state of inhibit signal control device M108 and shearing device M104.
In addition, TTL output buffer relies on Backplane Transceiver logic ground and returns to ground, rather than logic ground in a conventional manner, and this is by the ground bounce-back that causes causing due to TTL current spike.Because ground bounce-back has reduced, passage to the skew of passage has reduced, so noise is minimized, and data are also more reliable.
Figure 7 shows that in a data collector 10 of the present invention the circuit diagram of spendable traditional CD and T/A logical one 6.
Figure 8 shows that in a data collector 10 of the present invention, spendable tradition arranges the schematic diagram of circuit 18.
Figure 9 shows that in a data collector 10 of the present invention the schematic diagram of spendable traditional band-gap circuit 20.
It should be understood that the multiple alternative method of embodiment of the present invention, also can apply in the present invention.Its objective is, claim below limits scope of the present invention, thereby contains the method and apparatus in the scope of these claims and equivalent thereof.
Claims (8)
1. the data collector of a high speed, it is characterized in that: biasing voltage regulator circuit, can be used to provide the driving stage of biasing voltage signal to the data collector of a high speed, biasing voltage regulator circuit comprises: (a) a kind of serial character string, this character string comprises the transistor that a plurality of diodes connect, and is connected in series in the resistive element between supply voltage and ground; (b) resistor network, and be connected to the serial character connection in series-parallel between supply voltage and ground, resistive element has had resistance, is the integral multiple of the resistance of resistor network; (c) npn output transistor, its collector electrode is connected to supply voltage, and base stage is connected with ground jointly with resistor network, and its emitter is connected to provide biasing voltage signal, thereby biasing voltage signal is the value of supply voltage independently, and variation with temperature is inversely proportional to.
2. the data collector of a kind of high speed according to claim 1, is characterized in that: the serial character string in biasing voltage regulator circuit has 5V
bEvoltage drop, the resistance of the resistive element in serial character string is the octuple of the resistance in resistor network, thus biasing voltage signal remains on the above 4V in ground
bE.
3. the data collector of a kind of high speed according to claim 1, is characterized in that: driving stage circuit can be used in the data collector of a high speed, and this drive circuit comprises: (a) input node, receives a driving stage data input signal; (b) output node, provides the output signal of a driving stage; (c) a N channel output transistor, provides the node of the output signal of driving stage to driver; (d) switching device, be connected between input node and N channel output transistor, like this, when input signal is logic high, switching device provides base drive device to open output transistor to N channel output transistor, when input signal is logic low, switching device just cuts out output transistor; (e) the first capacitive means, is connected between input node and switching device, and when input signal is converted to logic high from logic low, the first capacitive means just provides the base stage of electric current to N channel output transistor.
4. the data collector of a kind of high speed according to claim 3, is characterized in that: driving stage circuit also comprises the second capacitive means, is connected between switching device and output node, for controlling the transfer ratio of the output signal of driving stage.
5. the data collector of a kind of high speed according to claim 3, is characterized in that: driving stage circuit also comprises: (a) discharge capacity device, is connected to the base stage of N channel output transistor; (b) output switch, be connected between a discharge capacity device and ground, and the high level of response data input signal is to low level conversion, make discharge capacity electric discharge, the base stage of output transistor is to the discharge path on ground, by discharge capacity device and output switch capacitive means, turn-off fast output transistor.
6. the data collector of a kind of high speed according to claim 3, is characterized in that: available acceptor circuit in the data collector of a high speed, comprising: (a) input node, for receiving the input signal of a receiver; (b) input stage device, it is connected on input node, and for the input signal of receiver being converted to corresponding ECL Difference signal pair, this ECL Difference signal pair, comprises the first and second ECL signals; (c) in response to ECL to the TTL converter apparatus of ECL Difference signal pair, a corresponding TTL logic level signal is provided, ECL to TTL converter apparatus comprises the (i) input transistors of a NPN switching stage, its collector electrode is connected to a supply voltage, its emitter is connected to an internal node, and its base stage is connected to receive an ECL signal; The input transistors of (II) the 2nd NPN switching stage, its collector electrode is connected to supply voltage, and its base stage is connected to receive the 2nd ECL signal; (iii) capacitive means is connected to the emitter of the input transistors of the first switching stage; (IV) electric discharge device is connected between capacitive means and ground, also be connected between the emitter and ground of the second switching stage input transistors, thereby an ECL signal by high level to low level conversion, cause internal node to forward a TTL logic low to, the conversion to high level by low level of the one ECL signal, causes internal node to forward a TTL logic high to.
7. the data collector of a kind of high speed according to claim 6, it is characterized in that: acceptor circuit also comprises a TTL output buffer, and it comprises: (a) a kind of NPN divides transistor mutually, and its base stage is connected to internal node, its grounded emitter, its collector coupled is to output node; (b) a N channel pull-down transistor, its drain electrode is connected to and divides mutually transistorized collector electrode, its source ground, its grid is coupled to the node of a forbidding, like this, an effective inhibit signal of high level that is applied to the node of forbidding, opens pull-down transistor, thereby output node is placed on to a high impedance status; (c) a P channel disable transistor, its source electrode is connected to supply voltage, its drain coupled is to dividing mutually transistorized collector electrode, its grid is connected to the node of forbidding, the effective inhibit signal of high level that makes to be like this applied to the node of forbidding is closed "off" transistor, thereby make when output node be during at high impedance status, the power of output buffer consumption is zero.
8. the data collector of a kind of high speed according to claim 7, is characterized in that: the TTL output buffer in acceptor circuit, depends on Backplane Transceiver, the ground connection using logic ground as acceptor circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310612084.XA CN103647543A (en) | 2013-11-26 | 2013-11-26 | High-speed data transceiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310612084.XA CN103647543A (en) | 2013-11-26 | 2013-11-26 | High-speed data transceiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103647543A true CN103647543A (en) | 2014-03-19 |
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ID=50252717
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310612084.XA Pending CN103647543A (en) | 2013-11-26 | 2013-11-26 | High-speed data transceiver |
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| Country | Link |
|---|---|
| CN (1) | CN103647543A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106603247A (en) * | 2015-10-15 | 2017-04-26 | 杭州硅星科技有限公司 | Data transceiver, transceiver system and control method of data transceiver |
| CN112491435A (en) * | 2019-08-23 | 2021-03-12 | 微芯片技术股份有限公司 | Transceiver and driver architecture with low transmission and high interference tolerance |
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|---|---|---|---|---|
| US5266847A (en) * | 1990-12-28 | 1993-11-30 | National Semiconductor Corporation | High speed data transceiver |
| US5438282A (en) * | 1993-06-08 | 1995-08-01 | National Semiconductor Corporation | CMOS BTL compatible bus and transmission line driver |
| CN1770621A (en) * | 2004-11-05 | 2006-05-10 | 三星电子株式会社 | Differential amplifier circuit capable of reducing current consumption |
| CN201018409Y (en) * | 2007-02-07 | 2008-02-06 | 深圳创维－Rgb电子有限公司 | Overvoltage protection circuit of power factor corrector in power supply circuit |
| CN101840240A (en) * | 2010-03-26 | 2010-09-22 | 东莞电子科技大学电子信息工程研究院 | Adjustable multi-value output reference voltage source |
-
2013
- 2013-11-26 CN CN201310612084.XA patent/CN103647543A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5266847A (en) * | 1990-12-28 | 1993-11-30 | National Semiconductor Corporation | High speed data transceiver |
| US5438282A (en) * | 1993-06-08 | 1995-08-01 | National Semiconductor Corporation | CMOS BTL compatible bus and transmission line driver |
| CN1770621A (en) * | 2004-11-05 | 2006-05-10 | 三星电子株式会社 | Differential amplifier circuit capable of reducing current consumption |
| CN201018409Y (en) * | 2007-02-07 | 2008-02-06 | 深圳创维－Rgb电子有限公司 | Overvoltage protection circuit of power factor corrector in power supply circuit |
| CN101840240A (en) * | 2010-03-26 | 2010-09-22 | 东莞电子科技大学电子信息工程研究院 | Adjustable multi-value output reference voltage source |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106603247A (en) * | 2015-10-15 | 2017-04-26 | 杭州硅星科技有限公司 | Data transceiver, transceiver system and control method of data transceiver |
| CN106603247B (en) * | 2015-10-15 | 2023-02-17 | 杭州硅星科技有限公司 | Data transceiver, transceiver system, and control method of data transceiver |
| CN112491435A (en) * | 2019-08-23 | 2021-03-12 | 微芯片技术股份有限公司 | Transceiver and driver architecture with low transmission and high interference tolerance |
| CN112491435B (en) * | 2019-08-23 | 2022-11-18 | 微芯片技术股份有限公司 | Circuit of physical layer including transceiver and driver architecture |
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Application publication date: 20140319 |