CN113031690A - High-order temperature compensation MOS band gap reference circuit with low temperature drift - Google Patents

High-order temperature compensation MOS band gap reference circuit with low temperature drift Download PDF

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CN113031690A
CN113031690A CN202110269161.0A CN202110269161A CN113031690A CN 113031690 A CN113031690 A CN 113031690A CN 202110269161 A CN202110269161 A CN 202110269161A CN 113031690 A CN113031690 A CN 113031690A
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tube
nmos
pmos
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temperature
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CN113031690B (en
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李世彬
庞统猛
蒲煕
黄志茗
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University of Electronic Science and Technology of China
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

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Abstract

The invention discloses a high-order temperature compensation MOS band-gap reference circuit with low temperature drift, which comprises a first-order MOS band-gap reference circuit, a high-temperature region compensation circuit, a low-temperature region compensation circuit and a starting circuit. The invention adopts the grid electrode-source electrode voltage of the NMOS tube working in the subthreshold region to generate the voltage V with the negative temperature coefficientCTATThe difference between the grid electrode-source electrode voltages of two NMOS tubes working in the subthreshold region generates a positive temperature coefficient voltage VPTATThen weighting to obtain a first-order band gap reference voltage, and compensating the temperature curvature of the high-temperature region with a voltage VNL1、VNL2And a low temperature region temperature segment compensation voltage VNL3、VNL4The low-temperature-drift high-order temperature compensation MOS band-gap reference circuit is introduced into a first-order MOS band-gap reference circuit to obtain band-gap reference voltage with a low temperature coefficient, so that the low-temperature-drift high-order temperature compensation MOS band-gap reference circuit is obtained.

Description

High-order temperature compensation MOS band gap reference circuit with low temperature drift
Technical Field
The invention relates to the technical field of microelectronics, in particular to a high-order temperature compensation MOS band gap reference circuit with low temperature drift.
Background
The bandgap reference circuit is an important module of modern analog integrated circuits and digital-analog hybrid integrated circuits, and its performance characteristics directly affect the performance of the whole circuit, which requires to improve the performance characteristics of the bandgap reference circuit.
Fig. 1 shows a conventional bandgap reference circuit, which is basically configured to obtain a reference voltage with zero temperature characteristic by weighting a difference between an emitter-base voltage VEB1 of a PNP transistor Q1 with negative temperature characteristic and emitter-base voltages of two PNP transistors with positive temperature characteristic. The resistor R1 and the resistor R2 are made of the same material, the PMOS transistor M1, the PMOS transistor M2 and the PMOS transistor M3 have the same channel width-length ratio, and the area of an emitting electrode of the PNP type triode Q2 is n times of the area of emitting electrodes of the PNP type triode Q1 and the PNP type triode Q3. Then, the output voltage V of the conventional bandgap reference circuitREFComprises the following steps:
Figure BDA0002973464630000011
in the formula, VTIs a thermal voltage with positive temperature coefficient, VEB3Is the emitter-base voltage of the PNP transistor Q3, and R1 and R2 are resistance values. The output voltage V can be achieved by adjusting the resistor R1, the resistor R2 and the parameter nREFHas zero temperature characteristic in a certain temperature range. Due to VEB3The nonlinear first-order bandgap reference circuit has the defect of high temperature coefficient of output voltage, so that the application of the conventional first-order bandgap reference circuit in a high-precision system is greatly limited.
Disclosure of Invention
The invention aims to solve the problems in the prior art and designs a high-order temperature compensation MOS band-gap reference circuit with low temperature drift.
The invention is realized by the following technical scheme: a high-order temperature compensation MOS band-gap reference circuit with low temperature drift comprises a first-order MOS band-gap reference circuit, a high-temperature region compensation circuit, a low-temperature region compensation circuit and a starting circuit, wherein a signal output end of the first-order MOS band-gap reference circuit is respectively and electrically connected with a signal input end of the high-temperature region compensation circuit, a signal input end of the low-temperature region compensation circuit and a signal input end of the starting circuit, a signal output end of the starting circuit is electrically connected with a starting signal input end of the first-order MOS band-gap reference circuit, the first-order MOS band-gap reference circuit generates band-gap reference voltage with low temperature coefficient, the high-temperature region compensation circuit and the low-temperature region compensation circuit perform temperature compensation on the band-gap reference voltage generated by the first-order MOS band-gap.
In order to further realize the invention, the following arrangement mode is adopted: the first-order MOS band-gap reference circuit generates a voltage V with a negative temperature coefficient by adopting the grid-source voltage of an NMOS tube working in a subthreshold regionCTATThe difference between the gate-source voltages of two NMOS transistors working in the subthreshold region generates a voltage V with positive temperature coefficientPTATVoltage V ofCTATAnd voltage VPTATAnd weighting to obtain a first-order band gap reference voltage.
In order to further realize the invention, the following arrangement mode is adopted: the first-order MOS band-gap reference circuit comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M5, a PMOS tube M8, a PMOS tube M9, a PMOS tube M10, an NMOS tube M3, an NMOS tube M4, an NMOS tube M6, an NMOS tube M7, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and an error amplifier A1, wherein the source of the PMOS tube M1 is respectively connected with the source of the PMOS tube M2, the source of the PMOS tube M5, the source of the PMOS tube M8, the source of the PMOS tube M9, the source of the PMOS tube M10 and an external power supply VDD, the drain of the PMOS tube M1 is respectively connected with the positive input end of the error amplifier A1 and one end of the resistor R1, the other end of the resistor R1 is respectively connected with the gate of the NMOS tube M4 and the drain of the NMOS tube M3, the PMOS tube M1 is respectively connected with the output end of the error amplifier A1, the PMOS tube M2, the drain of the PMOS tube M2, the drain of the PMOS tube 2, the PMOS tube 2 and the PMOS tube 2, the high-temperature compensation circuit, the drain of the PMOS transistor M5 is connected to the drain of the NMOS transistor M6 and the gate of the NMOS transistor M7, the gate of the PMOS transistor M8 is connected to the drain of the PMOS transistor M8, the gate of the PMOS transistor M9 and the drain of the NMOS transistor M7, the source of the NMOS transistor M7 is connected to the gate of the NMOS transistor M6 and one end of the resistor R2, the other end of the resistor R2 is connected to an external ground GND, the drain of the PMOS transistor M9 is connected to the drain of the PMOS transistor M10 and one end of the resistor R4, a node where the drain of the PMOS transistor M9 and the drain of the PMOS transistor M10 are connected is also used as a bandgap reference output terminal VREF, and the other end of the resistor R4 is connected to the external ground GND through the resistor R3; the node of the grid of the PMOS tube M8 and the grid of the PMOS tube M9 are connected with the high-temperature region compensation circuit and the low-temperature region compensation circuit, and the output end of the error amplifier A1 and the node of the resistor R3 and the resistor R4 are connected with the high-temperature region compensation circuit, the low-temperature region compensation circuit and the starting circuit.
In order to further realize the invention, the following arrangement mode is adopted: the NMOS transistor M3, the NMOS transistor M4 and the NMOS transistor M6 all work in a subthreshold region, and the drain current of the PMOS transistor M10 generates a voltage V on the resistor R3 and the resistor R4PTATAnd is and
Figure BDA0002973464630000021
the drain current of the PMOS transistor M9 generates a voltage V on the resistor R3 and the resistor R4CTATAnd is and
Figure BDA0002973464630000022
in the expressions (1) and (2), q is an electron charge, k is a boltzmann constant, T is an absolute temperature, M is a ratio of a channel width-length ratio of the NMOS transistor M4 to a channel width-length ratio of the NMOS transistor M3, β2Is the ratio of the channel width length ratio of the PMOS transistor M10 to the channel width length ratio of the PMOS transistor M1, beta3Is the ratio of the channel width length ratio of the PMOS transistor M9 to the channel width length ratio of the PMOS transistor M8, VGS6Is the gate-source voltage of NMOS transistor M6, and VGS6Having a negative temperature characteristic, voltage VCTATHas a negative temperature characteristic.
Preferably, the PMOS transistor M1 and the PMOS transistor M2 have the same channel length, the NMOS transistor M6 and the NMOS transistor M7 have the same channel length, the channel width-to-length ratio of the NMOS transistor M4 is M times of that of the NMOS transistor M3, and the channel width-to-length ratio of the PMOS transistor M5 is β of the PMOS transistor M11The channel width length ratio of the PMOS transistor M10 is beta of the PMOS transistor M12The channel width length ratio of the PMOS transistor M9 is beta of the PMOS transistor M83The NMOS transistor M3, the NMOS transistor M4 and the NMOS transistor M6 all work in a subthreshold region, and the drain current of the PMOS transistor M10 generates a voltage V on the resistor R3 and the resistor R4PTATAnd is and
Figure BDA0002973464630000031
in the formula, R1、R3And R4The resistances of the resistor R1, the resistor R3 and the resistor R4, respectively, q is the electronic charge, k is the Boltzmann constant, and T is the absolute temperature; all resistors are made of the same material and have a voltage VPTATHas a positive temperature characteristic.
The PMOS transistor M8 and the PMOS transistor M9 have the same channel width and length, and the drain current I of the PMOS transistor M99The voltage V is generated on the resistor R3 and the resistor R4CTATAnd is and
Figure BDA0002973464630000032
in the formula, R2Is the resistance value of resistor R2, VGS6Is the gate-source voltage of NMOS transistor M6, and VGS6Having a negative temperature characteristic, voltage VCTATHas a negative temperature characteristic.
In order to further realize the invention, the following arrangement mode is adopted: the high-temperature region compensation circuit comprises a PMOS tube M, an NMOS tube M and an NMOS tube M, wherein the grid electrode of the PMOS tube M is connected with the grid electrode of the PMOS tube M and the grid electrode of the PMOS tube M, the source electrode of the PMOS tube M is respectively connected with the source electrode of the PMOS tube M, the source electrode of the PMOS tube M and an external power supply VDD, the drain electrode of the PMOS tube M is respectively connected with the grid electrode of the NMOS tube M, the drain electrode of the NMOS tube M and the grid electrode of the NMOS tube M, the source electrode of the NMOS tube M is respectively connected with the source electrode of the NMOS tube M, the drain electrode of the NMOS tube M and an external GND ground wire, and the drain electrode of the PMOS tube M is respectively connected with the drain electrode of the NMOS tube M, the drain electrode of, the drain of the NMOS transistor M16 is connected to the common node of the resistors R3 and R4 and the drain of the NMOS transistor M22, the drain of the PMOS transistor M17 is connected to the drain of the NMOS transistor M18, the gate of the NMOS transistor M18 and the gate of the NMOS transistor M19, the drain of the PMOS transistor M20 is connected to the drain of the NMOS transistor M19, the drain of the NMOS transistor M21, the gate of the NMOS transistor M21 and the gate of the NMOS transistor M22, the gates of the PMOS transistor M14 and the PMOS transistor M20 are connected to the output terminal of the error amplifier a1, and the drain of the NMOS transistor M22 is connected to the common node of the resistors R3 and R4.
In order to further realize the invention, the following arrangement mode is adopted: the drain current I of the NMOS tube M1616The voltage V generated at the resistor R4NL1Comprises the following steps:
Figure BDA0002973464630000033
drain current I of NMOS transistor M2222The voltage V generated at the resistor R4NL2Comprises the following steps:
Figure BDA0002973464630000034
Figure BDA0002973464630000041
in the formulae (3) and (4), beta4Is the ratio of the channel width length ratio of the PMOS transistor M11 to the channel width length ratio of the PMOS transistor M8, beta5Is the ratio of the channel width length ratio of the PMOS transistor M14 to the channel width length ratio of the PMOS transistor M1, beta6Is the ratio of the channel width-length ratio of the NMOS transistor M16 to the channel width-length ratio of the NMOS transistor M15, beta7Is the ratio of the channel width length ratio of the PMOS transistor M17 to the channel width length ratio of the PMOS transistor M8, beta8Is the ratio of the channel width length ratio of the PMOS transistor M20 to the channel width length ratio of the PMOS transistor M1, beta9Is the ratio of the channel width length ratio of the NMOS tube M22 to the channel width length ratio of the NMOS tube M21, q is the electronic charge, k is the Boltzmann constant, T is the absolute temperature, M is the ratio of the channel width length ratio of the NMOS tube M4 to the channel width length ratio of the NMOS tube M3, VGS6Is the gate-source voltage, T, of the NMOS transistor M6r1Is a reference temperature and is greater than room temperature, Tr2Is a reference temperature and is greater than a reference temperature Tr1。
As a preferable arrangement, the channel width-length ratio of the PMOS transistor M11 in the high-temperature region temperature curvature compensation circuit is beta of the PMOS transistor M84The channel width length ratio of the PMOS transistor M14 is beta of the PMOS transistor M15The channel width length ratio of the NMOS tube M16 is beta of the NMOS tube M156The NMOS transistor M12 and the NMOS transistor M13 have the same channel width and length and PMOThe channel width-length ratio of the S tube M17 is beta of the PMOS tube M87The channel width length ratio of the PMOS transistor M20 is beta of the PMOS transistor M18The channel width length ratio of the NMOS tube M22 is beta of the NMOS tube M219The NMOS transistor M18 and the NMOS transistor M19 have the same channel width and length, and the drain current I of the NMOS transistor M1616The voltage V generated at the resistor R4NL1Comprises the following steps:
Figure BDA0002973464630000042
drain current I of NMOS transistor M2222The voltage V generated at the resistor R4NL2Comprises the following steps:
Figure BDA0002973464630000043
in the formula, Tr1Is a reference temperature and is greater than room temperature, Tr2Is a reference temperature and is greater than a reference temperature Tr1。
In order to further realize the invention, the following arrangement mode is adopted: the low-temperature region compensation circuit comprises a PMOS tube M23, a PMOS tube M26, a PMOS tube M29, a PMOS tube M32, an NMOS tube M24, an NMOS tube M25, an NMOS tube M27, an NMOS tube M28, an NMOS tube M30, an NMOS tube M31, an NMOS tube M33 and an NMOS tube M34, wherein the source of the PMOS tube M23 is respectively connected with the source of the PMOS tube M26, the source of the PMOS tube M29, the source of the PMOS tube M32 and an external power supply VDD, the gate of the PMOS tube M23 is respectively connected with the output end of an error amplifier A1 and the gate of the PMOS tube M29, the drain of the PMOS tube M23 is respectively connected with the gate of the NMOS tube M24, the drain of the NMOS tube M24 and the gate of the NMOS tube M25, the source of the NMOS tube M24 is respectively connected with the source of the NMOS tube M25, the source of the NMOS tube M27, the source of the NMOS tube M28, the source of the NMOS tube M30, the drain of the NMOS tube M30 and the gate of the NMOS tube 30, the drain of the PMOS tube 30 are respectively connected with the drain, The grid electrode of the NMOS tube M27, the drain electrode of the NMOS tube M27 and the grid electrode of the NMOS tube M28 are connected, the drain electrode of the NMOS tube M28 is respectively connected with a common node of the resistor R3 and the resistor R4 and the drain electrode of the NMOS tube M34, the drain electrode of the PMOS tube M29 is respectively connected with the drain electrode of the NMOS tube M30, the grid electrode of the NMOS tube M30 and the grid electrode of the NMOS tube M31, and the drain electrode of the PMOS tube M32 is respectively connected with the drain electrode of the NMOS tube M31, the drain electrode of the NMOS tube M33, the grid electrode of the NMOS tube M33 and the grid electrode of the NMOS tube M34.
In order to further realize the invention, the following arrangement mode is adopted: the drain current I of the NMOS tube M2828The voltage V generated at the resistor R4NL3Comprises the following steps:
Figure BDA0002973464630000051
the drain current I of the NMOS tube M3434The voltage V generated at the resistor R4NL4Is composed of
Figure BDA0002973464630000052
Figure BDA0002973464630000053
In the formulae (5) and (6), beta10Is the ratio of the channel width length ratio of the PMOS transistor M23 to the channel width length ratio of the PMOS transistor M1, beta11Is the ratio of the channel width length ratio of the PMOS transistor M26 to the channel width length ratio of the PMOS transistor M8, beta12Is the ratio of the channel width-length ratio of the NMOS transistor M28 to the channel width-length ratio of the NMOS transistor M27, beta13Is the ratio of the channel width length ratio of the PMOS transistor M29 to the channel width length ratio of the PMOS transistor M1, beta14Is multiplied by the ratio of the channel width-length ratio of the PMOS transistor M32 to the channel width-length ratio of the PMOS transistor M8, beta15Is the ratio of the channel width length ratio of the NMOS tube M34 to the channel width length ratio of the NMOS tube M33, q is the electronic charge, k is the Boltzmann constant, T is the absolute temperature, M is the ratio of the channel width length ratio of the NMOS tube M4 to the channel width length ratio of the NMOS tube M3, VGS6Is the gate-source voltage, T, of the NMOS transistor M6r3Is a reference temperature and is less than room temperature, Tr4Is a reference temperature and is less than a reference temperature Tr3；
Preferably, the channel width-to-length ratio of the PMOS transistor M23 is β of the PMOS transistor M110The channel width length ratio of the PMOS transistor M26 is beta of the PMOS transistor M811The channel width length ratio of the NMOS tube M28 is beta of the NMOS tube M2712The NMOS transistor M24 and the NMOS transistor M25 have the same channel width and length, and the channel width and length ratio of the PMOS transistor M29 is beta of the PMOS transistor M113The channel width length ratio of the PMOS transistor M32 is beta of the PMOS transistor M814The channel width length ratio of the NMOS tube M34 is beta of the NMOS tube M3315The NMOS transistor M30 and the NMOS transistor M31 have the same channel width and length, so that the drain current I of the NMOS transistor M2828The voltage V generated at the resistor R4NL3Comprises the following steps:
Figure BDA0002973464630000054
drain current I of NMOS transistor M3434The voltage V generated at the resistor R4NL4Comprises the following steps:
Figure BDA0002973464630000055
in the formula, Tr3Is a reference temperature and is less than room temperature, Tr4Is a reference temperature and is less than a reference temperature Tr3。
In order to further realize the invention, the following arrangement mode is adopted: the starting circuit comprises a PMOS tube Ms1, a PMOS tube Ms2, an NMOS tube Ms3 and an NMOS tube Ms4, wherein the source electrode of the PMOS tube Ms1 is connected with an external power supply VDD, the grid electrode of the PMOS tube Ms1 is connected with the drain electrode of the PMOS tube Ms1 and the source electrode of the PMOS tube Ms2 respectively, the grid electrode of the PMOS tube Ms2 is connected with the drain electrode of the PMOS tube Ms2, the grid electrode of the NMOS tube Ms3 and the drain electrode of the NMOS tube Ms4 respectively, the source electrode of the NMOS tube Ms3 is connected with the source electrode of the NMOS tube Ms4 and an external ground wire GND respectively, the drain electrode of the NMOS tube Ms3 is connected with the output end of the error amplifier A1, and the grid electrode of the NMOS tube Ms4 is connected with the common node of the resistor R63.
In order to further realize the invention, the following arrangement mode is adopted: the output voltage of the high-order temperature compensation MOS band-gap reference circuit with low temperature drift is VREFAnd V isREF＝VPTAT+VCTAT-VNL1-VNL2-VNL3-VNL4Wherein V isPTATTo have a positive temperature coefficient of voltage, VCTATTo have a negative temperature coefficient voltage, VNL1And VNL2Voltage having temperature curvature characteristic for high temperature region, VNL3And VNL4The low temperature region has a temperature-segmented characteristic voltage.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the invention adopts the grid electrode-source electrode voltage of the NMOS tube working in the subthreshold region to generate the voltage V with the negative temperature coefficientCTATThe difference between the grid electrode-source electrode voltages of two NMOS tubes working in the subthreshold region generates a positive temperature coefficient voltage VPTATThe two are weighted to obtain a first-order band gap reference voltage, and the drain current of an NMOS tube M16 in a high-temperature region temperature curvature compensation circuit (high-temperature region compensation circuit) generates a voltage V on a resistor R4NL1The voltage V generated on the resistor R4 together with the drain current of the NMOS transistor M22NL2The band gap reference voltage is compensated in the high temperature region, and the voltage V generated on the resistor R4 by the drain current of the NMOS transistor M28 in the low temperature region temperature subsection compensation circuit (low temperature region compensation circuit)NL3The voltage V generated on the resistor R4 together with the drain current of the NMOS transistor M34NL4And compensating the band gap reference voltage in a low-temperature region so as to obtain a band gap reference voltage with high-order temperature compensation.
The first-order band gap reference of the invention utilizes the grid electrode-source electrode voltage of an NMOS tube working in a subthreshold region to generate the voltage V with a negative temperature coefficientCTATThe difference between the grid electrode-source electrode voltages of two NMOS tubes working in the subthreshold region generates a positive temperature coefficient voltage VPTATWeighting the two to obtain a first-order band-gap reference voltage, and utilizing a voltage V which increases in a curve along with the increase of the temperature TNL1And VNL2And a voltage V that decreases in a curve with increasing temperature TNL3And VNL4The high-order compensation is carried out on the band gap reference voltage, so that the temperature coefficient of the reference voltage is effectively reduced.
Drawings
Fig. 1 is a conventional bandgap reference circuit structure.
Fig. 2 is a circuit configuration diagram (first order MOS bandgap reference circuit portion) of the present invention.
Fig. 3 is a circuit configuration diagram (high temperature region compensation circuit portion) of the present invention.
Fig. 4 is a circuit configuration diagram (low temperature region compensation circuit and start-up circuit portion) of the present invention.
Fig. 5 is a first order bandgap reference voltage curve.
Fig. 6 is a schematic diagram of an output voltage curve of a MOS transistor implementing a high-order temperature compensation bandgap reference circuit according to the present invention.
Fig. 7 is a simulation of the output voltage temperature characteristic of the MOS transistor implementing the high-order temperature compensation bandgap reference circuit of the present invention.
Wherein A, B, C in fig. 2, 3 and 4 is the node where the individual circuits are connected to each other.
Detailed Description
The present invention will be described in further detail with reference to examples, but the embodiments of the present invention are not limited thereto.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention.
In the description of the present invention, it is to be understood that the terms etc. indicate orientations or positional relationships based on those shown in the drawings only for the convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
It is worth noting that: in the present application, when it is necessary to apply the known technology or the conventional technology in the field, the applicant may have the case that the known technology or/and the conventional technology is not specifically described in the text, but the technical means is not specifically disclosed in the text, and the present application is considered to be not in compliance with the twenty-sixth clause of the patent law.
Example 1:
a high-order temperature compensation MOS band-gap reference circuit with low temperature drift, as shown in FIGS. 2-4, adopts the following arrangement: the high-temperature compensation circuit and the low-temperature compensation circuit perform temperature compensation on the band gap reference voltage generated by the first-order MOS band gap reference circuit, and the starting circuit provides a starting signal for the first-order MOS band gap reference circuit.
Example 2:
the present embodiment is further optimized based on the above embodiment, and the same parts as those in the foregoing technical solution will not be described herein again, as shown in fig. 2 to fig. 4, in order to further better implement the present invention, the following setting manner is particularly adopted: the first-order MOS band-gap reference circuit generates a voltage V with a negative temperature coefficient by adopting the grid-source voltage of an NMOS tube working in a subthreshold regionCTATThe difference between the gate-source voltages of two NMOS transistors working in the subthreshold region generates a voltage V with positive temperature coefficientPTATVoltage V ofCTATAnd voltage VPTATAnd weighting to obtain a first-order band gap reference voltage.
Example 3:
the present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the foregoing technical solutions will not be described herein again, as shown in fig. 2 to fig. 4, in order to further better implement the present invention, the following setting modes are particularly adopted: the first-order MOS band-gap reference circuit comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M5, a PMOS tube M8, a PMOS tube M9, a PMOS tube M10, an NMOS tube M3, an NMOS tube M4, an NMOS tube M6, an NMOS tube M7, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and an error amplifier A1, wherein the source of the PMOS tube M1 is respectively connected with the source of the PMOS tube M2, the source of the PMOS tube M5, the source of the PMOS tube M8, the source of the PMOS tube M9, the source of the PMOS tube M10 and an external power supply VDD, the drain of the PMOS tube M1 is respectively connected with the positive input end of the error amplifier A1 and one end of the resistor R1, the other end of the resistor R1 is respectively connected with the gate of the NMOS tube M4 and the drain of the NMOS tube M3, the PMOS tube M1 is respectively connected with the output end of the error amplifier A1, the PMOS tube M2, the drain of the PMOS tube M2, the drain of the PMOS tube 2, the PMOS tube 2 and the PMOS tube 2, the high-temperature compensation circuit, the drain of the PMOS transistor M5 is connected to the drain of the NMOS transistor M6 and the gate of the NMOS transistor M7, the gate of the PMOS transistor M8 is connected to the drain of the PMOS transistor M8, the gate of the PMOS transistor M9 and the drain of the NMOS transistor M7, the source of the NMOS transistor M7 is connected to the gate of the NMOS transistor M6 and one end of the resistor R2, the other end of the resistor R2 is connected to an external ground GND, the drain of the PMOS transistor M9 is connected to the drain of the PMOS transistor M10 and one end of the resistor R4, a node where the drain of the PMOS transistor M9 and the drain of the PMOS transistor M10 are connected is also used as a bandgap reference output terminal VREF, and the other end of the resistor R4 is connected to the external ground GND through the resistor R3; the node of the grid of the PMOS tube M8 and the grid of the PMOS tube M9 are connected with the high-temperature region compensation circuit and the low-temperature region compensation circuit, and the output end of the error amplifier A1 and the node of the resistor R3 and the resistor R4 are connected with the high-temperature region compensation circuit, the low-temperature region compensation circuit and the starting circuit.
Example 4:
the present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the foregoing technical solutions will not be described herein again, as shown in fig. 2 to fig. 4, in order to further better implement the present invention, the following setting modes are particularly adopted: the NMOS transistor M3, the NMOS transistor M4 and the NMOS transistor M6 all work in a subthreshold region, and the drain current of the PMOS transistor M10 generates a voltage V on the resistor R3 and the resistor R4PTATAnd is and
Figure BDA0002973464630000091
the drain current of the PMOS transistor M9 generates a voltage V on the resistor R3 and the resistor R4CTATAnd is and
Figure BDA0002973464630000092
in the expressions (1) and (2), q is an electron charge, k is a boltzmann constant, T is an absolute temperature, M is a ratio of a channel width-length ratio of the NMOS transistor M4 to a channel width-length ratio of the NMOS transistor M3, β2Is the ratio of the channel width length ratio of the PMOS transistor M10 to the channel width length ratio of the PMOS transistor M1, beta3Is the ratio of the channel width length ratio of the PMOS transistor M9 to the channel width length ratio of the PMOS transistor M8, VGS6Is the grid-source electrode of the NMOS transistor M6Pressure and VGS6Having a negative temperature characteristic, voltage VCTATHas a negative temperature characteristic.
Example 5:
the present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the foregoing technical solutions will not be described herein again, as shown in fig. 2 to fig. 4, in order to further better implement the present invention, the following setting modes are particularly adopted: the high-temperature region compensation circuit comprises a PMOS tube M, an NMOS tube M and an NMOS tube M, wherein the grid electrode of the PMOS tube M is connected with the grid electrode of the PMOS tube M and the grid electrode of the PMOS tube M, the source electrode of the PMOS tube M is respectively connected with the source electrode of the PMOS tube M, the source electrode of the PMOS tube M and an external power supply VDD, the drain electrode of the PMOS tube M is respectively connected with the grid electrode of the NMOS tube M, the drain electrode of the NMOS tube M and the grid electrode of the NMOS tube M, the source electrode of the NMOS tube M is respectively connected with the source electrode of the NMOS tube M, the drain electrode of the NMOS tube M and an external GND ground wire, and the drain electrode of the PMOS tube M is respectively connected with the drain electrode of the NMOS tube M, the drain electrode of, the drain of the NMOS transistor M16 is connected to the common node of the resistors R3 and R4 and the drain of the NMOS transistor M22, the drain of the PMOS transistor M17 is connected to the drain of the NMOS transistor M18, the gate of the NMOS transistor M18 and the gate of the NMOS transistor M19, the drain of the PMOS transistor M20 is connected to the drain of the NMOS transistor M19, the drain of the NMOS transistor M21, the gate of the NMOS transistor M21 and the gate of the NMOS transistor M22, the gates of the PMOS transistor M14 and the PMOS transistor M20 are connected to the output terminal of the error amplifier a1, and the drain of the NMOS transistor M22 is connected to the common node of the resistors R3 and R4.
Example 6:
the present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the foregoing technical solutions will not be described herein again, as shown in fig. 2 to fig. 4, in order to further better implement the present invention, the following setting modes are particularly adopted: the drain current I of the NMOS tube M1616At the resistor R4Generated voltage VNL1Comprises the following steps:
Figure BDA0002973464630000101
Figure BDA0002973464630000102
drain current I of NMOS transistor M2222The voltage V generated at the resistor R4NL2Comprises the following steps:
Figure BDA0002973464630000103
in the formulae (3) and (4), beta4Is the ratio of the channel width length ratio of the PMOS transistor M11 to the channel width length ratio of the PMOS transistor M8, beta5Is the ratio of the channel width length ratio of the PMOS transistor M14 to the channel width length ratio of the PMOS transistor M1, beta6Is the ratio of the channel width-length ratio of the NMOS transistor M16 to the channel width-length ratio of the NMOS transistor M15, beta7Is the ratio of the channel width length ratio of the PMOS transistor M17 to the channel width length ratio of the PMOS transistor M8, beta8Is the ratio of the channel width length ratio of the PMOS transistor M20 to the channel width length ratio of the PMOS transistor M1, beta9Is the ratio of the channel width length ratio of the NMOS tube M22 to the channel width length ratio of the NMOS tube M21, q is the electronic charge, k is the Boltzmann constant, T is the absolute temperature, M is the ratio of the channel width length ratio of the NMOS tube M4 to the channel width length ratio of the NMOS tube M3, VGS6Is the gate-source voltage, T, of the NMOS transistor M6r1Is a reference temperature and is greater than room temperature, Tr2Is a reference temperature and is greater than a reference temperature Tr1。
Example 7:
the present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the foregoing technical solutions will not be described herein again, as shown in fig. 2 to fig. 4, in order to further better implement the present invention, the following setting modes are particularly adopted: the low-temperature region compensation circuit comprises a PMOS tube M23, a PMOS tube M26, a PMOS tube M29, a PMOS tube M32, an NMOS tube M24, an NMOS tube M25, an NMOS tube M27, an NMOS tube M28, an NMOS tube M30, an NMOS tube M31, an NMOS tube M33 and an NMOS tube M34, wherein the source of the PMOS tube M23 is respectively connected with the source of the PMOS tube M26, the source of the PMOS tube M29, the source of the PMOS tube M32 and an external power supply VDD, the gate of the PMOS tube M23 is respectively connected with the output end of an error amplifier A1 and the gate of the PMOS tube M29, the drain of the PMOS tube M23 is respectively connected with the gate of the NMOS tube M24, the drain of the NMOS tube M24 and the gate of the NMOS tube M25, the source of the NMOS tube M24 is respectively connected with the source of the NMOS tube M25, the source of the NMOS tube M27, the source of the NMOS tube M28, the source of the NMOS tube M30, the drain of the NMOS tube M30 and the gate of the NMOS tube 30, the drain of the PMOS tube 30 are respectively connected with the drain, The grid electrode of the NMOS tube M27, the drain electrode of the NMOS tube M27 and the grid electrode of the NMOS tube M28 are connected, the drain electrode of the NMOS tube M28 is respectively connected with a common node of the resistor R3 and the resistor R4 and the drain electrode of the NMOS tube M34, the drain electrode of the PMOS tube M29 is respectively connected with the drain electrode of the NMOS tube M30, the grid electrode of the NMOS tube M30 and the grid electrode of the NMOS tube M31, and the drain electrode of the PMOS tube M32 is respectively connected with the drain electrode of the NMOS tube M31, the drain electrode of the NMOS tube M33, the grid electrode of the NMOS tube M33 and the grid electrode of the NMOS tube M34.
Example 8:
the present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the foregoing technical solutions will not be described herein again, as shown in fig. 2 to fig. 4, in order to further better implement the present invention, the following setting modes are particularly adopted: the drain current I of the NMOS tube M2828The voltage V generated at the resistor R4NL3Comprises the following steps:
Figure BDA0002973464630000111
Figure BDA0002973464630000112
the drain current I of the NMOS tube M3434The voltage V generated at the resistor R4NL4Is composed of
Figure BDA0002973464630000113
In the formulae (5) and (6), beta10Is the ratio of the channel width length ratio of the PMOS transistor M23 to the channel width length ratio of the PMOS transistor M1, beta11Is the ratio of the channel width length ratio of the PMOS transistor M26 to the channel width length ratio of the PMOS transistor M8, beta12The channel width-length ratio of the NMOS transistor M28 to that of the NMOS transistor M27Ratio, beta13Is the ratio of the channel width length ratio of the PMOS transistor M29 to the channel width length ratio of the PMOS transistor M1, beta14Is multiplied by the ratio of the channel width-length ratio of the PMOS transistor M32 to the channel width-length ratio of the PMOS transistor M8, beta15Is the ratio of the channel width length ratio of the NMOS tube M34 to the channel width length ratio of the NMOS tube M33, q is the electronic charge, k is the Boltzmann constant, T is the absolute temperature, M is the ratio of the channel width length ratio of the NMOS tube M4 to the channel width length ratio of the NMOS tube M3, VGS6Is the gate-source voltage, T, of the NMOS transistor M6r3Is a reference temperature and is less than room temperature, Tr4Is a reference temperature and is less than a reference temperature Tr3；
Example 9:
the present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the foregoing technical solutions will not be described herein again, as shown in fig. 2 to fig. 4, in order to further better implement the present invention, the following setting modes are particularly adopted: the starting circuit comprises a PMOS tube Ms1, a PMOS tube Ms2, an NMOS tube Ms3 and an NMOS tube Ms4, wherein the source electrode of the PMOS tube Ms1 is connected with an external power supply VDD, the grid electrode of the PMOS tube Ms1 is connected with the drain electrode of the PMOS tube Ms1 and the source electrode of the PMOS tube Ms2 respectively, the grid electrode of the PMOS tube Ms2 is connected with the drain electrode of the PMOS tube Ms2, the grid electrode of the NMOS tube Ms3 and the drain electrode of the NMOS tube Ms4 respectively, the source electrode of the NMOS tube Ms3 is connected with the source electrode of the NMOS tube Ms4 and an external ground wire GND respectively, the drain electrode of the NMOS tube Ms3 is connected with the output end of the error amplifier A1, and the grid electrode of the NMOS tube Ms4 is connected with the common node of the resistor R63.
Example 10:
the present embodiment is further optimized based on any of the above embodiments, and the same parts as those in the foregoing technical solutions will not be described herein again, as shown in fig. 2 to fig. 4, in order to further better implement the present invention, the following setting modes are particularly adopted: the output voltage of the high-order temperature compensation MOS band-gap reference circuit with low temperature drift is VREFAnd V isREF＝VPTAT+VCTAT-VNL1-VNL2-VNL3-VNL4Wherein V isPTATTo have a positive temperature coefficient of voltage, VCTATTo have a negative temperature coefficient voltage, VNL1And VNL2Voltage having temperature curvature characteristic for high temperature region, VNL3And VNL4The low temperature region has a temperature-segmented characteristic voltage.
Example 11:
a high-order temperature compensation MOS band-gap reference circuit with low temperature drift is shown in figures 2-4 and comprises a first-order MOS band-gap reference circuit, a high-temperature region compensation circuit (high-temperature region temperature curvature compensation circuit), a low-temperature region compensation circuit (low-temperature region temperature subsection compensation circuit) and a starting circuit;
the signal output end of the first-order MOS band-gap reference circuit is electrically connected with the signal input end of the high-temperature region temperature curvature compensation circuit, the signal input end of the low-temperature region temperature segmentation compensation circuit and the signal input end of the starting circuit respectively, and the signal output end of the starting circuit is electrically connected with the starting signal input end of the first-order MOS band-gap reference circuit; the starting circuit enables the first-order MOS band-gap reference circuit to normally work and generate band-gap reference voltage output, and the first-order MOS band-gap reference circuit generates positive temperature coefficient voltage VPTATAnd a voltage V of negative temperature coefficientCTATWhile applying a voltage VPTATAnd voltage VCTATWeighting to generate band-gap reference voltage (namely output voltage of the whole circuit) V with low temperature coefficientREFThe drain current of the NMOS transistor M16 in the high temperature region temperature curvature compensation circuit generates a voltage V on a resistor R4NL1The voltage V generated on the resistor R4 together with the drain current of the NMOS transistor M22NL2The band gap reference voltage is compensated in the high temperature region, and the voltage V generated by the drain current of the NMOS transistor M28 on the resistor R4 in the low temperature region temperature segmented compensation circuitNL3The voltage V generated on the resistor R4 together with the drain current of the NMOS transistor M34NL4Compensating the band gap reference voltage in a low-temperature region to obtain a band gap reference voltage V after high-order temperature compensationREF。
The starting circuit only plays a role when the first-order MOS band-gap reference circuit is powered on, and the starting circuit stops working after the band-gap reference circuit is started, so that the influence of the starting circuit on a circuit behind the circuit is avoided.
As a preferred technical solution, as shown in fig. 2 to 4, the first-order bandgap reference circuit includes: a PMOS tube M1, a PMOS tube M2, a PMOS tube M5, a PMOS tube M8, a PMOS tube M9, a PMOS tube M10, an NMOS tube M3, an NMOS tube M4, an NMOS tube M6, an NMOS tube M7, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and an error amplifier A1;
the high temperature region temperature curvature compensation circuit includes: a PMOS tube M11, a PMOS tube M14, a PMOS tube M17, a PMOS tube M20, an NMOS tube M12, an NMOS tube M13, an NMOS tube M15, an NMOS tube M16, an NMOS tube M18, an NMOS tube M19, an NMOS tube M21 and an NMOS tube M22;
the low temperature region temperature segment compensation circuit includes: a PMOS tube M23, a PMOS tube M26, a PMOS tube M29, a PMOS tube M32, an NMOS tube M24, an NMOS tube M25, an NMOS tube M27, an NMOS tube M28, an NMOS tube M30, an NMOS tube M31, an NMOS tube M33 and an NMOS tube M34;
the start-up circuit 4 includes: PMOS tube Ms1, PMOS tube Ms2, NMOS tube Ms3 and NMOS tube Ms 4.
The source of the PMOS transistor M1 is connected to the source of the PMOS transistor M2, the source of the PMOS transistor M5, the source of the PMOS transistor M8, the source of the PMOS transistor M9, the source of the PMOS transistor M10, the source of the PMOS transistor M11, the source of the PMOS transistor M14, the source of the PMOS transistor M17, the source of the PMOS transistor M20, the source of the PMOS transistor M23, the source of the PMOS transistor M26, the source of the PMOS transistor M29, the source of the PMOS transistor M32, the source of the PMOS transistor Ms1, and the external power supply VDD.
The drain electrode of the PMOS tube M1 is respectively connected with the positive input end of the error amplifier A1 and one end of a resistor R1, and the other end of the resistor R1 is respectively connected with the grid electrode of the NMOS tube M4 and the drain electrode of the NMOS tube M3;
the grid electrode of the PMOS tube M1 is respectively connected with the output end of the error amplifier A1, the grid electrode of the PMOS tube M2, the grid electrode of the PMOS tube M5, the grid electrode of the PMOS tube M10, the grid electrode of the PMOS tube M14, the grid electrode of the PMOS tube M20, the grid electrode of the PMOS tube M23, the grid electrode of the PMOS tube M29 and the drain electrode of the NMOS tube Ms 3;
the drain electrode of the PMOS tube M2 is respectively connected with the inverted input end of the error amplifier A1 and the drain electrode of the NMOS tube M4, and the drain electrode of the PMOS tube M5 is respectively connected with the drain electrode of the NMOS tube M6 and the grid electrode of the PMOS tube M7;
the grid electrode of the PMOS tube M8 is respectively connected with the drain electrode of the PMOS tube M8, the grid electrode of the PMOS tube M9, the grid electrode of the PMOS tube M11, the grid electrode of the PMOS tube M17, the grid electrode of the PMOS tube M26 and the grid electrode of the PMOS tube M32, and the source electrode of the PMOS tube M7 is respectively connected with the grid electrode of the PMOS tube M6 and one end of a resistor R2;
the drain electrode of the PMOS tube M9 is respectively connected with the drain electrode of the PMOS tube M10 and one end of the resistor R4, and the node at which the drain electrode of the PMOS tube M9 is connected with the drain electrode of the PMOS tube M10 is also used as a band gap reference output end VREF;
the other end of the resistor R4 is connected to the drain of the NMOS transistor M16, the drain of the NMOS transistor M22, the drain of the NMOS transistor M28, the drain of the NMOS transistor M34, the gate of the NMOS transistor Ms4, and one end of the resistor R3, the other end of the resistor R3 is connected to the source of the NMOS transistor M3, the source of the NMOS transistor M4, the source of the NMOS transistor M6, the other end of the resistor R2, the source of the NMOS transistor M12, the source of.
The drain of the PMOS transistor M11 is connected to the gate of the NMOS transistor M12, the drain of the NMOS transistor M12 and the gate of the NMOS transistor M13, the drain of the PMOS transistor M14 is connected to the drain of the NMOS transistor M13, the gate of the NMOS transistor M15, the drain of the NMOS transistor M15 and the gate of the NMOS transistor M16, the drain of the NMOS transistor M16 is connected to the common node of the resistor R3 and the resistor R4, the drain of the NMOS transistor M22, the drain of the NMOS transistor M28, the drain of the NMOS transistor M34 and the gate of the NMOS transistor Ms4, the drain of the PMOS transistor M17 is connected to the drain of the NMOS transistor M18, the gate of the NMOS transistor M18 and the gate of the NMOS transistor M19, and the drain of the PMOS transistor M20 is connected to the drain of the NMOS transistor M19, the drain of the NMOS transistor M21, the drain of the NMOS transistor M21 and the gate of the NMOS transistor M22.
The drain of the PMOS transistor M23 is connected to the gate of the NMOS transistor M24, the drain of the NMOS transistor M24, and the gate of the NMOS transistor M25, the drain of the PMOS transistor M26 is connected to the drain of the NMOS transistor M25, the gate of the NMOS transistor M27, the drain of the NMOS transistor M27, and the gate of the NMOS transistor M28, the drain of the PMOS transistor M29 is connected to the drain of the NMOS transistor M30, the gate of the NMOS transistor M30, and the gate of the NMOS transistor M31, and the drain of the PMOS transistor M32 is connected to the drain of the NMOS transistor M31, the drain of the NMOS transistor M33, the gate of the NMOS transistor M33, and the gate of the NMOS transistor M34.
The grid electrode of the PMOS tube Ms1 is respectively connected with the drain electrode of the PMOS tube Ms1 and the source electrode of the PMOS tube Ms2, and the grid electrode of the PMOS tube Ms2 is respectively connected with the drain electrode of the PMOS tube Ms2, the grid electrode of the NMOS tube Ms3 and the drain electrode of the NMOS tube Ms 4.
In the first-order MOS band-gap reference circuit, the grid-source voltage V of the NMOS transistor M4 working in the subthreshold regionGS4The emitter-base voltage has similar performance characteristics when the base electrode and the collector electrode of the PNP type triode are in short circuit, namely the grid electrode-source electrode voltage V of the NMOS transistor M4GS4Has a negative temperature characteristic; similarly, the gate-source voltage V of the NMOS transistor M3GS3The emitter-base voltage has similar performance characteristics when the base electrode and the collector electrode of the PNP type triode are in short circuit, namely the grid electrode-source electrode voltage V of the NMOS transistor M3GS3Has a negative temperature characteristic.
The PMOS transistor M1 and the PMOS transistor M2 have the same channel length, the NMOS transistor M6 and the NMOS transistor M7 have the same channel length, the channel width-length ratio of the NMOS transistor M4 is M times of that of the NMOS transistor M3, and then the drain current I of the PMOS transistor M1 is1Comprises the following steps:
Figure BDA0002973464630000141
where R1 is the resistance of resistor R1, q is the electronic charge, k is the Boltzmann constant, and T is the absolute temperature. The channel width-to-length ratio of the PMOS transistor M10 is beta of the PMOS transistor M12Multiplied by the drain current I of the PMOS transistor M1010The voltage V is generated on the resistor R3 and the resistor R4PTATComprises the following steps:
Figure BDA0002973464630000142
in the formula, R3And R4The resistance values of the resistor R3 and the resistor R4 are respectively, and all the resistors are made of the same material, so that V isPTATHas a positive temperature characteristic.Drain current I of PMOS transistor M88Comprises the following steps:
Figure BDA0002973464630000151
in the formula, R2Is the resistance of resistor R2. PMOS transistor M8 and PMOS transistor M9 constitute a pair of current mirrors, and the channel width-length ratio of PMOS transistor M9 is beta of PMOS transistor M83Multiplied by the drain current I of the PMOS transistor M99The voltage V is generated on the resistor R3 and the resistor R4CTATComprises the following steps:
Figure BDA0002973464630000152
thus, VCTATHas a negative temperature characteristic.
The invention is compensation VGS6And the high-temperature area is nonlinear, and a high-temperature area temperature curvature compensation circuit is adopted. The channel width-to-length ratio of the PMOS transistor M11 is beta of the PMOS transistor M84The channel width length ratio of the PMOS transistor M14 is beta of the PMOS transistor M15The channel width length ratio of the NMOS tube M16 is beta of the NMOS tube M156The NMOS transistor M12 and the NMOS transistor M13 have the same channel width and length, and the channel width and length ratio of the PMOS transistor M17 is beta of the PMOS transistor M87The channel width length ratio of the PMOS transistor M20 is beta of the PMOS transistor M18The channel width length ratio of the NMOS tube M22 is beta of the NMOS tube M219The NMOS transistor M18 and the NMOS transistor M19 have the same channel width and length, and the drain current I of the NMOS transistor M1616The voltage V generated at the resistor R4NL1Comprises the following steps:
Figure BDA0002973464630000153
drain current I of NMOS transistor M2222The voltage V generated at the resistor R4NL2Comprises the following steps:
Figure BDA0002973464630000154
in the formula, Tr1Is a reference temperature and is greater than room temperature, Tr2Is a reference temperature and is greater than a reference temperature Tr1。
The invention is compensation VGS6And the low-temperature region is nonlinear, and a low-temperature region temperature curvature compensation circuit is adopted. The channel width-to-length ratio of the PMOS transistor M23 is beta of the PMOS transistor M110The channel width length ratio of the PMOS transistor M26 is beta of the PMOS transistor M811The channel width length ratio of the NMOS tube M28 is beta of the NMOS tube M2712The NMOS transistor M24 and the NMOS transistor M25 have the same channel width and length, and the channel width and length ratio of the MOS transistor M29 is beta of the PMOS transistor M113The channel width length ratio of the PMOS transistor M32 is beta of the PMOS transistor M814The channel width length ratio of the NMOS tube M34 is beta of the NMOS tube M3315The NMOS transistor M30 and the NMOS transistor M31 have the same channel width and length, so that the drain current I of the NMOS transistor M2828The voltage V generated at the resistor R4NL3Comprises the following steps:
Figure BDA0002973464630000155
drain current I of NMOS transistor M3434The voltage V generated at the resistor R4NL4Comprises the following steps:
Figure BDA0002973464630000161
in the formula, Tr3Is a reference temperature and is less than room temperature, Tr4Is a reference temperature and is less than a reference temperature Tr3。
From the formula (one) to the formula (eight), the MOS transistor realizes the output voltage V of the output end VREF of the high-order temperature compensation bandgap reference circuitREFComprises the following steps:
VREF＝VPTAT+VCTAT-VNL1-VNL2-VNL3-VNL4(nine)
According to the formula (nine), the MOS tube realizes the output voltage V of the high-order temperature compensation band-gap reference circuitREFComprising VPTAT、VCTAT、VNL1、VNL2、VNL3And VNL4Six factors, wherein VPTATAnd VCTATWeighted to form a first order bandgap reference voltage, VNL1And VNL2Will compensate VGS6High order temperature nonlinearity, VNL3And VNL4Will compensate VGS6High order temperature non-linearity, as shown in fig. 6.
FIG. 7 shows the output voltage V of the MOS transistor band-gap reference circuit with high-order temperature compensationREFThe abscissa is temperature, and the ordinate is output voltage of the bandgap reference. Simulation results show that the MOS tube realizes the output voltage V of the high-order temperature compensation MOS band-gap reference circuit in the temperature range of-40 ℃ to 125 DEG CREFThe temperature coefficient of (a) was 3.1 ppm/DEG C.
In the above embodiment of the present invention, the MOS transistor is provided to implement the high-order temperature compensation bandgap reference circuit, which includes a first-order MOS bandgap reference circuit, a high-temperature region temperature curvature compensation circuit, a low-temperature region temperature segmented compensation circuit, and a start circuit. The first-order MOS band-gap reference circuit of the invention adopts the grid electrode-source electrode voltage of an NMOS tube working in a subthreshold region to generate a voltage V with a negative temperature coefficientCTATThe difference between the gate-source voltages of two NMOS transistors working in the subthreshold region generates a voltage V with positive temperature coefficientPTATVoltage V ofCTATAnd voltage VPTATWeighting the two to obtain a first-order band gap reference voltage, and carrying out drain current I of an NMOS transistor M16 in the high-temperature region temperature curvature compensation circuit16The voltage V generated at the resistor R4NL1And drain current I of NMOS transistor M2222The voltage V generated at the resistor R4NL2And drain current I of NMOS transistor M28 in the low-temperature region temperature segmented compensation circuit28The voltage V generated at the resistor R4NL3And drain current I of NMOS transistor M3434The voltage V generated at the resistor R4NL4Introducing into a first-order band-gap reference voltage to obtain a band-gap reference voltage V after high-order temperature compensationREF。
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications and equivalent variations of the above embodiments according to the technical spirit of the present invention are within the scope of the present invention.

Claims (9)

1. A high-order temperature compensation MOS band-gap reference circuit with low temperature drift is characterized in that: the high-temperature compensation circuit and the low-temperature compensation circuit perform temperature compensation on the band gap reference voltage generated by the first-order MOS band gap reference circuit, and the starting circuit provides a starting signal for the first-order MOS band gap reference circuit.
2. The low-temperature-drift high-order temperature-compensation MOS bandgap reference circuit according to claim 1, wherein: the first-order MOS band-gap reference circuit generates a voltage V with a negative temperature coefficient by adopting the grid-source voltage of an NMOS tube working in a subthreshold regionCTATThe difference between the gate-source voltages of two NMOS transistors working in the subthreshold region generates a voltage V with positive temperature coefficientPTATVoltage V ofCTATAnd voltage VPTATAnd weighting to obtain a first-order band gap reference voltage.
3. A low-temperature-drift high-order temperature-compensated MOS bandgap reference circuit as claimed in claim 1 or 2, wherein: the first-order MOS band-gap reference circuit comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M5, a PMOS tube M8, a PMOS tube M9, a PMOS tube M10, an NMOS tube M3, an NMOS tube M4, an NMOS tube M6, an NMOS tube M7, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and an error amplifier A1, wherein the source of the PMOS tube M1 is respectively connected with the source of the PMOS tube M2, the source of the PMOS tube M5, the source of the PMOS tube M8, the source of the PMOS tube M9, the source of the PMOS tube M10 and an external power supply VDD, the drain of the PMOS tube M1 is respectively connected with the positive input end of the error amplifier A1 and one end of the resistor R1, the other end of the resistor R1 is respectively connected with the gate of the NMOS tube M4 and the drain of the NMOS tube M3, the PMOS tube M1 is respectively connected with the output end of the error amplifier A1, the PMOS tube M2, the drain of the PMOS tube M2, the drain of the PMOS tube 2, the PMOS tube 2 and the PMOS tube 2, the high-temperature compensation circuit, the drain of the PMOS transistor M5 is connected to the drain of the NMOS transistor M6 and the gate of the NMOS transistor M7, the gate of the PMOS transistor M8 is connected to the drain of the PMOS transistor M8, the gate of the PMOS transistor M9 and the drain of the NMOS transistor M7, the source of the NMOS transistor M7 is connected to the gate of the NMOS transistor M6 and one end of the resistor R2, the other end of the resistor R2 is connected to an external ground GND, the drain of the PMOS transistor M9 is connected to the drain of the PMOS transistor M10 and one end of the resistor R4, a node where the drain of the PMOS transistor M9 and the drain of the PMOS transistor M10 are connected is also used as a bandgap reference output terminal VREF, and the other end of the resistor R4 is connected to the external ground GND through the resistor R3; the node of the grid of the PMOS tube M8 and the grid of the PMOS tube M9 are connected with the high-temperature region compensation circuit and the low-temperature region compensation circuit, and the output end of the error amplifier A1 and the node of the resistor R3 and the resistor R4 are connected with the high-temperature region compensation circuit, the low-temperature region compensation circuit and the starting circuit.
4. The low-temperature-drift high-order temperature-compensation MOS bandgap reference circuit according to claim 3, wherein: the NMOS transistor M3, the NMOS transistor M4 and the NMOS transistor M6 all work in a subthreshold region, and the drain current of the PMOS transistor M10 generates a voltage V on the resistor R3 and the resistor R4PTATAnd is and
Figure FDA0002973464620000021
the drain current of the PMOS transistor M9 generates a voltage V on the resistor R3 and the resistor R4CTATAnd is and
Figure FDA0002973464620000022
in the formulae (1) and (2), q is an electronic charge, k is a boltzmann constant,t is absolute temperature, M is the ratio of the channel width-length ratio of the NMOS transistor M4 to the channel width-length ratio of the NMOS transistor M3, beta2Is the ratio of the channel width length ratio of the PMOS transistor M10 to the channel width length ratio of the PMOS transistor M1, beta3Is the ratio of the channel width length ratio of the PMOS transistor M9 to the channel width length ratio of the PMOS transistor M8, VGS6Is the gate-source voltage of NMOS transistor M6, and VGS6Having a negative temperature characteristic, voltage VCTATHas a negative temperature characteristic.
5. The low-temperature-drift high-order temperature-compensation MOS bandgap reference circuit according to claim 3, wherein: the high-temperature region compensation circuit comprises a PMOS tube M, an NMOS tube M and an NMOS tube M, wherein the grid electrode of the PMOS tube M is connected with the grid electrode of the PMOS tube M and the grid electrode of the PMOS tube M, the source electrode of the PMOS tube M is respectively connected with the source electrode of the PMOS tube M, the source electrode of the PMOS tube M and an external power supply VDD, the drain electrode of the PMOS tube M is respectively connected with the grid electrode of the NMOS tube M, the drain electrode of the NMOS tube M and the grid electrode of the NMOS tube M, the source electrode of the NMOS tube M is respectively connected with the source electrode of the NMOS tube M, the drain electrode of the NMOS tube M and an external GND ground wire, and the drain electrode of the PMOS tube M is respectively connected with the drain electrode of the NMOS tube M, the drain electrode of, the drain of the NMOS transistor M16 is connected to the common node of the resistors R3 and R4 and the drain of the NMOS transistor M22, the drain of the PMOS transistor M17 is connected to the drain of the NMOS transistor M18, the gate of the NMOS transistor M18 and the gate of the NMOS transistor M19, the drain of the PMOS transistor M20 is connected to the drain of the NMOS transistor M19, the drain of the NMOS transistor M21, the gate of the NMOS transistor M21 and the gate of the NMOS transistor M22, the gates of the PMOS transistor M14 and the PMOS transistor M20 are connected to the output terminal of the error amplifier a1, and the drain of the NMOS transistor M22 is connected to the common node of the resistors R3 and R4.
6. The low-temperature-drift high-order temperature compensation MOS band-gap reference circuit according to claim 5The method is characterized in that: the drain current I of the NMOS tube M1616The voltage V generated at the resistor R4N 1Comprises the following steps:
Figure FDA0002973464620000023
Figure FDA0002973464620000024
drain current I of NMOS transistor M2222The voltage V generated at the resistor R4N 2Comprises the following steps:
Figure FDA0002973464620000025
in the formulae (3) and (4), beta4Is the ratio of the channel width length ratio of the PMOS transistor M11 to the channel width length ratio of the PMOS transistor M8, beta5Is the ratio of the channel width length ratio of the PMOS transistor M14 to the channel width length ratio of the PMOS transistor M1, beta6Is the ratio of the channel width-length ratio of the NMOS transistor M16 to the channel width-length ratio of the NMOS transistor M15, beta7Is the ratio of the channel width length ratio of the PMOS transistor M17 to the channel width length ratio of the PMOS transistor M8, beta8Is the ratio of the channel width length ratio of the PMOS transistor M20 to the channel width length ratio of the PMOS transistor M1, beta9Is the ratio of the channel width length ratio of the NMOS tube M22 to the channel width length ratio of the NMOS tube M21, q is the electronic charge, k is the Boltzmann constant, T is the absolute temperature, M is the ratio of the channel width length ratio of the NMOS tube M4 to the channel width length ratio of the NMOS tube M3, VGS6Is the gate-source voltage, T, of the NMOS transistor M6r1Is a reference temperature and is greater than room temperature, Tr2Is a reference temperature and is greater than a reference temperature Tr1。
7. The low-temperature-drift high-order temperature-compensation MOS bandgap reference circuit according to claim 3, wherein: the low-temperature region compensation circuit comprises a PMOS tube M23, a PMOS tube M26, a PMOS tube M29, a PMOS tube M32, an NMOS tube M24, an NMOS tube M25, an NMOS tube M27, an NMOS tube M28, an NMOS tube M30, an NMOS tube M31, an NMOS tube M33 and an NMOS tube M34, wherein the source of the PMOS tube M23 is respectively connected with the source of the PMOS tube M26, the source of the PMOS tube M29, the source of the PMOS tube M32 and an external power supply VDD, the gate of the PMOS tube M23 is respectively connected with the output end of an error amplifier A1 and the gate of the PMOS tube M29, the drain of the PMOS tube M23 is respectively connected with the gate of the NMOS tube M24, the drain of the NMOS tube M24 and the gate of the NMOS tube M25, the source of the NMOS tube M24 is respectively connected with the source of the NMOS tube M25, the source of the NMOS tube M27, the source of the NMOS tube M28, the source of the NMOS tube M30, the drain of the NMOS tube M30 and the gate of the NMOS tube 30, the drain of the PMOS tube 30 are respectively connected with the drain, The grid electrode of the NMOS tube M27, the drain electrode of the NMOS tube M27 and the grid electrode of the NMOS tube M28 are connected, the drain electrode of the NMOS tube M28 is respectively connected with a common node of the resistor R3 and the resistor R4 and the drain electrode of the NMOS tube M34, the drain electrode of the PMOS tube M29 is respectively connected with the drain electrode of the NMOS tube M30, the grid electrode of the NMOS tube M30 and the grid electrode of the NMOS tube M31, and the drain electrode of the PMOS tube M32 is respectively connected with the drain electrode of the NMOS tube M31, the drain electrode of the NMOS tube M33, the grid electrode of the NMOS tube M33 and the grid electrode of the NMOS tube M34.
8. The low-temperature-drift high-order temperature-compensation MOS bandgap reference circuit according to claim 7, wherein: the drain current I of the NMOS tube M2828The voltage V generated at the resistor R4N 3Comprises the following steps:
Figure FDA0002973464620000031
Figure FDA0002973464620000032
the drain current I of the NMOS tube M3434The voltage V generated at the resistor R4N 4Is composed of
Figure FDA0002973464620000033
In the formulae (5) and (6), beta10Is the ratio of the channel width length ratio of the PMOS transistor M23 to the channel width length ratio of the PMOS transistor M1, beta11Is the ratio of the channel width length ratio of the PMOS transistor M26 to the channel width length ratio of the PMOS transistor M8, beta12Is the ratio of the channel width-length ratio of the NMOS transistor M28 to the channel width-length ratio of the NMOS transistor M27, beta13Is the channel width length ratio and PMO of the PMOS transistor M29Ratio of channel width to length, β, of S-tube M114Is multiplied by the ratio of the channel width-length ratio of the PMOS transistor M32 to the channel width-length ratio of the PMOS transistor M8, beta15Is the ratio of the channel width length ratio of the NMOS tube M34 to the channel width length ratio of the NMOS tube M33, q is the electronic charge, k is the Boltzmann constant, T is the absolute temperature, M is the ratio of the channel width length ratio of the NMOS tube M4 to the channel width length ratio of the NMOS tube M3, VGS6Is the gate-source voltage, T, of the NMOS transistor M6r3Is a reference temperature and is less than room temperature, Tr4Is a reference temperature and is less than a reference temperature Tr3。
9. The low-temperature-drift high-order temperature-compensation MOS bandgap reference circuit according to claim 3, wherein: the starting circuit comprises a PMOS tube Ms1, a PMOS tube Ms2, an NMOS tube Ms3 and an NMOS tube Ms4, wherein the source electrode of the PMOS tube Ms1 is connected with an external power supply VDD, the grid electrode of the PMOS tube Ms1 is connected with the drain electrode of the PMOS tube Ms1 and the source electrode of the PMOS tube Ms2 respectively, the grid electrode of the PMOS tube Ms2 is connected with the drain electrode of the PMOS tube Ms2, the grid electrode of the NMOS tube Ms3 and the drain electrode of the NMOS tube Ms4 respectively, the source electrode of the NMOS tube Ms3 is connected with the source electrode of the NMOS tube Ms4 and an external ground wire GND respectively, the drain electrode of the NMOS tube Ms3 is connected with the output end of the error amplifier A1, and the grid electrode of the NMOS tube Ms4 is connected with the common node of the resistor R63.
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