CN115016591B - Band gap reference circuit with low temperature drift - Google Patents

Band gap reference circuit with low temperature drift Download PDF

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CN115016591B
CN115016591B CN202210683723.0A CN202210683723A CN115016591B CN 115016591 B CN115016591 B CN 115016591B CN 202210683723 A CN202210683723 A CN 202210683723A CN 115016591 B CN115016591 B CN 115016591B
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pmos tube
tube
circuit
reference circuit
pmos
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CN115016591A (en
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宋宇
陈立新
熊海峰
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Shanghai Taisi Microelectronics Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

Disclosed is a band gap reference circuit of low temperature drift, comprising: a first-order bandgap reference circuit outputting currents IPTAT1, IPTAT2, IPTAT3 proportional to absolute temperature, a voltage VBE biased at the PTAT current, and a first-order compensated bandgap reference voltage VREF; the bandgap reference circuit further includes: a first-order zero-temperature current circuit and a high-order band-gap reference circuit; the high-order bandgap reference circuit includes: PMOS tube P1, PMOS tube P2, PMOS tube P3, PMOS tube P4, PMOS tube P6, NMOS tube N1, NMOS tube N2, NMOS tube N3, resistor R3, triode Q3 and triode Q4; the first-order zero-temperature current circuit comprises: PMOS tube P5, resistor R2, amplifier A1 and op circuit; the invention realizes the band gap reference circuit with low temperature drift lower than 5 ppm/DEG C.

Description

Band gap reference circuit with low temperature drift
Technical Field
The invention relates to the technical field of band gap reference circuits, in particular to a band gap reference circuit with low temperature drift.
Background
The band gap reference source is widely applied to various integrated circuits, plays an extremely important role in the modern integrated circuits at the increasingly developing day, plays an important role in analog-to-digital converters and digital-to-analog converters as well as some analog-to-digital circuits, and directly determines the precision and performance of the whole circuit by the temperature characteristic and noise resistance of the band gap reference source;
in order to ensure that the circuit has good performance and enough accurate precision, the current band gap reference circuit can not realize the temperature coefficient lower than 5 ppm/DEG C, and ensures that the lowest working voltage of the whole circuit is more than 2V;
the prior art can not meet the demands of people at present, and based on the present situation, the prior art needs to be improved.
Disclosure of Invention
The present invention is directed to a bandgap reference circuit with low temperature drift, so as to solve the problems set forth in the background art.
The invention provides a band gap reference circuit with low temperature drift, which comprises the following technical scheme: a first-order bandgap reference circuit, a first-order zero-temperature current circuit and a high-order bandgap reference circuit;
the first-order bandgap reference circuit outputs currents IPTAT1, IPTAT2, IPTAT3, VBE (voltage biased at PTAT current) and VREF (first-order compensated bandgap reference voltage) proportional to absolute temperature;
the high-order bandgap reference circuit includes: PMOS tube P1, PMOS tube P2, PMOS tube P3, PMOS tube P4, PMOS tube P6, NMOS tube N1, NMOS tube N2, NMOS tube N3, resistor R3, triode Q3 and triode Q4;
the IPTAT1 is loaded to the emitter of the triode Q4 through a resistor R3, the IPTAT1 is also loaded to the grid electrode of the PMOS tube P4, the IPTAT2 is loaded to the source electrodes of the PMOS tube P3 and the PMOS tube P4, the IPTAT3 is loaded to the source electrodes of the PMOS tube P1 and the PMOS tube P2, and the VBE is loaded to the grid electrode of the PMOS tube P1;
the first-order zero-temperature current circuit comprises: the power supply circuit comprises a PMOS tube P5, a resistor R2, an amplifier A1 and an OP circuit, wherein the source electrode of the PMOS tube P5 and the source electrode of the PMOS tube P6 are commonly coupled with a power supply end VDD, the PMOS tube P5 and the PMOS tube P6 are commonly coupled with a grid electrode, the drain electrode of the PMOS tube P5 is coupled to the power supply end VSS through the coupling resistor R2, the grid electrode of the PMOS tube P5 is also coupled to the output end of the amplifier A1, one input end of the amplifier A1 is loaded with VREF output by the first-order band gap reference circuit, the other input end is coupled to a connecting line of the drain electrode of the PMOS tube P5 and the resistor R2, and the power supply end of the amplifier is coupled to the OP circuit;
the invention has the following technical effects:
the invention is provided with a first-order band gap reference circuit, a first-order zero-temperature current circuit and a high-order band gap reference circuit, wherein the first-order band gap reference circuit is coupled with the first-order zero-temperature current circuit and the high-order band gap reference circuit by outputting currents IPTAT1, IPTAT2, IPTAT3, VBE and VREF which are in direct proportion to absolute temperature, the high-order band gap reference circuit is used for outputting a high-order band gap reference HPREF, and the EAD simulation software tool is used for simulating the circuit, so that the simulation result is 4.2 ppm/DEG C, and the temperature coefficient of the band gap reference circuit is lower than 5 ppm/DEG C, and the lowest working voltage in the whole circuit of the band gap reference circuit is higher than 2V.
Drawings
FIG. 1 is a schematic diagram of the overall circuit structure of the present invention;
FIG. 2 is a schematic diagram of a first-order bandgap reference circuit according to an embodiment of the invention;
FIG. 3 is a schematic diagram of an OP circuit according to an embodiment of the present invention;
FIG. 4 is a simulation plot of the band gap reference voltage HPREF curve for high order compensation output after simulation of the circuit of FIG. 1 by the EAD simulation software tool.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the present invention without making any inventive effort fall within the scope of the present invention.
Referring to FIG. 1, in one embodiment of the present invention, a bandgap reference circuit is provided for illustrating the structural composition of the bandgap reference circuit, the bandgap reference circuit comprising: a first-order bandgap reference circuit, a first-order zero-temperature current circuit and a high-order bandgap reference circuit;
the first-order bandgap reference circuit outputs currents IPTAT1, IPTAT2, IPTAT3, VBE (voltage biased at PTAT current) and VREF (first-order compensated bandgap reference voltage) proportional to absolute temperature;
the high-order bandgap reference circuit includes: PMOS tube P1, PMOS tube P2, PMOS tube P3, PMOS tube P4, PMOS tube P6, NMOS tube N1, NMOS tube N2, NMOS tube N3, resistor R3, triode Q3 and triode Q4;
in an embodiment, the IPTAT1 is loaded to the emitter of the triode Q4 through the resistor R3, and the IPTAT1 is also loaded to the gate of the PMOS tube P4, the IPTAT2 is loaded to the sources of the PMOS tube P3 and the PMOS tube P4, the IPTAT3 is loaded to the sources of the PMOS tube P1 and the PMOS tube P2, and the VBE is loaded to the gate of the PMOS tube P1; the grid electrode and the drain electrode of the PMOS tube P3 are in short circuit to output a high-order band gap reference HPREF, the drain electrode of the PMOS tube P3 is coupled with the drain electrode of the NMOS tube N2, the drain electrode of the PMOS tube P1 is coupled with the drain electrode of the NMOS tube N1, the drain electrode of the PMOS tube P2 is coupled with the drain electrode of the NMOS tube N3, one path of the grid electrode of the PMOS tube P2 is coupled with the drain electrode of the PMOS tube P6, and the other path of the grid electrode of the PMOS tube P2 is coupled with the emitter electrode of the triode Q3; the grid electrode of the NMOS tube N2 is coupled with the grid electrode of the NMOS tube N1, the grid electrode of the NMOS tube N1 is in short circuit with the drain electrode, and the grid electrode of the NMOS tube N3 is in short circuit with the drain electrode; the base electrode and the collector electrode of the triode Q3 and the triode Q4 are both coupled with the power supply end VSS, and the source electrode of the NMOS tube N1, the source electrode of the NMOS tube N2 and the source electrode of the NMOS tube N3 are coupled with the power supply end VSS;
in an embodiment, the first order zero temperature current circuit comprises: the power supply circuit comprises a PMOS tube P5, a resistor R2, an amplifier A1 and an OP circuit, wherein the source electrode of the PMOS tube P5 and the source electrode of the PMOS tube P6 are commonly coupled with a power supply end VDD, the PMOS tube P5 and the PMOS tube P6 are commonly coupled with a grid electrode, the drain electrode of the PMOS tube P5 is coupled to the power supply end VSS through the coupling resistor R2, the grid electrode of the PMOS tube P5 is also coupled to the output end of the amplifier A1, one input end of the amplifier A1 is loaded with VREF output by the first-order band gap reference circuit, the other input end is coupled to a connecting line of the drain electrode of the PMOS tube P5 and the resistor R2, and the power supply end of the amplifier is coupled to the OP circuit;
in an embodiment, there are a plurality of OP circuits (OP is an operational amplifier), and referring to fig. 3, this embodiment provides an OP circuit including: a direct current source, an NMOS tube NZ11, an NMOS tube NZ12, a PMOS tube PZ11 and a PMOS tube PZ12; the OP circuit is powered by a direct current source, the grid electrode of the NMOS tube NZ11 loads the positive input end IP of the OP circuit, the grid electrode of the NMOS tube NZ12 loads the negative input end IN of the OP circuit, and the output end OUT is loaded to the power supply end of the amplifier A1; the OP circuit is a common operational amplifier with NMOS as input and the function implemented is ip≡in.
The present invention provides another embodiment for illustrating the inference that the present invention achieves low temperature drift below 5ppm/°c, in which the first order bandgap reference circuit outputs currents IPTAT1, IPTAT2, IPTAT3, VBE (voltage biased at PTAT current), VREF (first order compensated bandgap reference voltage) proportional to absolute temperature, where IPTAT 3:iptat2=1:a, a is a constant; the width-to-length ratio of NMOS transistors N1 to N2, N1 to N2=1 to A'; wherein, a 'and a are constants with equal values, namely a=a', and the value a is uniformly adopted in the subsequent calculation formula; the width-to-length ratio of the PMOS tube P1 to the PMOS tube P2 is 1:1; the width-to-length ratio of the PMOS tube P3 to the PMOS tube P4 is 1:1; the width-to-length ratio of the PMOS tubes P1 and P3 is P1:P3=M:1, wherein M is a constant; there is no need to explicitly calculate the value of the constant A, M, and then calculate the high-order bandgap reference HPREF later.
Referring to fig. 2, in an embodiment, the present invention provides an embodiment of a first-order bandgap reference circuit, but the present invention is not limited to the first-order bandgap reference circuit of fig. 2, and the present invention may be applied to any circuit of a first-order bandgap reference.
Triode base-emission voltage formulas are known:
wherein V is G0 Is the bandgap voltage of silicon in the triode at zero K temperature; η is a process related constant;k' is Boltzmann constant, q is electron charge, T is working temperature; t (T) r Is a reference temperature; and I C For triode collector current, α is temperature dependent collector current I C Temperature order of (2); when I C When IPTAT is adopted, alpha is approximately equal to 1; when I C Approximately zero temperature current, α≡0.
Referring to FIG. 2, in an embodimentWherein the size ratio of transistors Q1 and Q2 is q1:q2=1:n, N being a constant;
referring to fig. 1, IN the embodiment, an OP circuit and a PMOS transistor P5 form a negative feedback loop, VREF is input to a negative input terminal IN of the OP circuit, a positive input terminal IP and a drain electrode of the PMOS transistor P5 are connected together, when IP becomes high, an output of the OP circuit becomes high, and the output of the OP circuit is input to a gate electrode of the PMOS transistor P5, the drain electrode of the PMOS transistor P5 becomes low, and returns to an IP terminal of the OP circuit to become low, so that negative feedback is formed, and as known from a virtual short theory of an amplifier, the two input terminals ip=in of the OP; the current flowing through the PMOS transistor P5 is VREF/R2, and since the PMOS transistor P5 and the PMOS transistor P6 have the same size and the same source and gate voltages, the current flowing through the PMOS transistor P6 is also VREF/R2, which is approximately zero temperature current, so in the VBE voltage of the transistor Q3, α≡0, then:
the bias current of transistor Q1 in fig. 2 is PTAT current, so α≡1 in VBE voltage of transistor Q1:
from this, it can be derived that:
the saturation current formula of the MOS tube is known:
I D ＝S*K*(V GS -V TH ) 2
the following conclusions are drawn:
S P1 *K*(V GS_P1 -V TH ) 2 +S P2 *K*(V GS_P2 -V TH ) 2 ＝I PTAT3 (1)
S P4 *K*(V GS_P4 -V TH ) 2 +S P3 *K*(V GS_P3 -V TH ) 2 ＝I PTAT2 (2)
It is known that:
the width-to-length ratio of the PMOS tube P1 to the PMOS tube P3 is P1:P3=M:1, the width-to-length ratio of the PMOS tube P1 to the PMOS tube P2 is 1:1, and the width-to-length ratio of the PMOS tube P3 to the PMOS tube P4 is 1:1, so that:
M*S P3 ＝M*S P4 ＝S P1 ＝S P2
as known, the width-to-length ratio N1:n2=1:a of the NMOS transistor N1 to the NMOS transistor N2, so:
S P3 *K*(V GS_P3 -V TH ) 2 ＝A*S P1 *K*(V GS_P1 -V TH ) 2 (3)
Namely: a x M (V GS_P1 -V TH ) 2 ＝(V GS_P3 -V TH ) 2 Formula (4);
(3) substituting to obtain: s is S P4 *K*(V GS_P4 -V TH ) 2 +A*S P1 *K*(V GS_P1 -V TH ) 2 ＝I PTAT2 (5)
IPTAT 3:iptat2=1:a is known and will be brought into:
A*M*(V GS_P2 -V TH ) 2 ＝(V GS_P4 -V TH ) 2 (6)
Is obtained from the formula (4) and the formula (6):
that is to say,
because of V G_P3 ＝HPREF，V G_P4 ＝V BE_Q4 +I PTAT * R3, can be obtained:
then:
wherein V is BE_Q4 Is the base-emitter voltage of α≡1, so the band-gap reference voltage for higher order compensation can be obtained:
then according to the formula of the formula,zero temperature HPREF can be obtained;
in an embodiment, the above derived higher order bandgap reference formula is ideal, and in fact, due to environmental impact and performance impact of components, the formulaThe two expressions are not necessarily all equal to 0, in the process used in this example, +.>Andafter the two equations are added, ΔV≡600uV is obtained. Wherein V is G0 The value is generally 1.2V; deltaV is the voltage difference of the high-order compensated bandgap reference voltage HPREF output in the selected temperature range, e.g., FIG. 4 selects 20 ℃ and 70 ℃, the voltage difference corresponding to 20 ℃ and 70 ℃ being DeltaV;
by a temperature coefficient calculation formula:
wherein C is RANGE Is a range of selected temperatures, temperature coefficient TC (Temperature Coefficient), typically expressed in ppm/°c, for a reference voltage, lpppm/°c represents the parts per million of the output voltage that deviate from its nominal value when the ambient temperature changes by 1 ℃ at some reference point (typically 25 ℃).
Specific temperature coefficients are thus obtained:
wherein V is G0 Is HPREF voltage at 25deg.C, 100 is C obtained from 60- (-40) by selecting the range of-40deg.C and 60 deg.C RANGE ＝100；
By the deduction of the formula, the inference that the invention can finally realize low-temperature drift lower than 5 ppm/DEG C can be obtained;
referring to fig. 4, in the examples, in order to demonstrate the correctness of the above-described embodiment derivation, the present invention brings the actual circuit shown in fig. 1 into simulation by means of an EAD simulation software tool, the simulation results refer to fig. 4, the abscissa in fig. 4 represents temperature, and the ordinate represents a band gap reference voltage HPREF for high-order compensation, wherein point a is the lowest point of the HPREF curve at-40 to 60 ℃, point B is the highest point of the HPREF curve at-40 to 60 ℃, Δv is about 0.5mV, and the typical value is 1.188V, so the simulation result is 4.2ppm/°c, less than 5ppm/°c, and it can be seen that the present invention realizes a band gap reference circuit of a temperature coefficient lower than 5ppm/°c.
In an embodiment, referring to fig. 1, the branch of iptat1 that is loaded to the higher order bandgap reference circuit is the circuit part that has the highest demand for supply voltage, and the lowest operating voltage of the branch circuit determines the lowest operating voltage of the overall circuit, calculated as follows:
VDDmax＝V BE_Q4 +IPTAT1*R3+V TH_P4 +V DSAT_PM2
wherein V is DSAT_PM2 The saturation voltage of the PM2 tube of the PMOS tube in FIG. 2; v (V) TH_P4 The threshold voltage of the P4 tube of the PMOS tube; v (V) BE_Q4 Base emitter voltage for transistor Q4 biased at PTAT1 current;
wherein V is BE_Q4 +IPTAT1*R3≈1.2V，V TH_P4 ＞0.7V，V DSAT_PM2 > 0.15V, VDDmax > 2V.
The lowest operating voltage of the entire bandgap reference circuit is greater than 2V while achieving a temperature coefficient of less than 5ppm/°c.
In an embodiment, the indexes of all MOS transistors are based on common parameters of 5V MOSFETs, and specifically vary according to the selected process.
Although the present invention has been described with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described, or equivalents may be substituted for elements thereof, and any modifications, equivalents, improvements and changes may be made without departing from the spirit and principles of the present invention.

Claims (10)

1. A low temperature drift bandgap reference circuit comprising: a first-order bandgap reference circuit outputting currents IPTAT1, IPTAT2, IPTAT3 proportional to absolute temperature, a voltage VBE biased at the PTAT current, and a first-order compensated bandgap reference voltage VREF;
the method is characterized in that the low temperature drift of the temperature coefficient of the band gap reference circuit is smaller than 5 ppm/DEG C, and the lowest working voltage of the whole band gap reference circuit is larger than 2V;
the bandgap reference circuit further includes: a first-order zero-temperature current circuit and a high-order band-gap reference circuit;
the high-order bandgap reference circuit includes: PMOS tube P1, PMOS tube P2, PMOS tube P3, PMOS tube P4, PMOS tube P6, NMOS tube N1, NMOS tube N2, NMOS tube N3, resistor R3, triode Q3 and triode Q4;
the IPTAT1 is loaded to the emitter of the triode Q4 through a resistor R3, the IPTAT1 is also loaded to the grid electrode of the PMOS tube P4, the IPTAT2 is loaded to the source electrodes of the PMOS tube P3 and the PMOS tube P4, the IPTAT3 is loaded to the source electrodes of the PMOS tube P1 and the PMOS tube P2, the VBE is loaded to the grid electrode of the PMOS tube P1, and the grid electrode and the drain electrode of the PMOS tube P3 are in short circuit to output a band gap reference voltage HPREF with high-order compensation;
the drain electrode of the PMOS tube P3 is coupled with the drain electrode of the NMOS tube N2, the drain electrode of the PMOS tube P1 is coupled with the drain electrode of the NMOS tube N1, the drain electrode of the PMOS tube P2 is coupled with the drain electrode of the NMOS tube N3, one path of the grid electrode of the PMOS tube P2 is coupled with the drain electrode of the PMOS tube P6, and the other path of the grid electrode of the PMOS tube P2 is coupled with the emitter electrode of the triode Q3;
the grid electrode of the NMOS tube N2 is coupled with the grid electrode of the NMOS tube N1, the grid electrode of the NMOS tube N1 is in short circuit with the drain electrode, and the grid electrode of the NMOS tube N3 is in short circuit with the drain electrode;
the base electrode and the collector electrode of the triode Q3 and the triode Q4 are both coupled with the power supply end VSS, and the source electrode of the NMOS tube N1, the source electrode of the NMOS tube N2 and the source electrode of the NMOS tube N3 are coupled with the power supply end VSS;
the first-order zero-temperature current circuit comprises: PMOS tube P5, resistor R2, amplifier A1 and OP circuit;
the source of the PMOS tube P5 and the source of the PMOS tube P6 are commonly coupled to the power supply end VDD, the drain of the PMOS tube P5 and the PMOS tube P6 are commonly coupled to the grid electrode, the drain of the PMOS tube P5 is coupled to the power supply end VSS through a coupling resistor R2, the grid electrode of the PMOS tube P5 is also coupled to the output end of the amplifier A1, one input end of the amplifier A1 is loaded with VREF output by the first-order band gap reference circuit, the other input end is coupled to the connecting line of the drain of the PMOS tube P5 and the resistor R2, and the power supply end of the amplifier is coupled to the OP circuit.
2. A low temperature drift bandgap reference circuit as claimed in claim 1, wherein: the OP circuit comprises: a direct current source, an NMOS tube NZ11, an NMOS tube NZ12, a PMOS tube PZ11 and a PMOS tube PZ12;
the OP circuit is powered by a direct current source, the grid electrode of the NMOS tube NZ11 loads the positive input end IP of the OP circuit, the grid electrode of the NMOS tube NZ12 loads the negative input end IN of the OP circuit, and the output end OUT of the OP circuit is loaded to the power supply end of the amplifier A1.
3. A low temperature drift bandgap reference circuit as claimed in claim 1, wherein: the first-order band gap reference circuit outputs a current iptat3 proportional to absolute temperature, iptat2=1: a, wherein a is a constant.
4. A low temperature drift bandgap reference circuit as claimed in claim 1, wherein: the width-to-length ratio N1 of the NMOS tube N1 to the NMOS tube N2 is as follows: n2=1: a'; where A' is a constant.
5. A low temperature drift bandgap reference circuit as claimed in claim 1, wherein: the width-to-length ratio of the PMOS tube P1 to the PMOS tube P2 is 1:1.
6. A low temperature drift bandgap reference circuit as claimed in claim 1, wherein: the width-to-length ratio of the PMOS tube P3 to the PMOS tube P4 is 1:1.
7. A low temperature drift bandgap reference circuit as claimed in claim 1, wherein: the width-to-length ratio p1:p3=m1 of the PMOS transistor P1 and the PMOS transistor P3, wherein M is a constant.
8. A low temperature drift bandgap reference circuit as claimed in claim 1, wherein: the band gap reference voltage calculation formula of the high-order compensation is as follows:
wherein,
V G0 is the bandgap voltage of silicon in a triode at zero K temperature, eta is a process-related constant,k' is Boltzmann constant, q is electron charge, T is operating temperature, T r Is the reference temperature, and I C Is triode collector current, alpha is temperature-dependent collector current I C Temperature order of (2); n is a constant of the size ratio of the triodes Q1 and Q2, A is a constant of the current value ratio of the current IPTAT3 to the current value ratio of the current IPTAT2, and M is a constant of the width-to-length ratio of the PMOS tube P1 to the MPOS tube P3.
9. A low temperature drift bandgap reference circuit as claimed in claim 1, wherein: the calculation formula of the temperature coefficient of the band gap reference circuit is less than 5 ppm/DEG C:
wherein,
DeltaV is a higher order output over a selected temperature rangeThe voltage difference of the compensated bandgap reference voltage HPREF, deltaV takes a value of 600uV; v (V) G0 Is the band gap voltage of silicon in triode at zero K temperature, V G0 The value was 1.2V.
10. The bandgap reference circuit of claim 1, wherein said bandgap reference circuit has a minimum operating voltage greater than 2V calculated by:
VDDmax＝V BE_Q4 +IPTAT1*R3+V TH_P4 +V DSAT_PM2
wherein V is DSAT_PM2 The saturation voltage of the PM2 tube of the PMOS tube; v (V) TH_P4 The threshold voltage of the P4 tube of the PMOS tube; v (V) BE_Q4 Base emitter voltage for transistor Q4 biased at PTAT1 current;
wherein V is BE_Q4 +iptat1×r3 has a value of 1.2v, v TH_P4 ＞0.7V，V DSAT_PM2 ＞0.15V。
CN202210683723.0A 2022-06-16 2022-06-16 Band gap reference circuit with low temperature drift Active CN115016591B (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140028447A (en) * 2012-08-29 2014-03-10 엘지디스플레이 주식회사 Current reference circuit
CN105786077A (en) * 2016-04-20 2016-07-20 广东工业大学 High-order temperature drift compensation band-gap reference circuit without operational amplifier
CN109062310A (en) * 2018-07-13 2018-12-21 厦门芯豪科技有限公司 A kind of low-power consumption band-gap reference circuit with source compensated by using high-order curvature
CN111949063A (en) * 2020-08-10 2020-11-17 上海川土微电子有限公司 Band-gap reference voltage source with low temperature drift
CN113031690A (en) * 2021-03-12 2021-06-25 电子科技大学 High-order temperature compensation MOS band gap reference circuit with low temperature drift
CN113608568A (en) * 2021-06-18 2021-11-05 西安电子科技大学 Low-power-consumption low-voltage low-temperature-drift band-gap reference voltage source

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140028447A (en) * 2012-08-29 2014-03-10 엘지디스플레이 주식회사 Current reference circuit
CN105786077A (en) * 2016-04-20 2016-07-20 广东工业大学 High-order temperature drift compensation band-gap reference circuit without operational amplifier
CN109062310A (en) * 2018-07-13 2018-12-21 厦门芯豪科技有限公司 A kind of low-power consumption band-gap reference circuit with source compensated by using high-order curvature
CN111949063A (en) * 2020-08-10 2020-11-17 上海川土微电子有限公司 Band-gap reference voltage source with low temperature drift
CN113031690A (en) * 2021-03-12 2021-06-25 电子科技大学 High-order temperature compensation MOS band gap reference circuit with low temperature drift
CN113608568A (en) * 2021-06-18 2021-11-05 西安电子科技大学 Low-power-consumption low-voltage low-temperature-drift band-gap reference voltage source

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
一种带曲率补偿的高精度带隙基准源设计;张龙;冯全源;王丹;;微电子学;20150420(第02期);全文 *

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