CN113608568A - Low-power-consumption low-voltage low-temperature-drift band-gap reference voltage source - Google Patents

Abstract

The invention discloses a low-power-consumption low-voltage low-temperature-drift band-gap reference voltage source, which comprises a starting circuit, a band-gap reference core circuit and a reference power generation circuit, wherein the starting circuit is used for starting the band-gap reference core circuit and the reference power generation circuit in the power-on process of power voltage; the band-gap reference core circuit is used for generating positive temperature coefficient current; the reference power supply generation circuit is used for generating negative temperature coefficient current, primarily compensates the negative temperature coefficient current by using a source level negative feedback structure consisting of a triode and an NMOS (N-channel metal oxide semiconductor) tube, and mutually compensates the positive temperature coefficient current and voltage generated by the negative temperature coefficient current by using a resistor connection to obtain a reference voltage source. The band-gap reference voltage source adopts the negative temperature coefficient difference of the emitter junction voltage of a triode and the grid source voltage of an NMOS tube and source level negative feedback, and can obtain a reference voltage source with a low temperature drift coefficient.

Description

Low-power-consumption low-voltage low-temperature-drift band-gap reference voltage source

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a low-power-consumption low-voltage low-temperature-drift band-gap reference voltage source.

Background

With the rapid development of the internet of things industry, the market of wireless electronic devices is rapidly growing. Meanwhile, as the process nodes of the integrated circuit are reduced, the integration index of the electronic components is increased. As a basic unit of a circuit, a bandgap reference voltage source plays a great role in reference source applications of a chip, such as reference potentials of an operational amplifier, an ADC, an error amplifier, and the like, and the performance of the bandgap reference voltage source often greatly affects the performance of the whole system.

A conventional bandgap reference voltage source is shown in figure 1. The closed loop formed by the operational amplifier and the PMOS transistors M1 and M2 forces the voltage at the node X, Y to be equal, i.e. V_X＝V_YTherefore, the currents flowing through the triodes on the two sides are ensured to be the same, namely, positive temperature coefficient current is generated:

wherein the content of the first and second substances,

k is Boltzmann constant, T is absolute temperature, Q is unit charge and power, n is the area ratio of transistors Q1 and Q2, and R1 is a resistor. This current is ideally invariant to the supply voltage and is proportional to absolute temperature.

Positive temperature coefficient current I_PTATThe band-gap reference voltage is generated by copying a PMOS (P-channel metal oxide semiconductor) transistor M3 to an output circuit

Wherein, V_BE3Is the emitter junction voltage of transistor Q3 and exhibits a negative temperature coefficient characteristic. Under ideal conditions, by rational regulation

And obtaining a reference voltage source with lower sensitivity to temperature change.

The bandgap reference voltage source of the conventional structure has significant disadvantages. The transistor is characterized in that in practical application, the emitter junction voltage V of the transistor_BEThe negative temperature coefficient of (a) exhibits nonlinearity, and it is difficult to achieve a good effect only by first-order temperature compensation. And due to the emitter junction voltage V of transistor Q3_BE3The output voltage is large, and the requirement of a low-power consumption circuit is difficult to meet. Therefore, the conventional bandgap reference voltage source structure cannot be well adapted to increasingly advanced low-voltage and low-power consumption circuits.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a low-power-consumption low-voltage low-temperature-drift bandgap reference voltage source. The technical problem to be solved by the invention is realized by the following technical scheme:

the invention provides a low-power consumption, low-voltage and low-temperature-drift band-gap reference voltage source, which comprises a starting circuit, a band-gap reference core circuit and a reference power supply generating circuit, wherein,

the starting circuit is used for starting the band-gap reference core circuit and the reference power supply generating circuit in the power-on process of the power supply voltage;

the band-gap reference core circuit is used for generating positive temperature coefficient current;

the reference power supply generation circuit is used for generating negative temperature coefficient current, primarily compensates the negative temperature coefficient current by using a source level negative feedback structure consisting of a triode and an NMOS (N-channel metal oxide semiconductor) tube, and mutually compensates the positive temperature coefficient current and voltage generated by the negative temperature coefficient current by using a resistor connection to obtain a reference voltage source.

In one embodiment of the present invention, the start-up circuit comprises a PMOS transistor M16, a PMOS transistor M17, an NMOS transistor M18, and an NMOS transistor M19, wherein,

the source electrode of the PMOS tube M16 is connected with a power supply voltage VDD, and the drain electrode and the grid electrode are both connected with the source electrode of the PMOS tube M17; the grid electrode of the PMOS transistor M17 and the grid electrode of the NMOS transistor M18 are both connected to the output end of a reference voltage Vr, and the drain electrode of the PMOS transistor M17 and the drain electrode of the NMOS transistor M18 are both connected to the grid electrode of the NMOS transistor M19; the drain electrode of the NMOS tube M19 is connected with the reference power supply generation circuit and the band-gap reference core circuit, and the source electrode of the NMOS tube M18 and the source electrode of the NMOS tube M19 are both connected with the ground potential GND.

In an embodiment of the invention, the bandgap reference core circuit includes a PMOS transistor M5, a PMOS transistor M6, a PMOS transistor M9, a PMOS transistor M10, a PMOS transistor M11, an NMOS transistor M1, an NMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M7, an NMOS transistor M8, a transistor Q1, a transistor Q2, a resistor Rb, a resistor Rz, and a capacitor Cc, wherein,

the source electrode of the PMOS transistor M5, the source electrode of the PMOS transistor M6, the source electrode of the PMOS transistor M9, the source electrode of the PMOS transistor M10 and the source electrode of the PMOS transistor M11 are all connected with a power supply voltage VDD, and the gate electrode of the PMOS transistor M9, the gate electrode of the PMOS transistor M10, the gate electrode of the PMOS transistor M11 and the drain electrode of the PMOS transistor M5 are all connected to the drain electrode of the NMOS transistor M19;

the capacitor Cc and the resistor Rz are connected in series between the gate and the drain of the PMOS transistor M10, the resistor Rb is connected between the drain of the PMOS transistor M10 and the emitter of the triode Q2, and the base and the collector of the triode Q2 are both connected with the ground potential GND; the emitter of the triode Q1 is connected with the drain of the PMOS tube M11, and the base and the collector are both connected with the ground potential GND;

the grid electrode of the NMOS tube M3 and the grid electrode of the NMOS tube M7 are both connected with the drain electrode of the PMOS tube M11, the grid electrode of the NMOS tube M8 and the grid electrode of the NMOS tube M4 are both connected with the drain electrode of the PMOS tube M10, the drain electrode of the NMOS tube M7 and the drain electrode of the NMOS tube M8 are both connected with the drain electrode of the PMOS tube M9, and the source electrode of the NMOS tube M7 and the source electrode of the NMOS tube M8 are both connected with the drain electrode of the NMOS tube M2;

the grid and the drain of the NMOS transistor M2 are both connected with the grid of the NMOS transistor M1, the source of the NMOS transistor M1 and the source of the NMOS transistor M2 are both connected with ground potential GND, and the source of the NMOS transistor M3 and the source of the NMOS transistor M4 are both connected with the drain of the NMOS transistor M1;

the drain electrode of the PMOS tube M5 is connected with the drain electrode of an NMOS tube M3, and the grid electrode of the PMOS tube M5 and the grid electrode of the PMOS tube M6 are both connected with the drain electrode of the PMOS tube M6; the drain electrode of the NMOS tube M4 is connected with the drain electrode of the PMOS tube M6.

In one embodiment of the present invention, the reference power generating circuit includes an NMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M15, a resistor R1, a resistor R2, a resistor R3, and a resistor R4, wherein,

the source electrode of the PMOS transistor M13, the source electrode of the PMOS transistor M14 and the source electrode of the PMOS transistor M15 are all connected with a power supply voltage VDD; the drain electrode of the PMOS pipe M15 is used as the output end of the reference voltage Vr; the grid electrode of the PMOS tube M15 is connected with the drain electrode of the PMOS tube M5;

the resistor R2, the resistor R3 and the resistor R4 are connected in series between the drain of the PMOS tube M15 and the ground potential GND; the drain electrode of the PMOS pipe M14 is connected between the resistor R3 and the resistor R4; the grid electrode of the PMOS transistor M14 and the grid electrode of the PMOS transistor M13 are both connected with the source electrode of the PMOS transistor M13; the source electrode of the NMOS transistor M12 is connected with the drain electrode of the PMOS transistor M13, and the gate electrode of the NMOS transistor M12 is connected with the emitter electrode of the triode Q1; the resistor R1 is connected between the drain of the NMOS transistor M12 and the ground potential GND.

Compared with the prior art, the invention has the beneficial effects that:

1. the invention makes up the problem of larger emitter junction voltage V of the triode by using the NMOS tube as the input stage of the operational amplifier in the band-gap reference voltage circuit_BEThe PMOS tube is used as the weak point that the input stage overdrive voltage of the operational amplifier is insufficient under low voltage, thereby meeting the requirement of low-voltage operation.

2. The invention adopts the emitter junction voltage V of the triode in the reference power supply generating circuit_BEAnd the gate-source voltage V of the NMOS tube_GSThe method for making difference of negative temperature coefficient and the source level negative feedback technology can obtain a lower and more stable negative temperature coefficient, and when the method is applied to a circuit, the positive temperature coefficient and the negative temperature coefficient are adjusted by matching with a resistor, finally a reference voltage source with low temperature drift coefficient can be obtained, the power consumption is lower than 2uW, the output voltage is 800mV, [ -20 ℃,110 DEG C]The temperature drift coefficient in the temperature range is about 0.86 ppm/DEG C, and the output noise has excellent performance.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

FIG. 1 is a circuit diagram of a conventional bandgap reference voltage source;

FIG. 2 is a circuit diagram of a low-power consumption, low-voltage and low-temperature-drift bandgap reference voltage source according to an embodiment of the present invention;

FIG. 3a shows the emitter junction voltage V of the transistor_BEAnd NMOS tube gate source voltage V_GSEach according to temperatureA simulation graph of the changes;

FIG. 3b shows the emitter junction voltage V of the transistor_BEAnd NMOS tube gate source voltage V_GSA simulation graph of the negative temperature coefficient of (a) with temperature variation;

fig. 4a to 4d are graphs showing simulation results of the bandgap reference voltage source with low power consumption, low voltage and low temperature drift according to the embodiment of the invention.

Detailed Description

In order to further explain the technical means and effects of the present invention adopted to achieve the predetermined object, a low power consumption and low voltage and low temperature drift bandgap reference voltage source according to the present invention is described in detail below with reference to the accompanying drawings and the detailed description.

The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or device comprising the element.

Referring to fig. 2, fig. 2 is a circuit diagram of a low-power consumption, low-voltage and low-temperature-drift bandgap reference voltage source according to an embodiment of the present invention. The band-gap reference voltage source comprises a starting circuit, a band-gap reference core circuit and a reference power supply generating circuit, wherein,

comprises a starting circuit, a band-gap reference core circuit and a reference power supply generating circuit, wherein,

the starting circuit is used for starting the band-gap reference core circuit and the reference power supply generating circuit in the power-on process of the power supply voltage;

the band-gap reference core circuit is used for generating positive temperature coefficient current;

the reference power supply generation circuit is used for generating negative temperature coefficient current, primarily compensates the negative temperature coefficient current by using a source level negative feedback structure consisting of a triode and an NMOS (N-channel metal oxide semiconductor) tube, and mutually compensates the positive temperature coefficient current and voltage generated by the negative temperature coefficient current by using a resistor connection to obtain a reference voltage source.

Further, the starting circuit comprises a PMOS tube M16, a PMOS tube M17, an NMOS tube M18 and an NMOS tube M19, wherein,

the source electrode of the PMOS tube M16 is connected with a power supply voltage VDD, and the drain electrode and the grid electrode are both connected with the source electrode of the PMOS tube M17; the grid electrode of the PMOS transistor M17 and the grid electrode of the NMOS transistor M18 are both connected to the output end of a reference voltage Vr, and the drain electrode of the PMOS transistor M17 and the drain electrode of the NMOS transistor M18 are both connected to the grid electrode of the NMOS transistor M19; the drain electrode of the NMOS tube M19 is connected with the reference power supply generation circuit and the band-gap reference core circuit, and the source electrode of the NMOS tube M18 and the source electrode of the NMOS tube M19 are both connected with the ground potential GND.

Further, the band gap reference core circuit comprises a PMOS tube M5, a PMOS tube M6, a PMOS tube M9, a PMOS tube M10, a PMOS tube M11, an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M7, an NMOS tube M8, a triode Q1, a triode Q2, a resistor Rb, a resistor Rz and a capacitor Cc, wherein,

the source electrode of the PMOS transistor M5, the source electrode of the PMOS transistor M6, the source electrode of the PMOS transistor M9, the source electrode of the PMOS transistor M10 and the source electrode of the PMOS transistor M11 are all connected with a power supply voltage VDD, and the gate electrode of the PMOS transistor M9, the gate electrode of the PMOS transistor M10, the gate electrode of the PMOS transistor M11 and the drain electrode of the PMOS transistor M5 are all connected to the drain electrode of the NMOS transistor M19;

the capacitor Cc and the resistor Rz are connected in series between the gate and the drain of the PMOS transistor M10, the resistor Rb is connected between the drain of the PMOS transistor M10 and the emitter of the triode Q2, and the base and the collector of the triode Q2 are both connected with the ground potential GND; the emitter of the triode Q1 is connected with the drain of the PMOS tube M11, and the base and the collector are both connected with the ground potential GND;

the grid electrode of the NMOS tube M3 and the grid electrode of the NMOS tube M7 are both connected with the drain electrode of the PMOS tube M11, the grid electrode of the NMOS tube M8 and the grid electrode of the NMOS tube M4 are both connected with the drain electrode of the PMOS tube M10, the drain electrode of the NMOS tube M7 and the drain electrode of the NMOS tube M8 are both connected with the drain electrode of the PMOS tube M9, and the source electrode of the NMOS tube M7 and the source electrode of the NMOS tube M8 are both connected with the drain electrode of the NMOS tube M2;

the grid and the drain of the NMOS transistor M2 are both connected with the grid of the NMOS transistor M1, the source of the NMOS transistor M1 and the source of the NMOS transistor M2 are both connected with ground potential GND, and the source of the NMOS transistor M3 and the source of the NMOS transistor M4 are both connected with the drain of the NMOS transistor M1;

the drain electrode of the PMOS tube M5 is connected with the drain electrode of an NMOS tube M3, and the grid electrode of the PMOS tube M5 and the grid electrode of the PMOS tube M6 are both connected with the drain electrode of the PMOS tube M6; the drain electrode of the NMOS tube M4 is connected with the drain electrode of the PMOS tube M6.

Further, the reference power generating circuit comprises an NMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M15, a resistor R1, a resistor R2, a resistor R3 and a resistor R4, wherein,

the source electrode of the PMOS transistor M13, the source electrode of the PMOS transistor M14 and the source electrode of the PMOS transistor M15 are all connected with a power supply voltage VDD; the drain electrode of the PMOS pipe M15 is used as the output end of the reference voltage Vr; the grid electrode of the PMOS tube M15 is connected with the drain electrode of the PMOS tube M5;

the resistor R2, the resistor R3 and the resistor R4 are connected in series between the drain of the PMOS tube M15 and the ground potential GND; the drain electrode of the PMOS pipe M14 is connected between the resistor R3 and the resistor R4; the grid electrode of the PMOS transistor M14 and the grid electrode of the PMOS transistor M13 are both connected with the source electrode of the PMOS transistor M13; the source electrode of the NMOS transistor M12 is connected with the drain electrode of the PMOS transistor M13, and the gate electrode of the NMOS transistor M12 is connected with the emitter electrode of the triode Q1; the resistor R1 is connected between the drain of the NMOS transistor M12 and the ground potential GND.

Further, the transistor Q2 includes at least two transistors that are identical to and parallel to the transistor Q1.

The working principle of the band-gap reference voltage source is as follows:

the starting circuit ensures that the power supply voltage VDD is subjected to a power-on process and is increased from 0V to 1V, and the expected function can be realized after the power supply voltage VDD is stabilized. The PMOS transistor M17 and the NMOS transistor M18 form an inverter structure, and the PMOS transistor M16 is connected in a diode form, so that the voltage transmitted to the drain electrode of the PMOS transistor M10 by the power supply voltage VDD is reduced, normal on-off of the inverter is guaranteed, and power consumption is reduced, wherein the voltage serves as the high level of the inverter. In the power-on process of the power supply voltage VDD, the inverter outputs a high level to control the NMOS transistor M19 to be conducted, the grid potentials of the PMOS transistors M5, M10, M11 and M15 are pulled down to the ground potential GND, and at the moment, the band gap reference core circuit and the reference power supply generation circuit start to work. When the output reference potential Vr rises to be greater than the threshold voltage of the NMOS transistor M18, the inverter formed by the PMOS transistor M17 and the NMOS transistor M18 outputs low level, the NMOS transistor M19 is turned off, and the dynamic power consumption is gradually reduced to 0. The overall circuit stabilizes over a period of time. The starting circuit of the embodiment adopts a logic structure switch, and has the advantage of extremely low static power consumption.

Further, an NMOS transistor M1, an NMOS transistor M3, an NMOS transistor M4, a PMOS transistor M5, and a PMOS transistor M6 in the bandgap reference core circuit form a five-transistor OTA (operational amplifier), and the five-transistor OTA, the PMOS transistor M10, the PMOS transistor M11, the transistor Q1, the transistor Q2, and the resistor Rb form a main structure of the bandgap reference, so as to obtain a positive temperature coefficient current:

wherein the content of the first and second substances,

k is Boltzmann's constant, T is absolute temperature, Q is the amount of charge per unit, and n is the area ratio of transistors Q1 and Q2.

The NMOS transistor M2, the NMOS transistor M7, the NMOS transistor M8 and the PMOS transistor M9 provide bias for a tail current transistor M1 of the five-transistor OTA. The resistor Rz and the capacitor Cc introduce Miller compensation in a feedback loop from the five-transistor OTA to the PMOS transistor M10 and the PMOS transistor M11, so that the loop stability and the bandwidth of the band-gap reference core circuit are improved. NMOS transistor M3 and NMOS transistor M4 act as input stages of the five-transistor OTA because: triode V_BEThe PMOS tube is used as an input stage, the OTA is difficult to be ensured to be in a saturation region under the low-voltage and low-power consumption work of the circuit, and meanwhile the intrinsic gain of the NMOS tube is large, so the NMOS tube is used as the input stage.

The NMOS transistor M12, the PMOS transistor M13 and the resistor R1 in the reference power generation circuit generate negative temperature coefficient current I_CTATThe PMOS tube M13 and the PMOS tube M14 form a current mirror to copy the negative temperature coefficient current I_CTATCurrent flows to resistor R4. PMOS transistor M15 copies PTC current I_PTATFlows in sequence to the resistor R2, the resistor R3, and the resistor R4. The drain of the PMOS transistor M15 is used as the output Vr of the bandgap reference voltage source of this embodiment. Its internal principle is as follows.

In the circuit topology structure of the NMOS transistor M12, the PMOS transistor M13 and the resistor R1, the NMOS transistor M12 and the resistor R1 form source negative feedback, and the PMOS transistor M13 serves as a load. According to the band-gap reference voltage source provided by the embodiment of the invention, the negative temperature coefficient current with lower sensitivity to temperature change is obtained through the structure, so that the low temperature drift coefficient is integrally realized in the process of mutual compensation with the positive temperature coefficient current. Specifically, the emitter junction voltage V of transistor Q1_BEThe absolute value of the negative temperature coefficient is large, and the change is large; grid source voltage V of NMOS tube_GSThe absolute value of the negative temperature coefficient of (3) is small and the variation is small. In the source negative feedback structure, the input voltage of the gate of the NMOS transistor M12 is the emitter junction voltage V of the transistor Q1_BEBy this structure, the emitter junction voltage V of the transistor Q1 is utilized_BEAnd the grid source voltage V of the NMOS tube_GSThe negative temperature coefficient is used for making difference, and simultaneously, the characteristic that the source negative feedback per se relaxes the input voltage is also utilized, so that the electricity is improvedThe negative temperature coefficient voltage on the resistor R1 and the negative temperature coefficient current flowing on the resistor R1 are

The current flowing from the PMOS transistor M14 to the resistor R4

Wherein, (W/L)₁₃Represents the width-to-length ratio (W/L) of the PMOS tube M13₁₄The width-to-length ratio of the PMOS transistor M14 is shown. The PMOS transistor M15 sequentially flows to the resistor R2, the resistor R3 and the resistor R4 with the current of

Wherein, (W/L)₁₅Represents the width-to-length ratio (W/L) of the PMOS tube M15₁₁The width-to-length ratio of the PMOS transistor M11 is shown. The output reference voltages are as follows:

the parameters are arranged to obtain:

according to the above formula, by adjusting the width-to-length ratio of M11, M13, M14 and M15, the area ratio n of the transistors Q1 and Q2, and the sizes of the resistors Rb, R1, R2, R3 and R4, a desired output reference voltage can be obtained. The area ratio n of the resistor Rb to the triodes Q1 and Q2 is mainly used for adjusting the positive temperature coefficient current I generated by the band gap reference core circuit_PTATCurrent flow; the resistor R1 regulates the obtained negative temperature coefficient current I_CTATThe magnitude of the current; adjusting the sizes of the resistors R2, R3 and R4 to ensure that the current I has positive temperature coefficient_PTATThe voltage generated by the resistors R3 and R4 has positive temperature characteristic, and the voltage generated by the negative temperature coefficient current flowing through R4 has negative temperature characteristic, so that the purpose of positive and negative temperature characteristic compensation is achieved, and the sensitivity of the output reference voltage to the temperature is reduced. In the process, the resistors R3 and R4 work togetherAdjusting the approximate value of the output reference voltage and realizing mutual compensation of positive and negative temperature drift coefficients to serve as coarse adjustment; resistors R2, R3 act together to adjust the precise value of the output reference voltage and the temperature range of the low temperature drift coefficient as a fine tuning.

Compared with the traditional structure (the traditional structure is caused by the emitter junction voltage V) through the band gap reference voltage source generated by the current with positive and negative temperature coefficients flowing through the resistors R2, R3 and R4_BELarge in itself and difficult to obtain a lower output voltage), which can obtain a lower output voltage.

The bandgap reference voltage source of the embodiment of the present invention is further described with reference to simulation experiments.

The circuit elements of the simulation experiment of the embodiment of the invention adopt a CMOS process, and a simulation circuit is built in Cadence software under a Linux operating system. The embodiment of the invention adopts a SpectreRF simulation tool to respectively carry out relevant performance simulation on the circuit.

FIG. 3a shows the emitter junction voltage V of the transistor_BEAnd NMOS tube gate source voltage V_GSSimulation graphs of each variation with temperature; FIG. 3b shows the emitter junction voltage V of the transistor_BEAnd a simulation diagram of the NMOS tube grid source voltage negative temperature coefficient changing with the temperature. As can be seen from FIGS. 3a and 3b, the emitter junction voltage V is generated by a triode_BEAnd NMOS tube gate source voltage V_GSThe emitter junction voltage V of the triode can be realized under the condition of the lowest power consumption and area by combining the negative temperature coefficient difference of the resistor R1 and adopting a source level negative feedback technology_BEThe negative temperature coefficient of (a) is primarily compensated.

Fig. 4a to 4d are graphs showing simulation results of the bandgap reference voltage source with low power consumption, low voltage and low temperature drift according to the embodiment of the present invention, wherein fig. 4a is a graph showing the voltage variation of the resistor R1 with temperature, compared with the emitter junction voltage V of the transistor in fig. 3a_BEThe negative temperature coefficient of the voltage on the integral resistor R1 is changed, and the negative temperature coefficient of the voltage on the integral resistor R1 is moderate, so that the negative temperature characteristic of the circuit is improved to a great extent by a source-level negative feedback structure; fig. 4b is a simulation of the overall loop stability in a bandgap reference core circuit, showing that the overall loop bandwidth of the bandgap reference core circuit is greater than 800kHz,the phase margin is larger than 54 deg; FIG. 4c is a simulation graph of the variation of the output reference voltage Vr with temperature, calculated at-20 deg.C, 110 deg.C]The temperature drift coefficient is about 0.86 ppm/DEG C in a temperature range; FIG. 4d is a graph of a simulation of the output noise power spectrum at an output reference voltage Vr, the output noise power spectral density being about at 100Hz

The graph shows that the output noise spectrum has excellent performance.

The simulation results show that: the band-gap reference voltage source has outstanding overall performance and can realize low power consumption, low voltage and low temperature drift.

In summary, the embodiment of the invention uses the NMOS transistor as the input stage of the operational amplifier in the bandgap reference voltage circuit, thereby making up for the larger emitter junction voltage V of the triode_BEThe PMOS tube is used as the weak point that the input stage overdrive voltage of the operational amplifier is insufficient under low voltage, so that the requirement of low-voltage work is met; by using emitter junction voltage V of triode in reference power supply generation circuit_BEAnd the gate-source voltage V of the NMOS tube_GSThe method for making difference of negative temperature coefficient and the source level negative feedback technology can obtain a lower and more stable negative temperature coefficient, and when the method is applied to a circuit, the positive temperature coefficient and the negative temperature coefficient are adjusted by matching with a resistor, finally a reference voltage source with low temperature drift coefficient can be obtained, the power consumption is lower than 2uW, the output voltage is 800mV, [ -20 ℃,110 DEG C]The temperature drift coefficient in the temperature range is about 0.86 ppm/DEG C, and the output noise has excellent performance.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (4)

1. A low-power consumption, low-voltage and low-temperature drift band-gap reference voltage source is characterized by comprising a starting circuit, a band-gap reference core circuit and a reference power supply generating circuit, wherein,

the starting circuit is used for starting the band-gap reference core circuit and the reference power supply generating circuit in the power-on process of the power supply voltage;

the band-gap reference core circuit is used for generating positive temperature coefficient current;

the reference power supply generation circuit is used for generating negative temperature coefficient current, primarily compensates the negative temperature coefficient current by using a source level negative feedback structure consisting of a triode and an NMOS (N-channel metal oxide semiconductor) tube, and mutually compensates the positive temperature coefficient current and voltage generated by the negative temperature coefficient current by using a resistor connection to obtain a reference voltage source.

2. The low-power consumption, low-voltage and low-temperature drift bandgap reference voltage source according to claim 1, wherein the start-up circuit comprises a PMOS transistor M16, a PMOS transistor M17, an NMOS transistor M18 and an NMOS transistor M19, wherein,

the source electrode of the PMOS tube M16 is connected with a power supply voltage VDD, and the drain electrode and the grid electrode are both connected with the source electrode of the PMOS tube M17; the grid electrode of the PMOS transistor M17 and the grid electrode of the NMOS transistor M18 are both connected to the output end of a reference voltage Vr, and the drain electrode of the PMOS transistor M17 and the drain electrode of the NMOS transistor M18 are both connected to the grid electrode of the NMOS transistor M19; the drain electrode of the NMOS tube M19 is connected with the reference power supply generation circuit and the band-gap reference core circuit, and the source electrode of the NMOS tube M18 and the source electrode of the NMOS tube M19 are both connected with the ground potential GND.

3. The low-power consumption, low-voltage and low-temperature drift bandgap reference voltage source according to claim 2, wherein the bandgap reference core circuit comprises a PMOS transistor M5, a PMOS transistor M6, a PMOS transistor M9, a PMOS transistor M10, a PMOS transistor M11, an NMOS transistor M1, an NMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M7, an NMOS transistor M8, a triode Q1, a triode Q2, a resistor Rb, a resistor Rz and a capacitor Cc, wherein,

the source electrode of the PMOS transistor M5, the source electrode of the PMOS transistor M6, the source electrode of the PMOS transistor M9, the source electrode of the PMOS transistor M10 and the source electrode of the PMOS transistor M11 are all connected with a power supply voltage VDD, and the gate electrode of the PMOS transistor M9, the gate electrode of the PMOS transistor M10, the gate electrode of the PMOS transistor M11 and the drain electrode of the PMOS transistor M5 are all connected to the drain electrode of the NMOS transistor M19;

the capacitor Cc and the resistor Rz are connected in series between the gate and the drain of the PMOS transistor M10, the resistor Rb is connected between the drain of the PMOS transistor M10 and the emitter of the triode Q2, and the base and the collector of the triode Q2 are both connected with the ground potential GND; the emitter of the triode Q1 is connected with the drain of the PMOS tube M11, and the base and the collector are both connected with the ground potential GND;

the grid electrode of the NMOS tube M3 and the grid electrode of the NMOS tube M7 are both connected with the drain electrode of the PMOS tube M11, the grid electrode of the NMOS tube M8 and the grid electrode of the NMOS tube M4 are both connected with the drain electrode of the PMOS tube M10, the drain electrode of the NMOS tube M7 and the drain electrode of the NMOS tube M8 are both connected with the drain electrode of the PMOS tube M9, and the source electrode of the NMOS tube M7 and the source electrode of the NMOS tube M8 are both connected with the drain electrode of the NMOS tube M2;

the grid and the drain of the NMOS transistor M2 are both connected with the grid of the NMOS transistor M1, the source of the NMOS transistor M1 and the source of the NMOS transistor M2 are both connected with ground potential GND, and the source of the NMOS transistor M3 and the source of the NMOS transistor M4 are both connected with the drain of the NMOS transistor M1;

the drain electrode of the PMOS tube M5 is connected with the drain electrode of an NMOS tube M3, and the grid electrode of the PMOS tube M5 and the grid electrode of the PMOS tube M6 are both connected with the drain electrode of the PMOS tube M6; the drain electrode of the NMOS tube M4 is connected with the drain electrode of the PMOS tube M6.

4. The low-power consumption, low-voltage and low-temperature drift bandgap reference voltage source according to claim 3, wherein the reference voltage generating circuit comprises an NMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M15, a resistor R1, a resistor R2, a resistor R3 and a resistor R4, wherein,

the source electrode of the PMOS transistor M13, the source electrode of the PMOS transistor M14 and the source electrode of the PMOS transistor M15 are all connected with a power supply voltage VDD; the drain electrode of the PMOS pipe M15 is used as the output end of the reference voltage Vr; the grid electrode of the PMOS tube M15 is connected with the drain electrode of the PMOS tube M5;

the resistor R2, the resistor R3 and the resistor R4 are connected in series between the drain of the PMOS tube M15 and the ground potential GND; the drain electrode of the PMOS pipe M14 is connected between the resistor R3 and the resistor R4; the grid electrode of the PMOS transistor M14 and the grid electrode of the PMOS transistor M13 are both connected with the source electrode of the PMOS transistor M13; the source electrode of the NMOS transistor M12 is connected with the drain electrode of the PMOS transistor M13, and the gate electrode of the NMOS transistor M12 is connected with the emitter electrode of the triode Q1; the resistor R1 is connected between the drain of the NMOS transistor M12 and the ground potential GND.

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