CN114172499A - Reset circuit - Google Patents

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Publication number
CN114172499A
CN114172499A CN202111188944.2A CN202111188944A CN114172499A CN 114172499 A CN114172499 A CN 114172499A CN 202111188944 A CN202111188944 A CN 202111188944A CN 114172499 A CN114172499 A CN 114172499A
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circuit
tube
nmos
pmos
power supply
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许天辉
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Beijing Xin Yi Technology Co ltd
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Beijing Xin Yi Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption

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Abstract

The application provides a reset circuit, includes: the circuit comprises a starting circuit, a bias circuit, a reference voltage circuit, a power supply voltage sampling circuit and a comparator circuit, wherein the starting circuit is used for controlling the starting of the bias circuit and automatically closing the bias circuit after the bias circuit is successfully started; the bias circuit is used for generating voltage bias and providing the voltage bias for the reference voltage circuit, the power supply voltage sampling circuit and the comparator circuit; a reference voltage circuit for generating a reference voltage; the power supply voltage sampling circuit is used for detecting power supply voltage and outputting a power supply voltage sampling signal; and the comparator circuit is used for comparing the reference voltage generated by the reference voltage circuit with the power supply voltage sampling signal output by the power supply voltage sampling circuit and outputting a reset signal. The power supply power-on and abnormal power failure reset detection function is achieved, and meanwhile lower power consumption is consumed in the normal working range of the power supply voltage.

Description

Reset circuit
Technical Field
The application relates to the technical field of circuit structures, in particular to a reset circuit.
Background
In recent years, programmable logic devices such as a single chip microcomputer and the like are more and more widely applied in the fields of industrial automatic production, process control, intelligent instruments and meters and the like, the production efficiency, the control quality and the economic benefit are effectively improved, and any programmable logic device can execute an application program after reliable reset, so that the design of a reset circuit is very important. For example, the reset circuit is commonly used in an integrated circuit system to reset a register and initialize a digital-analog hybrid circuit during power-on or when power is low, so as to prevent the chip from operating in an abnormal state.
Disclosure of Invention
The application aims to provide a reset circuit.
According to an embodiment of the present application, there is provided a reset circuit including:
a start-up circuit, a bias circuit, a reference voltage circuit, a power supply voltage sampling circuit, a comparator circuit, wherein,
the starting circuit is used for controlling the starting of the biasing circuit and automatically closing the biasing circuit after the biasing circuit is successfully started;
the bias circuit is used for generating voltage bias and providing the voltage bias for the reference voltage circuit, the power supply voltage sampling circuit and the comparator circuit;
a reference voltage circuit for generating a reference voltage;
the power supply voltage sampling circuit is used for detecting power supply voltage and outputting a power supply voltage sampling signal;
and the comparator circuit is used for comparing the reference voltage generated by the reference voltage circuit with the power supply voltage sampling signal output by the power supply voltage sampling circuit and outputting a reset signal.
The technical scheme provided by the embodiment of the application can have the following beneficial effects:
by arranging the starting circuit, the biasing circuit, the reference voltage circuit, the power supply voltage sampling circuit and the comparator circuit, the reset detection function of the power supply during power-on and abnormal power-off is accurately realized, and meanwhile, lower power consumption is consumed in a normal working range of the power supply voltage.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a block diagram of a reset circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic circuit diagram of a start-up circuit and a bias circuit in a reset circuit according to an embodiment of the present disclosure;
fig. 3 is a circuit schematic diagram of a reference circuit in a reset circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic circuit diagram of a power supply voltage sampling circuit in a reset circuit according to an embodiment of the present disclosure;
fig. 5 is a circuit schematic diagram of a comparator circuit in a reset circuit according to an embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.
In recent years, programmable logic devices such as a single chip microcomputer and the like are more and more widely applied in the fields of industrial automatic production, process control, intelligent instruments and meters and the like, the production efficiency, the control quality and the economic benefit are effectively improved, and any programmable logic device can execute an application program after reliable reset, so that the design of a reset circuit is very important. For example, the reset circuit is commonly used in an integrated circuit system to reset a register and initialize a digital-analog hybrid circuit during power-on or when power is low, so as to prevent the chip from operating in an abnormal state.
To this end, the present application provides a reset circuit, and in particular, the reset circuit of the embodiments of the present application is described below with reference to the accompanying drawings.
Fig. 1 is a block diagram of a reset circuit according to an embodiment of the present disclosure, and as shown in fig. 1, the reset circuit may include a start circuit 110, a bias circuit 120, a reference voltage circuit 130, a power supply voltage sampling circuit 140, and a comparator circuit 150.
The start-up circuit 110 is used for controlling the start-up of the bias circuit and automatically turning off the bias circuit after the bias circuit is successfully started up.
And a bias circuit 120 for generating a voltage bias to provide the voltage bias to the reference voltage circuit, the power supply voltage sampling circuit and the comparator circuit.
And a reference voltage circuit 130 for generating a reference voltage.
Reference voltages can be used, among other things, in voltage regulators, analog-to-digital converters and digital-to-analog converters of power supply systems, as well as in many other measurement and control systems.
And a power supply voltage sampling circuit 140 for detecting the power supply voltage and outputting a power supply voltage sampling signal.
It should be noted that, in an implementation manner, the power supply voltage sampling circuit further includes a hysteresis structure, where the hysteresis structure is used to generate hysteresis when the reset signal is switched, so as to prevent the reset signal from jittering.
And a comparator circuit 150 for comparing the reference voltage generated by the reference voltage circuit with the power supply voltage sampling signal output by the power supply voltage sampling circuit and outputting a reset signal.
It should be noted that both the reference voltage generated by the reference voltage circuit and the power supply voltage sampling signal output by the power supply voltage sampling circuit have positive temperature coefficients.
It should be noted that, the specific structures of the starting circuit and the bias circuit are shown in fig. 2, and fig. 2 is a circuit schematic diagram of the starting circuit and the bias circuit, where the starting circuit includes a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor; the bias circuit comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a resistor. As an example, the first PMOS transistor may be a PMOS transistor MPS0, the second PMOS transistor may be a PMOS transistor MPS1, the first NMOS transistor may be an NMOS transistor MNS0, the third PMOS transistor may be a PMOS transistor MPB1, the fourth PMOS transistor may be a PMOS transistor MPB2, the fifth PMOS transistor may be a PMOS transistor MPB3, the second NMOS transistor may be an NMOS transistor MNB1, the third NMOS transistor may be an NMOS transistor MNB2, the fourth NMOS transistor may be an NMOS transistor MNB3, and the resistor may be a resistor R0.
That is, as shown in fig. 2, the start-up circuit 110 may include PMOS transistors MPS0, MPS1 and NMOS transistor MNS0 for ensuring normal start-up of the bias circuit 120 at power-up; the bias circuit 120 may include PMOS transistors MPB1, MPB2, MPB3, NMOS transistors MNB1, MNB2, MNB3, and a resistor R0, and is configured to generate a quiescent current, and form a gate bias voltage through the gate of the PMOS transistor MPB3 and the gate of the NMOS transistor MNB3, so as to provide a voltage bias for other modules.
As shown in fig. 2, the sources of the PMOS transistors MPS0, MPS1, MPB1, MPB2 and MPB3 are respectively connected to the power supply, and the source and the drain of the NMOS transistor MNS0 and the sources of the NMOS transistors MNB2 and MNB3 are both connected to the ground potential; the drain of the PMOS tube MPS0 is connected to the gate of the PMOS tube MPS1 and the gate of the NMOS tube MNS0 respectively, and the drain of the PMOS tube MPS1 is connected to the drain of the NMOS tube MN2, the gate of the NMOS tube MNB3 and the drain of the PMOS tube MPB2 respectively; the gates of the PMOS tubes MPB1, MPB2 and MPB3 are connected with the drain of the MPB3 and the drain of the NMOS tube MNB 3; the drain electrode of the PMOS tube MPB1 is connected with the drain electrode and the grid electrode of the NMOS tube MNB 1; the source electrode of the NMOS tube MNB1 is connected with one end of the resistor R0, and the other end of the resistor R0 is connected with the ground potential; PMOS tubes MPB1, MPB2 and MPB3 form a current mirror structure, NMOS tubes MNB1 and MNB2 form the current mirror structure, and a feedback loop is formed by NMOS tube MNB3 and PMOS tube MPB3, so that the current ratios of branches of the PMOS tubes MPB1, MPB2 and MPB3 are the same as the width-length ratios of the branches of the PMOS tubes MPB1, MPB2 and MPB 3.
For example, if the width-to-length ratios of the PMOS transistors MPB1, MPB2, and MPB3 are the same, and the width-to-length ratios of the NMOS transistors MNB2 and MNB3 are the same, IMNB1＝IMNB2-IMNB3＝I0，IMNB1And IMNB2The current branches MPB1 and MPB2 are respectively, and the sizes of NMOS tubes MNB1, MNB2 and MNB3 are reasonably set to make the NMOS tubes operate in a saturation region, so that it can be known that:
Figure RE-GDA0003488220130000031
wherein: kMNB1＝μnCox(W/L)MNB1，KMNB2＝μnCox(W/L)MNB2,μnIs the electron mobility of NMOS transistor, CoxFor MOS transistor grid unit area grid oxide capacitance (W/L)MNB1And (W/L)MNB2The width-length ratios of the NMOS tubes MNB1 and MNB2 are respectively;
then, it can be known that:
Figure RE-GDA0003488220130000032
as can be seen from equation (2), the current is a current independent of the power supply voltage, and by appropriately setting the sizes of the NMOS transistors MNB1, MNB2, and MNB3 and the resistance of the resistor R0, a desired bias current can be obtained, and finally, the desired bias current is mirrored to other modules through the NMOS transistor MNB3 and the MOS transistor MPB3 to provide bias voltages for the other modules.
When the power supply is powered on, the initial voltage of the gate of the NMOS transistor MNS0 is 0v, the PMOS transistor MPS1 is controlled to be started, the gate of the NMOS transistor MNB3 is charged through the PMOS transistor MPS1 until the MNB3 is started, and the gate potentials of the PMOS transistors MPB1, MPB2, MPB3 and MPS0 are pulled down to be started, so that the bias circuit is started; the MPS0 is turned on to charge the gates of NMOS transistor MNS0 and PMOS transistor MPS1 to high, and PMOS transistor MPS1 is finally turned off.
It should be noted that, in one implementation, the reference voltage circuit 130 may include N sub-reference voltage circuits; each sub-reference voltage circuit includes: a sixth PMOS tube, a fifth NMOS tube and a sixth NMOS tube; the connection relationship of each component in each sub-reference voltage circuit can be as follows: the grid electrode of the sixth PMOS tube is connected with the grid electrode of a fifth PMOS tube in the bias circuit, the source electrode of the sixth PMOS tube is connected with the power line, the drain electrode of the sixth PMOS tube is connected with the drain electrode and the grid electrode of a fifth NMOS tube and the grid electrode of the sixth NMOS tube, and the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube; the drain electrode of the sixth NMOS tube is used as the output of the sub-reference voltage circuit; wherein N is a positive integer.
In addition, in the present embodiment, the first-stage sub-reference voltage circuit is located at a first position among the N sub-reference voltage circuits, and a source of the sixth NMOS transistor in the first-stage sub-reference voltage circuit is connected to the ground potential; the source electrode of a sixth NMOS tube in the ith sub-reference voltage circuit is connected with the output of the (i + 1) th sub-reference voltage circuit; wherein 1< i is less than or equal to N.
For example, as shown in fig. 3, which is a schematic circuit diagram of the reference voltage circuit, it is assumed that the reference voltage circuit 130 is composed of N sub-reference voltage circuits 131 (N is a positive integer greater than or equal to 1), and includes N PMOS transistors and 2N NMOS transistors. The N PMOS tubes consist of PM1 and PM2.
As shown in fig. 3, the PMOS transistor PMi, the NMOS transistors NMiS0, and NMiS1 form the i-th sub-reference voltage circuit 131 (where i is greater than or equal to 1 and less than or equal to N, and is a positive integer, the same applies below); the connection method of the PMOS transistor and the NMOS transistor in the ith sub-reference voltage circuit 131 may be as follows: the grid electrode of the PMOS tube PMi is connected with the grid electrode of a PMOS tube MPB3 in the bias circuit, the source electrode of the PMOS tube PMi is connected with a power line, the drain electrode of the PMOS tube PMi is connected with the drain electrode and the grid electrode of an NMOS tube NMiS0 and the grid electrode of NMiS1, and the source electrode of the NMOS tube NMiS0 is connected with the drain electrode of NMiS 1; while the drain of NMiS1 serves as the output of the i-th stage sub-reference voltage circuit. If i > 1, the source of NMiS1 is connected to the output of i-1 stage sub-reference voltage circuit, and when i is equal to 1, NM1S1 is connected to ground; the sizes of the PMOS tube PMi and the NMOS tubes NMiS0 and NMiS1 are reasonably selected, so that the NMOS tubes NMiS0 and NMiS1 work in a subthreshold region, and the formula (3) can be obtained by a subthreshold region formula:
Figure RE-GDA0003488220130000041
in the formula (3), IbiasFor the branch current of PMi, I0Is a process-dependent current parameter, W0/L0And W1/L1Width to length ratio, V, of NMiS0 and NMiS1, respectivelyTIs a thermal voltage, VthnFor NMOS threshold voltage, VGS0 and VGS1 are gate-to-source voltage differences of NMiS0 and NMiS1, respectively, and VDS0 and VDS1 are drain voltage differences of NMiS0 and NMiS1, respectively; xinThe subthreshold slope factor of the NMOS transistor is a constant related to the process.
In addition, when VDS0And VDS1Greater than 3VTWhen, equation (3) can be ignored
Figure RE-GDA0003488220130000051
And
Figure RE-GDA0003488220130000052
then maleFormula (3) is simplified as:
Figure RE-GDA0003488220130000053
further obtaining:
VDS1＝VGS1-VVGS0≈ξnVT lnk1 (5)
wherein k is1＝(W0/L0)/(W1/L1)；
In summary, neglecting the influence of the sub-reference voltage circuit of the later stage on the preceding stage and the substrate bias effect, the final output reference voltage of the reference voltage circuit is:
Vptat≈nVDS1≈nξnVTlnk1 (6)。
furthermore, the NMOS of all sub-reference voltage circuits in the reference voltage circuit works in a sub-threshold region, and the static working current can be very low, so that the circuit structure can realize low power consumption design.
It should be noted that, in an implementation manner, a specific structure of the power supply voltage sampling circuit is shown in fig. 4, and fig. 4 is a circuit schematic diagram of the power supply voltage sampling circuit. The power supply voltage sampling circuit comprises a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a seventh NMOS tube, an eighth NMOS tube and a diode; wherein:
as an example, the seventh PMOS transistor may be a PMOS transistor PMT0, the eighth PMOS transistor may be a PMOS transistor PMT1, the ninth PMOS transistor may be a PMOS transistor PMT2, the seventh NMOS transistor may be an NMOS transistor NMT0, the eighth NMOS transistor may be an NMOS transistor NMT1, and the diode may be a diode D0.
As shown in fig. 4, the connection among the PMOS transistor, the NMOS transistor, and the diode in the power voltage sampling circuit is as follows: the source electrodes of the PMOS tubes PMT0 and PMT2 are connected with a power supply, the drain electrodes of the PMOS tubes PMT0 and PMT2 are connected with the source electrode of the PMT1 and the drain electrode of the diode D0, the grid electrode of the PMOS tube PMT0 is connected with the grid electrode and the drain electrode of the PMT1 and the drain electrode of the NMOS tube NMT0, the grid electrode of the PMOS tube PMT2 is connected with an output signal POR of the integral reset circuit, the grid electrodes of the NMOS tubes NMT0 and NMT1 are connected with the grid electrode of the NMOS tube MNB3 in the bias circuit, the source electrodes of the NMOS tubes NMT0 and NMT1 are connected with the ground potential, and the drain electrode of the NMT1 is connected with the negative end of the diode and is connected with the comparator circuit as the output of the power supply voltage sampling circuit.
It should be noted that, in an implementation manner, the NMOS tubes NMT0 and NMT1 are connected to the gate of the NMOS tube MNB3 in the bias circuit to form a current mirror structure, which provides current bias for the branches where the PMT1 and the D0 are located respectively; the PMOS tubes PMT0 and PMT1 operate in the subthreshold region, and as mentioned above, the voltage difference between the source and drain of PMT0 is:
VDSP＝VGSPMT0-VGSPMT1≈ξPVTlnk2 (7)
wherein k is2＝(WPMT1/LPMT1)/(WPMT0/LPMT0)，WPMT1/LPMT1And WPMT0/LPMT0Width-to-length ratio, ξ, of PMOS tubes PMT1 and PMT0pThe subthreshold slope factor of the PMOS transistor is a constant related to the process.
When POR is high, the Vsamp of the output voltage of the power supply voltage sampling circuit is Vsamp 1:
Vsamp1＝VDD-VDSP-Vpn≈VDD-ξPVTlnk2-Vpn (8)
wherein Vpn is the difference between the positive terminal and the negative terminal of the diode D0.
When POR is low, the power supply voltage sampling circuit outputs Vsamp — Vsamp 2.
It is noted that the diode PN junction voltage Vpn has a negative temperature coefficient, so both Vsamp1 and Vsamp2 have positive temperature coefficients; in addition, the quiescent current of the circuit of the power supply voltage sampling embodiment is limited by the currents of the NMOS transistors NMT0 and NMT1, the currents of the NMOS transistors NMT0 and NMT1 are generated by the voltage bias signals output by the bias circuit, the quiescent operating current of the power supply voltage sampling circuit cannot change along with the change of the power supply voltage, and the power supply voltage sampling circuit can still work in a constant low power consumption state when the working range of the power supply voltage is wide.
In one implementation, as shown in fig. 5, a circuit schematic of a comparator circuit; the output Vptat of the reference voltage circuit is compared with the output voltage Vsamp of the power supply voltage sampling circuit through a comparator, and finally a power supply reset signal POR is output; taking the above embodiment as an example, the working process of the reset circuit with high precision and low power consumption is as follows:
when the power supply is powered on, the starting circuit controls the starting of the biasing circuit along with the rise of the power supply voltage and provides bias for the reference voltage circuit, the power supply voltage sampling circuit and the comparator circuit; when the power supply is high enough, the reference voltage circuit is stabilized in advance and outputs a stable reference voltage VPTAT, and meanwhile, the power supply voltage sampling circuit outputs a voltage Vsamp which changes along with the power supply, wherein the Vsamp is Vsamp 1; the comparator circuit compares the reference voltage Vptat with the voltage Vsamp and outputs a reset signal POR;
when the power supply voltage reaches the power-on reset threshold VDD _ TH 1:
Vsamp1＝Vptat (10)
then, from equation (6) and equation (8):
VDD_TH1＝nξnVTlnk1+ξpVTlnk2+Vpn (11)
and due to the medium thermal voltage V in equation (11)TkT/q, which is positively correlated to temperature, while the diode PN junction voltage Vpn has a negative temperature coefficient, and the other parameters are independent of temperature; then n and k can be adjusted1、k2And the area of the diode, the power-on reset threshold VDD _ TH1 can be adjusted and has a lower temperature coefficient, so that the temperature dependence of the power-on reset threshold voltage is greatly reduced.
Further, when the power supply VDD > VDD _ TH1, the reset signal POR is released, the reset signal POR of this embodiment is pulled back to low level, and the reset signal controls the PMOS transistor PMT2 of the embodiment of the power supply voltage sampling circuit, so that the output of the power supply voltage sampling circuit Vsamp1 changes to Vsamp2, thereby generating the hysteresis voltage.
In another implementation, when the power supply is powered down, the power supply voltage sampling circuit outputs a voltage Vsamp that varies with the power supply, where Vsamp is Vsamp 2; the comparator circuit compares the reference voltage VPTAT with the voltage Vsamp2 and outputs a reset signal POR;
when the power supply voltage drops to reach the power down reset threshold VDD _ TH 2:
Vsamp2＝Vptat (12)
then from equation (6) one can derive:
VDD_TH2＝nξnVT lnk1+Vpn (13)
as described above, the thermal voltage V in the formula (12)TkT/q, which is positively correlated with temperature, and the diode PN junction voltage Vpn has a negative temperature coefficient, so that the temperature compensation between the two can greatly reduce the temperature correlation of the power-down reset threshold voltage VDD _ TH 2.
According to the reset circuit of the embodiment of the application, the high-precision low-power-consumption reset circuit ensures that the whole reset circuit is normally started when being powered on through the starting circuit, provides voltage bias for other modules through the low-power-consumption bias circuit, generates reference voltage through the low-power-consumption reference voltage circuit, accurately detects power voltage through the low-power-consumption power voltage sampling circuit and outputs a power voltage sampling signal; comparing the reference voltage output by the reference voltage circuit with the power supply voltage sampling signal through a comparator circuit, and finally outputting a reset signal; furthermore, the reference voltage generated by the reference voltage circuit has a positive temperature coefficient, the power supply voltage sampling signal output by the power supply voltage sampling circuit also has a positive temperature coefficient, and the temperature coefficients of the reference voltage and the power supply voltage sampling signal are offset, so that the correlation between the power supply voltage reset threshold and the temperature is greatly reduced; furthermore, the reset signal feedback controls the power supply voltage sampling circuit to form a hysteresis effect, so that a power-on reset threshold value and a power-off reset threshold value form a hysteresis interval, and the stability of the reset signal is ensured; in addition, the static working current of each module of the reset circuit with low power consumption and high stability is very low and is irrelevant to a power supply, so that a low-power-consumption design scheme is effectively realized.

Claims (10)

1. A reset circuit, comprising: a start-up circuit, a bias circuit, a reference voltage circuit, a power supply voltage sampling circuit, a comparator circuit, wherein,
the starting circuit is used for controlling the starting of the bias circuit and automatically closing the bias circuit after the bias circuit is successfully started;
the bias circuit is used for generating voltage bias and providing the voltage bias for the reference voltage circuit, the power supply voltage sampling circuit and the comparator circuit;
the reference voltage circuit is used for generating a reference voltage;
the power supply voltage sampling circuit is used for detecting power supply voltage and outputting a power supply voltage sampling signal;
and the comparator circuit is used for comparing the reference voltage generated by the reference voltage circuit with the power supply voltage sampling signal output by the power supply voltage sampling circuit and outputting a reset signal.
2. The reset circuit of claim 1, wherein the start-up circuit comprises a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor; the bias circuit comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a resistor; wherein the content of the first and second substances,
the source electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are respectively connected with a power supply; the source electrode and the drain electrode of the first NMOS tube, the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are connected with the ground potential; the drain electrode of the first PMOS tube is respectively connected with the gate electrode of the second PMOS tube and the gate electrode of the first NMOS tube, and the drain electrode of the second PMOS tube is respectively connected with the drain electrode of the third NMOS tube, the gate electrode of the fourth NMOS tube and the drain electrode of the fourth PMOS tube; the grid electrodes of the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are connected with the drain electrode of the fifth PMOS tube and the drain electrode of the fourth NMOS tube; the drain electrode of the third PMOS tube is connected with the drain electrode and the grid electrode of the second NMOS tube; the source electrode of the second NMOS tube is connected with one end of the resistor, and the other end of the resistor is connected with the ground potential; the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube form a current mirror structure, the second NMOS tube and the third NMOS tube form a current mirror structure, and a feedback loop is formed by the fourth NMOS tube and the fifth PMOS tube.
3. The reset circuit of claim 2, wherein the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor all operate in a saturation region.
4. The reset circuit of claim 2, wherein the reference voltage circuit comprises N sub-reference voltage circuits; each of the sub-reference voltage circuits includes: a sixth PMOS tube, a fifth NMOS tube and a sixth NMOS tube; wherein the content of the first and second substances,
the grid electrode of the sixth PMOS tube is connected with the grid electrode of the fifth PMOS tube in the bias circuit, the source electrode of the sixth PMOS tube is connected with a power line, the drain electrode of the sixth PMOS tube is connected with the drain electrode and the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube, and the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube; the drain electrode of the sixth NMOS tube is used as the output of the sub-reference voltage circuit; wherein N is a positive integer.
5. The reset circuit of claim 4, wherein the source of the sixth NMOS transistor of the first stage of sub-reference voltage circuit is connected to ground potential; the source electrode of a sixth NMOS tube in the ith-level sub-reference voltage circuit is connected with the output of the (i + 1) -level sub-reference voltage circuit; wherein 1< i is less than or equal to N.
6. The reset circuit of claim 4 or 5, wherein the fifth NMOS transistor and the sixth NMOS transistor operate in a sub-threshold region.
7. The reset circuit of claim 2, wherein the power voltage sampling circuit comprises a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a diode; wherein the content of the first and second substances,
the source electrodes of the seventh PMOS tube and the ninth PMOS tube are connected with a power supply, the drain electrodes of the seventh PMOS tube and the ninth PMOS tube are connected with the source electrode of the eighth PMOS tube and the drain electrode of the diode, the grid electrode of the seventh PMOS tube is connected with the grid electrode and the drain electrode of the eighth PMOS tube and the drain electrode of the seventh NMOS tube, the grid electrode of the ninth PMOS tube is connected with an output signal of the reset circuit, the grid electrodes of the seventh NMOS tube and the eighth NMOS tube are connected with the grid electrode of the fourth NMOS tube in the bias circuit, the source electrodes of the seventh NMOS tube and the eighth NMOS tube are connected with the ground potential, and the drain electrode of the eighth NMOS tube is connected with the negative end of the diode and is used as the output of the power supply voltage sampling circuit to be connected with the comparator circuit.
8. The reset circuit of claim 7, wherein the seventh NMOS transistor and the eighth NMOS transistor are connected to the gate of the fourth NMOS transistor in the bias circuit to form a current mirror structure, and the current mirror structure provides current bias for the eighth PMOS transistor and the branch where the diode is located, respectively.
9. The reset circuit of claim 1, wherein the supply voltage sampling circuit further comprises a hysteresis structure; wherein the content of the first and second substances,
the hysteresis structure is used for generating hysteresis when the reset signal is switched.
10. The reset circuit of claim 1, wherein the reference voltage generated by the reference voltage circuit and the power supply voltage sampling signal output by the power supply voltage sampling circuit both have positive temperature coefficients.
CN202111188944.2A 2021-10-12 2021-10-12 Reset circuit Pending CN114172499A (en)

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* Cited by examiner, † Cited by third party
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CN116505925A (en) * 2023-03-21 2023-07-28 湖南芯易德科技有限公司 Low-power-consumption power-on and power-off reset circuit with temperature compensation function and reset device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116505925A (en) * 2023-03-21 2023-07-28 湖南芯易德科技有限公司 Low-power-consumption power-on and power-off reset circuit with temperature compensation function and reset device
CN116505925B (en) * 2023-03-21 2024-02-02 湖南芯易德科技有限公司 Low-power-consumption power-on and power-off reset circuit with temperature compensation function and reset device

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