CN116505925A - Low-power-consumption power-on and power-off reset circuit with temperature compensation function and reset device - Google Patents

Low-power-consumption power-on and power-off reset circuit with temperature compensation function and reset device Download PDF

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Publication number
CN116505925A
CN116505925A CN202310278635.7A CN202310278635A CN116505925A CN 116505925 A CN116505925 A CN 116505925A CN 202310278635 A CN202310278635 A CN 202310278635A CN 116505925 A CN116505925 A CN 116505925A
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power
circuit
reset
pmos tube
tube
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CN116505925B (en
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陈质冉
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Hunan Xinyide Technology Co ltd
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Hunan Xinyide Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention relates to the technical field of chip reset, and discloses a low-power-consumption power-on and power-off reset circuit with temperature compensation and a reset device, wherein the circuit comprises a power line, a starting circuit, a positive temperature current circuit, a reset circuit, a grounding wire and a reset signal output interface; the starting circuit, the positive temperature current circuit, the reset circuit and the reset signal output interface are sequentially connected, and the starting circuit is connected with the reset circuit; the starting circuit is used for starting the low-power-consumption power-on and power-off reset circuit with temperature compensation, the positive temperature current circuit is used for generating positive temperature coefficient current based on the started low-power-consumption power-on and power-off reset circuit with temperature compensation, the reset circuit is used for generating negative temperature coefficient voltage, generating turnover voltage irrelevant to temperature based on the positive temperature coefficient current and the negative temperature coefficient voltage, and outputting a reset signal based on the turnover voltage. The invention improves the resetting accuracy of the resetting circuit.

Description

Low-power-consumption power-on and power-off reset circuit with temperature compensation function and reset device
Technical Field
The invention relates to the technical field of chip reset, in particular to a low-power-consumption power-on and power-off reset circuit with temperature compensation and a reset device.
Background
With the rapid development of chip technology, various chips are increasingly used in various fields, and meanwhile, the reset function of the chips is also increasingly emphasized.
The conventional reset circuit is realized based on an RC charging network, the resistor in the integrated circuit is usually realized by a PMOS tube with a long channel, and the capacitor is usually realized by a MOS capacitor. Or the voltage dividing signal of the power supply voltage is input into the amplifier to realize the monitoring of the power supply voltage. The temperature characteristic of the divided signal largely influences the temperature characteristic of the trigger point voltage. The conventional reset circuit has no temperature compensation function, and the potential of an output node of the conventional reset circuit linearly drops along with the increase of the working temperature of the MOS tube, so that the output trigger potential of the conventional reset circuit also linearly drops along with the increase of the temperature, and the power-on reset working state is unstable. The traditional reset circuit can not achieve the effects of both power-on and power-off speed of power supply voltage, chip area and power consumption of the reset circuit. The reset circuit has great defects, and has the problem that the reset voltage has large voltage value change along with the process and the temperature, namely, the reset accuracy of the reset circuit is not high because the reset voltage can be changed along with the process and the temperature and the rising or falling speed of the power supply voltage.
Disclosure of Invention
The invention mainly aims to provide a low-power-consumption power-on and power-off reset circuit with temperature compensation and a reset device, and aims to improve the reset accuracy of the reset circuit.
In order to achieve the above purpose, the invention provides a low-power-consumption power-on and power-off reset circuit with temperature compensation, which comprises a power line, a starting circuit, a positive temperature current circuit, a reset circuit, a grounding line and a reset signal output interface;
the starting circuit, the positive temperature current circuit and the reset circuit are respectively connected with the power line and the ground line, the starting circuit, the positive temperature current circuit, the reset circuit and the reset signal output interface are sequentially connected, and the starting circuit is connected with the reset circuit;
the starting circuit is used for starting the low-power-consumption power-on and power-off reset circuit with temperature compensation, the positive temperature current circuit is used for generating positive temperature coefficient current based on the started low-power-consumption power-on and power-off reset circuit with temperature compensation, the reset circuit is used for generating negative temperature coefficient voltage based on the started low-power-consumption power-on and power-off reset circuit with temperature compensation, generating turnover voltage irrelevant to temperature based on the positive temperature coefficient current and the negative temperature coefficient voltage, and outputting a reset signal based on the turnover voltage.
Optionally, the starting circuit includes a third PMOS transistor, a fourth PMOS transistor and a fourth NMOS transistor;
the source electrode of the third PMOS tube is connected with the power line, the grid electrode of the third PMOS tube is connected with the positive temperature current circuit, the drain electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and the grid electrode of the fourth NMOS tube, the grid electrode of the fourth PMOS tube is connected with the reset circuit, the source electrode of the fourth PMOS tube is connected with the power line, the drain electrode of the fourth PMOS tube is connected with the positive temperature current circuit, and the source electrode and the drain electrode of the fourth NMOS tube are connected with the ground line.
Optionally, the positive temperature current circuit comprises a first control circuit and a second control circuit, wherein the first control circuit comprises a fifth PMOS tube, a sixth PMOS tube, a fifth NMOS tube and a sixth NMOS tube;
the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected with the power line, the grid electrode of the sixth PMOS tube is respectively connected with the drain electrode of the sixth PMOS tube, the grid electrode of the fifth PMOS tube, the reset circuit and the grid electrode of the third PMOS tube, the drain electrode of the fifth PMOS tube is sequentially connected with the grid electrode of the fifth NMOS tube and the drain electrode of the fifth NMOS tube, the grid electrode of the fifth NMOS tube is respectively connected with the drain electrode of the fourth PMOS tube, the reset circuit and the grid electrode of the sixth NMOS tube, the drain electrode of the sixth NMOS tube is connected with the drain electrode of the sixth PMOS tube, and the second control circuit is connected with the source electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube.
Optionally, the second control circuit includes a first transistor, a second transistor and a first resistor;
the emitter of the first transistor is connected with the source electrode of the fifth NMOS tube, the collector and the base of the first transistor are connected with the ground wire, the first end of the first resistor is connected with the source electrode of the sixth NMOS tube, the second end of the first resistor is connected with the emitter of the second transistor, the collector and the base of the second transistor are connected with the ground wire, and the first transistor and the second transistor comprise PNP transistors.
Optionally, the calculation formula of the positive temperature coefficient current is: i1 = (Vbe 1-Vbe 2)/r 1, where Vbe1 is the on voltage of the first transistor, vbe2 is the on voltage of the second transistor, and r1 is the resistance value of the first resistor.
Optionally, the reset circuit includes a third control circuit, a fourth control circuit, and an output circuit;
the third control circuit comprises a first PMOS tube, a second PMOS tube, a seventh PMOS tube and an eighth PMOS tube, wherein the grid electrode of the first PMOS tube is connected with the grid electrode of the fourth PMOS tube, the power line is connected with the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the grid electrode of the seventh PMOS tube, the source electrode of the seventh PMOS tube and the source electrode of the eighth PMOS tube, the grid electrode of the second PMOS tube is connected with the grid electrode of the sixth PMOS tube, the drain electrode of the second PMOS tube is respectively connected with the grid electrode of the eighth PMOS tube, the drain electrode of the first PMOS tube and the fourth control circuit, and the drain electrode of the seventh PMOS tube is respectively connected with the fourth control circuit and the output circuit after being connected with the drain electrode of the eighth PMOS tube.
Optionally, the fourth control circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a seventh NMOS transistor;
the grounding wire is connected with the source electrode of the first NMOS tube, the source electrode of the second NMOS tube and the source electrode of the seventh NMOS tube, the grid electrode and the drain electrode of the seventh NMOS tube are connected with the drain electrode of the second PMOS tube, the grid electrode of the first NMOS tube is respectively connected with the grid electrode of the second NMOS tube and the grid electrode of the fifth NMOS tube, the drain electrode of the first NMOS tube is connected with the drain electrode of the eighth PMOS tube, the drain electrode of the second NMOS tube is connected with the source electrode of the third NMOS tube, the drain electrode of the third NMOS tube is connected with the drain electrode of the eighth PMOS tube, and the grid electrode of the third NMOS tube is connected with the output circuit.
Optionally, the output circuit includes a first inverter and a second inverter;
the input end of the first inverter is connected with the drain electrode of the eighth PMOS tube, the output end of the first inverter is respectively connected with the grid electrode of the third NMOS tube and the input end of the second inverter, and the output end of the second inverter is connected with the reset signal output interface.
Optionally, the width-to-length ratio of the third PMOS transistor in the starting circuit is smaller than the width-to-length ratio of the sixth PMOS transistor in the positive temperature current circuit, the width-to-length ratio of the fifth PMOS transistor in the positive temperature current circuit is equal to the width-to-length ratio of the sixth PMOS transistor in the positive temperature current circuit, and the width-to-length ratio of the fifth NMOS transistor in the positive temperature current circuit is equal to the width-to-length ratio of the sixth NMOS transistor in the positive temperature current circuit.
In addition, in order to achieve the above purpose, the invention also provides a reset device, which is used for loading the low-power-consumption power-on-off reset circuit with temperature compensation, the reset device comprises a power switch and a circuit board, the power switch is connected with the low-power-consumption power-on-off reset circuit with temperature compensation, and the circuit board is provided with the low-power-consumption power-on-off reset circuit with temperature compensation and the power switch.
The invention provides a low-power consumption power-on and power-off reset circuit with temperature compensation, which comprises a power line, a starting circuit, a positive temperature current circuit, a reset circuit, a grounding wire and a reset signal output interface, wherein the power line is connected with the starting circuit; the starting circuit, the positive temperature current circuit and the reset circuit are respectively connected with the power line and the ground line, the starting circuit, the positive temperature current circuit, the reset circuit and the reset signal output interface are sequentially connected, and the starting circuit is connected with the reset circuit; the starting circuit is used for starting the low-power-consumption power-on and power-off reset circuit with temperature compensation, the positive temperature current circuit is used for generating positive temperature coefficient current based on the started low-power-consumption power-on and power-off reset circuit with temperature compensation, the reset circuit is used for generating negative temperature coefficient voltage based on the started low-power-consumption power-on and power-off reset circuit with temperature compensation, generating turnover voltage irrelevant to temperature based on the positive temperature coefficient current and the negative temperature coefficient voltage, and outputting a reset signal based on the turnover voltage.
The positive temperature coefficient current is generated by the positive temperature current circuit based on the started low-power-consumption power-on and power-off reset circuit with temperature compensation, the temperature-independent turnover voltage is generated by the reset circuit based on the positive temperature coefficient current and the negative temperature coefficient voltage after the circuit is started, and finally a temperature-independent reset signal is output. Because the positive temperature coefficient current is positive temperature coefficient, the phenomenon that the voltage value is greatly changed along with the process and the temperature in the reset voltage in the prior art is avoided, and the reset signal irrelevant to the temperature is output through the positive temperature coefficient current of the negative temperature coefficient voltage and the positive temperature coefficient current, so that the stability of the reset voltage can be ensured, and the reset accuracy of the reset circuit is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a low power consumption power-on-off reset circuit with temperature compensation according to the present invention;
FIG. 2 is a schematic diagram of another structural framework connection of the low power up and down reset circuit with temperature compensation according to the present invention;
FIG. 3 is a schematic diagram of a first circuit connection of a low power up and down reset circuit with temperature compensation according to the present invention;
FIG. 4 is a schematic diagram of a second circuit connection of the low power up and down reset circuit with temperature compensation according to the present invention;
fig. 5 is a schematic diagram of a resetting device according to the present invention.
Reference numerals illustrate:
the achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are included in the embodiments of the present invention, the directional indications are merely used to explain the relative positional relationship, movement conditions, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
For clarity and conciseness of the following description of the embodiments, a brief description of a low-power-consumption power-on-power-off reset circuit with temperature compensation is given first:
the power-on reset circuit is widely applied to various chips and systems, and because the power supply voltage is in an abnormal state or abnormal logic overturning occurs to the components or logic gates of the circuit when the power supply voltage does not reach the normal working voltage in the process of powering on the chips or the systems, the logic of the whole circuit is disordered, so that the system cannot start to work normally. Thus ensuring proper start-up of the entire circuit power-up process by the power-on reset circuit. The power-on reset circuit is characterized in that the voltage suddenly drops in the operation process of the chip, and a plurality of uncertain phenomena can occur to the chip at the moment, so that the chip needs to be reset at the moment to be in a certain state, and unexpected results caused by misoperation are avoided. The power-on or power-off reset circuit keeps outputting an effective reset level (low or high level) all the time in the power-on or power-off process of the power supply until the reset signal is turned over (invalid reset level) after the power supply voltage rises or falls to a certain normal working voltage specified by the system, and the power-on or power-off reset process is completed. The power supply voltage values when the reset signal is turned over are respectively called a power-on reset voltage and a power-off reset voltage, and the power-on reset voltage is generally higher than the power-off reset voltage. The reset voltage of the power-on reset circuit integrated in the chip has great changes along with the process, the temperature and the voltage; the fast power-up and the slow power-up cannot be simultaneously realized, and the power consumption is generally larger or the area is larger. The existing power-on reset circuit generally only has power-on reset and does not have a power-off (power-off) reset function. Taking the example that the reset voltage varies greatly with the process, the temperature and the voltage as an example, assuming that the reset turnover voltage of the existing chip is 1.7V, the power supply voltage is 1.8V at the lowest when the chip is actually applied, and the reset turnover voltage of the chip exceeds the power supply voltage by 1.8V due to the influence of the temperature and the process, so that the chip is always in a reset state and cannot be separated from reset to enter a normal working state; the reset flip voltage of the chip is lower than the voltage of the chip capable of working normally due to temperature and process influence, for example, the reset flip voltage is only 1.2V, so that the chip does not reach the working state and is reset, and the reset effect cannot be achieved; and the same reset circuit can not realize quick power up and power down and slow power up and power down, similar reset failure can occur under different power up and power down speeds, and further, the problem that larger power consumption or larger area is needed for achieving good power up and power down performance is solved. Based on the problems, the invention designs the low-power-consumption power-on and power-off reset circuit with temperature compensation, has high power supply rejection ratio, and the reset voltage does not change greatly with temperature, voltage and process, so that the anti-interference capability of the chip is improved, the voltage application range of the circuit is improved, and particularly, the lowest application voltage of the circuit is improved, so that the chip has wider application range; meanwhile, the limitation of the chip on the power-on speed in use is solved, and the application requirement of an external circuit is reduced; the circuit is low in power consumption and simple, the cost of the chip is reduced, and the circuit meets the requirement of energy-saving application. The anti-interference capability of the chip is improved through the circuit, so that the chip works more stably and reliably, the voltage application range of the circuit is improved, and particularly, the lowest application voltage of the circuit is improved, so that the chip has a wider application range; the limitation of the power-on speed when the chip is used is solved, and the application requirement of an external circuit is reduced; the circuit is low in power consumption and simple, the cost of the chip is reduced, and the circuit meets the requirement of energy-saving application.
The scheme provides a low-power-consumption power-on and power-off reset circuit with temperature compensation, which comprises a power line, a starting circuit, a positive temperature current circuit, a reset circuit, a grounding wire and a reset signal output interface; the starting circuit, the positive temperature current circuit and the reset circuit are respectively connected with the power line and the ground line, the starting circuit, the positive temperature current circuit, the reset circuit and the reset signal output interface are sequentially connected, and the starting circuit is connected with the reset circuit; the starting circuit is used for starting the low-power-consumption power-on and power-off reset circuit with temperature compensation, the positive temperature current circuit is used for generating positive temperature coefficient current based on the started low-power-consumption power-on and power-off reset circuit with temperature compensation, the reset circuit is used for generating negative temperature coefficient voltage based on the started low-power-consumption power-on and power-off reset circuit with temperature compensation, generating turnover voltage irrelevant to temperature based on the positive temperature coefficient current and the negative temperature coefficient voltage, and outputting a reset signal based on the turnover voltage. The reset signal is output through the negative temperature coefficient voltage and the positive temperature coefficient current of the positive temperature coefficient, so that the phenomenon that the reset overturning voltage has large voltage value change along with the process and the temperature is avoided, the stability of the reset overturning voltage can be further ensured, and the reset accuracy of the reset circuit is improved.
The invention provides a low-power-consumption power-on and power-off reset circuit with temperature compensation.
In an embodiment of the present invention, as shown in fig. 1, fig. 1 is a schematic diagram of a structural framework of a low-power-consumption power-on-off reset circuit with temperature compensation, where the low-power-on-off reset circuit with temperature compensation includes a power line VDD, a start-up circuit 10, a positive temperature current circuit 20, a reset circuit 30, a ground line GND and a reset signal output interface 40;
the start-up circuit 10, the positive temperature current circuit 20 and the reset circuit 30 are respectively connected with the power line VDD and the ground line GND, the start-up circuit 10, the positive temperature current circuit 20, the reset circuit 30 and the reset signal output interface 40 are sequentially connected, and the start-up circuit 10 is connected with the reset circuit 30;
the starting circuit 10 is configured to start the low power consumption power-on/power-off reset circuit 100 with temperature compensation, the positive temperature current circuit 20 is configured to generate a positive temperature coefficient current I1 based on the started low power consumption power-on/power-off reset circuit 100 with temperature compensation, the reset circuit 30 is configured to generate a negative temperature coefficient voltage Vthn based on the started low power consumption power-on/power-off reset circuit 100 with temperature compensation, and generate a temperature-independent flip voltage based on the positive temperature coefficient current I1 and the negative temperature coefficient voltage Vthn, and output a reset signal RST based on the flip voltage.
In this embodiment, by the above circuit connection manner, the positive temperature coefficient current circuit 20 is utilized to generate a positive temperature coefficient current after the low power consumption power-on and power-off reset circuit 100 with temperature compensation is turned on, and the reset circuit 30 generates a negative temperature coefficient voltage Vthn to generate a temperature independent reference voltage VREF together, so that output control is performed through the reference voltage VREF and the MOS transistor of the reset circuit 30 (see the specific control flow of the whole circuit described below), the positive temperature coefficient current I1 refers to the first current in fig. 3, the second current refers to the second current in fig. 3, the negative temperature coefficient voltage refers to Vthn, the temperature independent (zero temperature coefficient) voltage (reference voltage) VREF refers to the zero temperature coefficient voltage, so that the reset signal output by the circuit is independent of temperature and process, the reset signal refers to the output level signal, and the function of resetting the chip is further realized, and the reset accuracy of the reset circuit is further improved through the output reset signal independent of temperature and process.
Further, in yet another embodiment of the low power consumption power up and down reset circuit with temperature compensation in the present application, referring to fig. 2, fig. 2 is a schematic diagram of still another structural framework connection of the low power consumption power up and down reset circuit with temperature compensation. The circuit is finely divided into each part, and further, the components and connection relation of each part are further described according to the division of each part. Referring to fig. 3, fig. 3 is a schematic diagram of a first circuit connection of a low-power-on/off reset circuit with temperature compensation, and the start-up circuit 10 includes a third PMOS tube PM3, a fourth PMOS tube PM4, and a fourth NMOS tube NM4.
The source electrode of the third PMOS tube PM3 is connected to the power line VDD, the gate electrode of the third PMOS tube PM3 is connected to the positive temperature current circuit 20, the drain electrode of the third PMOS tube PM3 is connected to the gate electrode of the fourth PMOS tube PM4 and the gate electrode of the fourth NMOS tube NM4, the gate electrode of the fourth PMOS tube PM4 is connected to the reset circuit 30, the source electrode of the fourth PMOS tube PM4 is connected to the power line VDD, the drain electrode of the fourth PMOS tube PM4 is connected to the positive temperature current circuit 20, and the source electrode and the drain electrode of the fourth NMOS tube NM4 are connected to the ground line GND.
In this embodiment, the starting circuit 10 controls the whole circuit to be turned on by the voltage at the point a in the figure and generates a third current on the line of the third PMOS tube PM3, the PM3 in the starting circuit 10 mirrors the current of the PM6 in the positive temperature current circuit 20, the PM3 current is the third current, and the NM4 is the NMOS capacitor. The drain electrode of PM3 is connected with the grid electrodes of PM4, PM1 and NM4, the connection point is point A, when the power supply voltage VDD rises, because the voltage at two ends of the capacitor does not suddenly change, and the third current is not generated yet, the point A voltage is zero, as the VDD rises, when the difference value between the point A voltage and the VDD is smaller than the threshold voltage Vth of PM4 and PM1, PM4 and PM1 are gradually conducted, the voltage at the point C and VREF gradually rises along with the change of the VDD, NM5, NM6, NM1 and NM2 are conducted, NM6 conduction pulls down the grid voltages of PM6, PM5, PM3 and PM2, PM6, PM5, PM3 and PM2 are conducted, so that the first, second and third currents generate, the third current charges NMOS capacitor NM4, the point A voltage gradually rises and finally equals VDD, so that the PM4 pipe and the PM1 pipe are closed, the starting circuit is started, and finally the whole circuit normally works.
Further, the positive temperature current circuit 20 includes a first control circuit 21 and a second control circuit 22, where the first control circuit 21 includes a fifth PMOS pipe PM5, a sixth PMOS pipe PM6, a fifth NMOS pipe NM5 and a sixth NMOS pipe NM6;
the source of the fifth PMOS PM5 and the source of the sixth PMOS PM6 are connected to the power line VDD, the gate of the sixth PMOS PM6 is connected to the drain of the sixth PMOS PM6, the gate of the fifth PMOS PM5, the reset circuit 30, and the gate of the third PMOS PM3, the drain of the fifth PMOS PM5 is connected to the gate of the fifth NMOS NM5 and the drain of the fifth NMOS NM5 in sequence, the gate of the fifth NMOS NM5 is connected to the drain of the fourth PMOS PM4, the reset circuit 30, and the gate of the sixth NMOS NM6, the drain of the sixth NMOS NM6 is connected to the drain of the sixth PMOS PM6, and the second control circuit 22 is connected to the source of the fifth NMOS NM5 and the source of the sixth NMOS NM 6.
Specifically, the second control circuit 22 includes a first transistor Q1, a second transistor Q2, and a first resistor R1;
the emitter of the first transistor Q1 is connected with the source of the fifth NMOS transistor NM5, the collector and the base of the first transistor Q1 are connected with the ground line GND, the first end of the first resistor R1 is connected with the source of the sixth NMOS transistor NM6, the second end of the first resistor R1 is connected with the emitter of the second transistor Q2, the collector and the base of the second transistor Q2 are connected with the ground line GND, and the first transistor Q1 and the second transistor Q2 include PNP transistors.
Specifically, the calculation formula of the positive temperature coefficient current is as follows: i1 = (Vbe 1-Vbe 2)/R1, wherein Vbe1 is the on voltage of the first transistor Q1, vbe2 is the on voltage of the second transistor Q2, and R1 is the resistance value of the first resistor R1.
In this embodiment, the positive temperature current circuit 20 in the whole circuit has degeneracy points, the circuit 10 needs to be started to break away from the degeneracy points, the positive temperature current circuit 20 turns on the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 through the voltage of the point C, and then turns on the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 and generates the positive temperature coefficient current I1 by pulling down the drain terminal potential of the sixth NMOS transistor NM6, wherein the calculation formula of the positive temperature coefficient current I1 is as above, and thus the positive temperature coefficient current I1 of the positive temperature coefficient generated by the positive temperature current circuit 20 is realized. When designing a triode, the area ratio of Q1 to Q2 is greater than 1:2 (the number of tubes of Q1 and Q2 are integers) the recommended ratio is 1:4, other ratios meeting the requirements are also possible. The ptc-I1 may be generated by ptc-I circuit 20, ptc-I1= (Vbe 1-Vbe 2)/r1=avbe/r1=v T * lnn/r1, where n is the area ratio of Q2 to Q1, V T The positive temperature coefficient current I1 is a positive temperature coefficient, and increases with increasing temperature.
Further, the reset circuit 30 includes a third control circuit 31, a fourth control circuit 32, and an output circuit 33, where the third control circuit includes a first PMOS tube PM1, a second PMOS tube PM2, a seventh PMOS tube PM7, and an eighth PMOS tube PM8;
the grid of the first PMOS pipe PM1 is connected to the grid of the fourth PMOS pipe PM4, the power line VDD is connected to the source of the first PMOS pipe PM1, the source of the second PMOS pipe PM2, the grid of the seventh PMOS pipe PM7, the source of the seventh PMOS pipe PM7, and the source of the eighth PMOS pipe PM8, the grid of the second PMOS pipe PM2 is connected to the grid of the sixth PMOS pipe PM6, the drain of the second PMOS pipe PM2 is connected to the grid of the eighth PMOS pipe PM8, the drain of the first PMOS pipe PM1, and the fourth control circuit 32, and the drain of the seventh PMOS pipe PM7 is connected to the drain of the eighth PMOS pipe PM8, and then is connected to the fourth control circuit 32 and the output circuit 33.
Specifically, the fourth control circuit 32 includes a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, and a seventh NMOS transistor NM7;
The ground line GND is connected to the source of the first NMOS transistor NM1, the source of the second NMOS transistor NM2, and the source of the seventh NMOS transistor NM7, the gate and the drain of the seventh NMOS transistor NM7 are connected to the drain of the second PMOS transistor PM2, the gate of the first NMOS transistor NM1 is connected to the gate of the second NMOS transistor NM2 and the gate of the fifth NMOS transistor NM5, the drain of the first NMOS transistor NM1 is connected to the drain of the eighth PMOS transistor NM8, the drain of the second NMOS transistor NM2 is connected to the source of the third NMOS transistor NM3, the drain of the third NMOS transistor NM3 is connected to the drain of the eighth PMOS transistor PM8, and the gate of the third NMOS transistor NM3 is connected to the output circuit 33.
Specifically, the output circuit 33 includes a first inverter INV1 and a second inverter IN2;
the input end of the first inverter INV1 is connected with the drain electrode of the eighth PMOS tube PM8, the output end of the first inverter INV1 is connected with the gate electrode of the third NMOS tube NM3 and the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected with the reset signal output interface 40.
In this embodiment, the first inverter INV1 and the second inverter INV2 may be schmitt inverters or common inverters, which is different in that the accuracy of the phase inversion of the schmitt inverters due to the working principle thereof is higher. Based on the fact that the seventh NMOS transistor NM7 is connected in a diode connection manner, that is, gate-drain connections are connected together, the voltage at the VREF point is equal to the gate-source voltage VGSn of NM7, when the circuit is operating normally, NM7 is in a saturated state, the current IDS of NM7 is equal to the second current, if the aspect ratio of PM2 to PM6 is m, the second current i2=mχi1, and ids=i2=mχi1 can be known
IDS=(1/2)μ n C ox （W/L）*（VGSn-Vthn） ² （1）
I2=m*I1=m*（Vbe1-Vbe2）/r1=m*ΔVbe/r1=m*V T *lnn/r1（2）
From the equation (1) and the equation (2)
m*V T *lnn/r1=(1/2)μ n C ox （W/L）*（VGSn-Vthn） ² （3）
Wherein, (VGSn-Vthn) is overdrive voltage, vthn is NM7 on voltage, (1/2) mu n C ox (W/L) is a conductive factor, mu n For carrier mobility, C ox The unit gate capacitance is the W/L ratio of the width to the length of the MOS tube. Based on the formula (3)
（4）
（5）
Threshold voltage Vthn of VREF expression (5) NM7 is a negative temperature coefficient, VREF expression (5)The VREF is a positive temperature coefficient, and the value of VREF can be set to be zero temperature coefficient through reasonable design.
The reset flip voltage of the output reset signal of the whole circuit (the whole circuit in the embodiment refers to a low-power-consumption power-on and power-off reset circuit with temperature compensation) is controlled by the reference voltage VREF, so that the reset accuracy of the chip can be controlled by the reset voltage.
Further, the width-to-length ratio of the third PMOS PM3 in the start-up circuit 10 is smaller than the width-to-length ratio of the sixth PMOS PM6 in the positive temperature current circuit 20, the width-to-length ratio of the fifth PMOS PM5 in the positive temperature current circuit 20 is equal to the width-to-length ratio of the sixth PMOS PM6 in the positive temperature current circuit 20, and the width-to-length ratio of the fifth NMOS NM5 in the positive temperature current circuit 20 is equal to the width-to-length ratio of the sixth NMOS NM6 in the positive temperature current circuit 20.
In the present embodiment, the ratio of the width to length ratio of PM5 to PM6 is 1: the ratio of the aspect ratio of 1, NM5 to NM6 is 1:1, a step of; PM2, NM1 and NM2 all mirror positive temperature coefficient currents, forming a second current, a fourth current and a fifth current respectively, wherein the ratio of the width to length ratio of PM2 and PM6 can be designed to be larger than 1:1, generally 1:4 or other ratio meeting the requirements, the ratio of the width to length ratio of NM1 to NM5 can be made small, so that the mirrored current is small, and the low power consumption requirements, such as 1:80, the ratio of the width to length ratios of NM2 and NM5 can also be made small, so that the mirrored current is small, meeting the low power consumption requirement, but is larger than the ratio of the width to length ratios of NM1 and NM5, such as 1:40.PM8 and NM7 take appropriate values according to the power-on and power-off reset voltages. And further, the whole circuit can be ensured to output a reset signal accurately according to the reset voltage on the premise of low power consumption, and the reset accuracy is further ensured.
Similarly, the current flowing through PM7 is mirrored by NM1 or NM2 by NM5, and is also positive temperature coefficient, PM7 operates in triode region, and the temperature coefficient of threshold voltage |vthp| of PM7 tends to be independent of temperature due to the positive temperature coefficient current regulation.
Reset flip voltage vturn=vref+|vthp|+vx+vy=vref+|vthp|=vgsn+|vthp| of the whole circuit, wherein Vx is an additional voltage caused by PM2 equivalent resistance, vy is an additional voltage caused by NM1, NM2 and NM3 equivalent resistance, and Vx and Vy are negligible in low power consumption applications; since VREF (VGSn) is a temperature independent quantity, |Vthp| is a quantity that tends to be temperature independent, the reset flip voltage Vturn is also a substantially temperature independent quantity so that the entire circuit is temperature compensated.
In yet another embodiment, referring to fig. 4, fig. 4 is a schematic diagram of a second circuit connection of a low power consumption power-on-off reset circuit with temperature compensation, which is different from fig. 3 in that a MOS transistor has one more pin substrate, so that the substrate of the PMOS transistor is connected to a high level end, and the substrate of the NMOS transistor is connected to a low level end. As can be seen, the reference voltage VREF is connected to the gate of PM8 to control the turn-on of PM8, the source of PM8 is connected to the power line VDD, the drain of PM8 is connected to two resistor strings of NM1 and NM3, and the two NMOS resistor strings are connected to the ground line GND. The drain electrode of the PMOS transistor is connected to a first inverter INV1, which may be an output control NM3 of the schmitt inverter, and the first inverter INV1 is further connected to a second inverter INV1, and a reset signal is finally output through the first inverter INV 1. The reset voltage turning point of the reset circuit is reference voltage VREF+the conduction voltage of the PMOS tube. The reset overturning voltage does not change along with temperature, process and power supply voltage, is not limited by the power on-off speed, widens the application voltage of the chip, and reduces the power consumption of the chip.
Further, based on the low-power-consumption power-on-power-off reset circuit diagram with temperature compensation, the power-on reset of the whole control flow is described: in the first stage, when VDD starts to start up the operation of the start-up circuit, the voltage at VREF point is quickly pulled up by PM1, and follows VDD to change, so that PM8 pipe is turned off in this period, and the voltage at C point is likewise pulled up by PM4, and follows VDD to change, the voltage at C point is raised to turn on NM1 and NM2 along with voltage rise, so that the voltage at B point is pulled down (NM 1 is turned on, B point is grounded), then the output level of the first inverter INV1 is high, NM3 is turned on under the premise of NM2 being turned on, the voltage at B point is pulled down, the high level outputs reset signal RST through the second inverter INV2, at this time, the RST signal is low, and the reset signal is valid; in the second stage, as the positive temperature coefficient current I1 is established (the voltage at the point C increases to enable NM5 and NM6 to be conducted along with the voltage rise to generate the positive temperature coefficient current I1), the starting circuit is out of operation, the second current is also established, the second current and NM7 form a stable voltage VREF, NM7 is connected into a diode form (the grid electrode and the drain electrode are connected together), and at the moment, the voltage of VREF is the grid source voltage VGSn of NM 7; in the third stage, as the VDD voltage continues to rise, the value of VDD-VGSn is greater than the absolute value |vthp| of the turn-on voltage of PM8, PM8 is turned on, the voltage at point B is pulled up, the power-on reset is completed after reaching the flip voltage of INV1, at this time, the reset signal RST is turned high, and NM3 is in the off state after the power-on reset is completed. From the above, the reset flip voltage of the whole circuit is vgsn+|vthp|+vx+vy, where Vx is the additional voltage due to PM2 equivalent resistance and Vy is the additional voltage due to NM1, NM2, and NM3 equivalent resistance. In order to achieve low power consumption, the current of each branch is small, for example, the positive temperature coefficient current is 15nA, the second current is 60nA, the larger the equivalent resistance is, the smaller the Vx and the Vy are, but the Vx and the Vy are always larger than zero. The voltage of VREF can be quickly increased when the PM1 tube is introduced to power on, so that the VREF can still quickly respond to the power on under the condition of low power consumption, the reset circuit can realize the power on at high and low speeds, and the reason is that the power on at high and low speeds is that the process can occur no matter what speed, namely, the VREF is firstly changed along with the change of VDD and then is changed into VGSn controlled by positive temperature coefficient current through the introduction of the PM1 tube, then PM8 is turned on, and the RST signal is ensured to be low (namely effective) in the initial stage when the power on is performed at high and low speeds. When VREF voltage becomes VGSn to be controlled, positive temperature coefficient current is generated at the moment, and a circuit of temperature-independent current is similar to a circuit of reference voltage, reference current and the like in a chip, which means that the power supply voltage VDD rises to a voltage at which a basic circuit in the chip can work normally, so that a reset flip signal of the circuit is prevented from being too early, and the phenomenon that the chip cannot work normally due to the early disappearance of the reset signal is avoided. Based on the current mirror structure, the circuit is less affected by variations in the supply voltage. Because the voltage value of VREF can be stabilized at VGSn certainly after the VDD is powered up to reach a stable value, the voltage value is not influenced by a power supply, and the structure can be changed into a high level after the reset is finished even if the low-voltage quick power-up is finished, and the structure enters a normal state, so that the phenomenon that the low-voltage quick power-up is always in a reset state and cannot be separated from the reset state is avoided.
The power-on reset of the whole control flow is described as follows: when the power supply voltage VDD drops to a certain extent, VDD is smaller than vgsn+|vthp|+vx+vy, PM8 is turned off, the B-point voltage is pulled down by NM1, the output of the first inverter INV1 becomes high, NM3 is turned on, this fifth current path of NM2 is formed, the B-point voltage is pulled lower, the output becomes low after passing through the two-stage inverters, that is, RST is changed from high to low, the circuit outputs a reset signal, and the power-on reset is completed. The fifth current branch of NM2 and NM3 is added to ensure that the power-down reset voltage is lower than the power-on reset voltage, so that error reset caused by unstable power supply VDD in the power-on and power-off process is avoided, the anti-interference capability of the circuit is improved, and the feedback also accelerates the power-on reset speed.
Based on positive temperature coefficient current i1= (Vbe 0-Vbe 1)/r 1 being positive temperature coefficient and on voltage Vthn7 of NM7 being negative temperature coefficient, by adjusting the magnitude of the second current and the aspect ratio of NM7, the voltage at VREF point can be made zero temperature coefficient as shown in formula (5), hardly affected by temperature. The reset flip voltage vturn=vref+|vthp|+vx+vy=vref+|vthp|=vgsn+|vthp| of the circuit, and Vx and Vy are negligible in low power applications; this reduces the temperature coefficient of the power-on-power-off reset voltage, resulting in improved temperature performance of the overall circuit. The whole power consumption of the whole circuit is mainly determined by positive temperature coefficient current, the positive temperature coefficient current can be very low and is little influenced by the process and the voltage, and the whole power consumption of the circuit can be 100nA or even lower. The power supply has low power consumption and can quickly respond to the power-on and power-off speed, and the power-on and power-off speed is not limited by the power supply.
The invention also provides a resetting device, and referring to fig. 5, fig. 5 is a schematic diagram of the resetting device.
The reset device is used for loading the low-power-consumption power-on and power-off reset circuit 100 with temperature compensation, and comprises a power switch 200 and a circuit board 300, wherein the power switch 200 is connected with the low-power-consumption power-on and power-off reset circuit 100 with temperature compensation, and the circuit board 300 is provided with the low-power-consumption power-on and power-off reset circuit 100 with temperature compensation and the power switch 200.
In yet another embodiment of the reset device, the reset device includes a power switch 200 and a circuit board 300, wherein the power switch 200 is connected to the low power up and down reset circuit 100 with temperature compensation and is disposed on the circuit board 300;
in yet another embodiment of the reset device, the reset device includes a power switch 200 and a circuit board 300, wherein the power switch 200 is connected with the low power up and down reset circuit 100 with temperature compensation and is disposed outside the circuit board 300;
in yet another embodiment of the reset device, the reset device includes a power switch 200 and a plurality of circuit boards 300, the power switch 200 is connected to the low power up and down reset circuit 100 with temperature compensation, and is disposed on a different circuit board 300 than the low power up and down reset circuit 100 with temperature compensation;
In yet another embodiment of the reset device, the reset device includes a power switch 200, a power device and a circuit board 300, where the power switch 200, the power switch and the low-power up-down reset circuit 100 with temperature compensation are sequentially connected and disposed on the circuit board 300;
in yet another embodiment of the reset device, the reset device includes a power switch 200, a power device and a plurality of circuit boards 300, wherein the power switch 200, the power switch 200 and the low power consumption power up and down reset circuit 100 with temperature compensation are sequentially connected, the circuit board 300 with temperature compensation power up and down reset circuit 100 is disposed on one of the circuit boards 300, and the power device and the power switch 200 are disposed on the other circuit boards 300;
in yet another embodiment of the reset device, the reset device includes a power switch 200, a power device, and a plurality of circuit boards 300, where the power device, the power switch 200, and the low power consumption power up-down reset circuit 100 with temperature compensation are sequentially connected, and the low power consumption power up-down reset circuit 100 with temperature compensation and the power switch 200 are disposed on one of the circuit boards 300, and the power device is disposed on the other circuit boards 300.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
The foregoing description is only of the optional embodiments of the present invention, and is not intended to limit the scope of the invention, and all the equivalent structural changes made by the description of the present invention and the accompanying drawings or the direct/indirect application in other related technical fields are included in the scope of the invention.

Claims (10)

1. The low-power-consumption power-on and power-off reset circuit with temperature compensation is characterized by comprising a power line, a starting circuit, a positive temperature current circuit, a reset circuit, a grounding wire and a reset signal output interface;
The starting circuit, the positive temperature current circuit and the reset circuit are respectively connected with the power line and the ground line, the starting circuit, the positive temperature current circuit, the reset circuit and the reset signal output interface are sequentially connected, and the starting circuit is connected with the reset circuit;
the starting circuit is used for starting the low-power-consumption power-on and power-off reset circuit with temperature compensation, the positive temperature current circuit is used for generating positive temperature coefficient current based on the started low-power-consumption power-on and power-off reset circuit with temperature compensation, the reset circuit is used for generating negative temperature coefficient voltage based on the started low-power-consumption power-on and power-off reset circuit with temperature compensation, generating turnover voltage irrelevant to temperature based on the positive temperature coefficient current and the negative temperature coefficient voltage, and outputting a reset signal based on the turnover voltage.
2. The low power consumption power-on-off reset circuit with temperature compensation according to claim 1, wherein the starting circuit comprises a third PMOS transistor, a fourth PMOS transistor and a fourth NMOS transistor;
the source electrode of the third PMOS tube is connected with the power line, the grid electrode of the third PMOS tube is connected with the positive temperature current circuit, the drain electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and the grid electrode of the fourth NMOS tube, the grid electrode of the fourth PMOS tube is connected with the reset circuit, the source electrode of the fourth PMOS tube is connected with the power line, the drain electrode of the fourth PMOS tube is connected with the positive temperature current circuit, and the source electrode and the drain electrode of the fourth NMOS tube are connected with the ground line.
3. The low power consumption power-on-off reset circuit with temperature compensation according to claim 2, wherein the positive temperature current circuit comprises a first control circuit and a second control circuit, the first control circuit comprises a fifth PMOS tube, a sixth PMOS tube, a fifth NMOS tube and a sixth NMOS tube;
the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected with the power line, the grid electrode of the sixth PMOS tube is respectively connected with the drain electrode of the sixth PMOS tube, the grid electrode of the fifth PMOS tube, the reset circuit and the grid electrode of the third PMOS tube, the drain electrode of the fifth PMOS tube is sequentially connected with the grid electrode of the fifth NMOS tube and the drain electrode of the fifth NMOS tube, the grid electrode of the fifth NMOS tube is respectively connected with the drain electrode of the fourth PMOS tube, the reset circuit and the grid electrode of the sixth NMOS tube, the drain electrode of the sixth NMOS tube is connected with the drain electrode of the sixth PMOS tube, and the second control circuit is connected with the source electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube.
4. The low power consumption power on-off reset circuit with temperature compensation of claim 3, wherein said second control circuit comprises a first transistor, a second transistor and a first resistor;
The emitter of the first transistor is connected with the source electrode of the fifth NMOS tube, the collector and the base of the first transistor are connected with the ground wire, the first end of the first resistor is connected with the source electrode of the sixth NMOS tube, the second end of the first resistor is connected with the emitter of the second transistor, the collector and the base of the second transistor are connected with the ground wire, and the first transistor and the second transistor comprise PNP transistors.
5. The low power consumption power-on-power-off reset circuit with temperature compensation according to claim 4, wherein the positive temperature coefficient current has a calculation formula: i1 = (Vbe 1-Vbe 2)/r 1, where Vbe1 is the on voltage of the first transistor, vbe2 is the on voltage of the second transistor, and r1 is the resistance value of the first resistor.
6. The low power consumption power-on and power-off reset circuit with temperature compensation according to claim 5, wherein the reset circuit comprises a third control circuit, a fourth control circuit and an output circuit, wherein the third control circuit comprises a first PMOS tube, a second PMOS tube, a seventh PMOS tube and an eighth PMOS tube;
the grid electrode of the first PMOS tube is connected with the grid electrode of the fourth PMOS tube, the power line is connected with the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the grid electrode of the seventh PMOS tube, the source electrode of the seventh PMOS tube and the source electrode of the eighth PMOS tube, the grid electrode of the second PMOS tube is connected with the grid electrode of the sixth PMOS tube, the drain electrode of the second PMOS tube is respectively connected with the grid electrode of the eighth PMOS tube, the drain electrode of the first PMOS tube and the fourth control circuit, and the drain electrode of the seventh PMOS tube and the drain electrode of the eighth PMOS tube are respectively connected with the fourth control circuit and the output circuit after being connected.
7. The low power consumption power-on-power-off reset circuit with temperature compensation according to claim 6, wherein the fourth control circuit comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a seventh NMOS transistor;
the grounding wire is connected with the source electrode of the first NMOS tube, the source electrode of the second NMOS tube and the source electrode of the seventh NMOS tube, the grid electrode and the drain electrode of the seventh NMOS tube are connected with the drain electrode of the second PMOS tube, the grid electrode of the first NMOS tube is respectively connected with the grid electrode of the second NMOS tube and the grid electrode of the fifth NMOS tube, the drain electrode of the first NMOS tube is connected with the drain electrode of the eighth PMOS tube, the drain electrode of the second NMOS tube is connected with the source electrode of the third NMOS tube, the drain electrode of the third NMOS tube is connected with the drain electrode of the eighth PMOS tube, and the grid electrode of the third NMOS tube is connected with the output circuit.
8. The low power consumption power-on-power-off reset circuit with temperature compensation of claim 7, wherein said output circuit comprises a first inverter and a second inverter;
the input end of the first inverter is connected with the drain electrode of the eighth PMOS tube, the output end of the first inverter is respectively connected with the grid electrode of the third NMOS tube and the input end of the second inverter, and the output end of the second inverter is connected with the reset signal output interface.
9. The low power consumption power on and power off reset circuit with temperature compensation according to any one of claims 1 to 8, wherein a width-to-length ratio of a third PMOS transistor in the start-up circuit is smaller than a width-to-length ratio of a sixth PMOS transistor in the positive temperature current circuit, the width-to-length ratio of a fifth PMOS transistor in the positive temperature current circuit is equal to the width-to-length ratio of the sixth PMOS transistor in the positive temperature current circuit, and the width-to-length ratio of a fifth NMOS transistor in the positive temperature current circuit is equal to the width-to-length ratio of the sixth NMOS transistor in the positive temperature current circuit.
10. A reset device, characterized in that the reset device is used for loading the low-power-consumption power-on-off reset circuit with temperature compensation according to any one of claims 1 to 9, the reset device comprises a power switch and a circuit board, the power switch is connected with the low-power-consumption power-on-off reset circuit with temperature compensation, and the circuit board is provided with the low-power-consumption power-on-off reset circuit with temperature compensation and the power switch.
CN202310278635.7A 2023-03-21 2023-03-21 Low-power-consumption power-on and power-off reset circuit with temperature compensation function and reset device Active CN116505925B (en)

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