CN109343639B - Low-temperature floating band gap reference voltage circuit, method and chip thereof - Google Patents

Low-temperature floating band gap reference voltage circuit, method and chip thereof Download PDF

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CN109343639B
CN109343639B CN201811295320.9A CN201811295320A CN109343639B CN 109343639 B CN109343639 B CN 109343639B CN 201811295320 A CN201811295320 A CN 201811295320A CN 109343639 B CN109343639 B CN 109343639B
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reference voltage
resistor
module
compensation
band
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CN109343639A (en
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朱光前
张启东
杨银堂
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Chongqing Institute Of Integrated Circuit Innovation Xi'an University Of Electronic Science And Technology
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Xidian University
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

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Abstract

The invention provides a low-temperature drift band gap reference voltage circuit, a method and a chip thereof; the circuit comprises a self-bias module, a band-gap reference core module and a voltage generation module; the method comprises the following steps: generating a primary reference voltage; generating a reference voltage before compensation by base current correction and a primary reference voltage; generating a low temperature drift bandgap reference voltage. The low-temperature drift band-gap reference voltage circuit and the method are applied to a power management chip. The invention has the advantages that: the band-gap reference voltage source circuit with ultrahigh precision and ultralow temperature drift coefficient is realized, and high-stability reference voltage can be provided for the circuit application with higher reference voltage requirement.

Description

Low-temperature floating band gap reference voltage circuit, method and chip thereof
Technical Field
The invention relates to the field of electronic circuits, in particular to a low-temperature floating band gap reference voltage circuit, a method and a chip thereof.
Background
At present, a reference voltage source has been used as an indispensable basic module in a semiconductor integrated circuit, which is widely used in amplifiers, analog-to-digital converters, digital-to-analog converters, radio frequencies, sensors, and power management chips. The conventional reference voltage source comprises a voltage reference based on reverse breakdown characteristics of a zener diode, a voltage reference based on forward conduction characteristics of a PN junction, a band gap reference and other implementation modes, wherein the band gap reference has the advantages of simple structure, stable voltage and the like, so that the reference voltage source is widely applied.
With the development of semiconductor technology and portable electronic products, the demand for reference voltage sources with low power consumption and high power supply voltage range is greatly increased, which also leads to a great increase in the design requirements of bandgap references. The bandgap reference may generate a reference voltage or reference voltage having a certain temperature characteristic regardless of power supply and process. The stability of the bandgap reference has a direct and crucial influence on the generation of the internal power supply, the adjustment of the output voltage, etc. of the whole system. The bandgap reference voltage must be able to overcome manufacturing process variations, variations in the system internal supply voltage over the operating range, and the effects of ambient temperature. As the accuracy of the system increases, the requirements on the temperature, voltage and process stability of the reference also increase.
In the design of power management chips, analog-to-digital converters (ADC), digital-to-analog converters (DAC), dynamic memory (DRAM), Flash memory, and other chips, the design of a bandgap reference with a low temperature coefficient, low power consumption, and a high Power Supply Rejection Ratio (PSRR) is critical.
The Brokaw bandgap circuit is a new bandgap reference source circuit proposed by Brokaw in 1974. As shown in the Brokaw bandgap cell diagram of fig. 1, assuming that the circuit is in an equilibrium state, due to the voltage clamping effect of the op-amp OPs1, the voltage drops across the two resistors Rs1 and Rs2 are equal, and the currents flowing through the two branches are equal, the base-emitter voltage difference of the two transistors Qs1 and Qs2 is:
Figure BDA0001851025300000021
wherein, the area ratio of the emitting electrodes of the transistors Qs1 and Qs2 is N. The current flowing through Rs2 is:
Figure BDA0001851025300000022
then the current flowing through the resistor Rs1 is the sum of the currents at the emitters of the two transistors Qs1 and Qs2, and the expression for the output reference voltage Vsref is:
Figure BDA0001851025300000023
by selecting a suitable ratio of N to the resistors Rs1 and Rs2, the output reference voltage Vsref with a smaller temperature coefficient can be obtained.
However, the bandgap reference circuit of the prior art has the following problems:
1) as the temperature changes, the bias current supplied to the bandgap voltage generating circuit will generally change, resulting in inaccurate reference voltage for final output.
2) The circuit design itself can cause poor compensation accuracy along with mismatch;
3) the high order temperature compensation accuracy of the actual bandgap reference is poor as a result of the excessively rough theoretical approximation of some circuits.
Disclosure of Invention
In order to solve the problems: the invention provides a low-temperature floating band gap reference voltage circuit, a method and application thereof. By utilizing the exponential characteristic of the base current to the temperature, in the bandgap reference core circuit, the current is corrected by the resistor, thereby correcting the output voltage. Meanwhile, a curvature compensation module capable of generating curvature-upward parabolic trend current is added to compensate high-order temperature nonlinear terms in the reference voltage.
According to a first aspect of the invention, a low temperature floating bandgap reference voltage circuit is provided:
the specific technical solution of the invention is as follows:
a low-temperature drift band-gap reference voltage circuit comprises a self-bias module, a band-gap reference core module and a voltage generation module;
the self-bias module provides bias voltage and bias current; the self-bias module is used as a self-starting circuit in the power-on process of a power supply;
the band-gap reference core module is composed of Brokaw band-gap units and generates a primary reference voltage, and the band-gap reference module comprises a base current correction resistor; a base current correction resistor is added into the base of a triode pair in a Brokaw band gap unit, and a reference voltage before compensation is generated after correction operation is carried out.
The voltage generation module generates a final reference voltage.
Preferably, the low-temperature floating band gap reference voltage circuit further comprises a curvature compensation module;
the curvature compensation module performs nonlinear curvature compensation on the reference voltage before compensation; the nonlinear curvature compensation is that a curvature compensation module generates nonlinear curvature compensation current which generates voltage through a resistor for compensation;
further preferably, the self-bias module includes field effect transistors M5 and M6; triodes Q3 and Q4, resistors R6 and R7; the field effect transistors M5 and M6 are PMOS tubes; the triode Q3 is a PNP triode and the triode Q4 is an NPN triode;
the source electrodes of the field effect transistors M6 and M5 are connected with a power supply VDD, and the grid electrode of the field effect transistor M5 is connected with the grid electrode of M6 and the drain electrode of M5; the field effect transistors M6 and M5 form a current mirror; the drain of the field effect transistor M6 and one end of the resistor R7 are connected to the point C and are used as the first output end of the self-bias module to be connected with the band-gap reference core module; the point B at the other end of the resistor R7 is connected with the base electrode of the triode Q4 and the emitting electrode of the triode Q3; an emitter E point of the triode Q4 is connected with one end of the resistor R6; the other end of the resistor R6 is grounded; the collector of the triode Q3 is grounded, and the base of the triode Q3 is used as a second output end of the self-bias module and is connected with the band-gap reference core module.
Further preferably, the bandgap reference core module comprises transistors Q1, Q2 and Q5; resistors R01, R02, R1, R2 and R3; an amplifier OP 1; r3 is a base current correction resistor; the transistors Q1, Q2, and Q5 are NPN transistors;
the collector of the triode Q5 is connected with a power supply VDD, the base of the triode Q5 is connected with the first output end of the self-bias module, and the emitter D point of the triode Q5 is connected with one end of the resistors R01 and R02; the triodes Q1 and Q2 form a triode pair, collectors of the triodes Q1 and Q2 are respectively connected with the other ends of the resistors R01 and R02, collectors of the triodes Q1 and Q2 are respectively connected with the inverting input end and the non-inverting input end of the amplifier OP1, bases of the triodes Q1 and Q2 are connected together through R3, a point A of a base of the triode Q1 is connected with a second output end of the self-bias module and is used as a first output end Vbgr of the band-gap reference core module to be connected with the voltage generation module; the output end of the amplifier OP1 is used as the second output end of the band-gap reference core module and is connected with the voltage generation module; an emitter of the triode Q1 is connected with one end of the resistor R2; an emitter of the triode Q2 is connected with one end of the resistor R2 through the resistor R1; the other end of the resistor R2 is connected to ground.
Further preferably, the voltage generation module includes a field effect transistor M10, resistors R4 and R5; the field effect transistor M10 is a PMOS tube;
the source of the field effect transistor M10 is connected with a power supply VDD, the gate of the field effect transistor M10 is connected with the second output end of the band-gap reference core module, the drain of the field effect transistor M10 is connected with one end of the resistor R4 together to be output as a final reference voltage Vref; the other end of the resistor R4 and one end of the resistor R5 are connected with a first output end of the band-gap reference core module; the other end of the resistor R5 is connected to ground.
Still further preferably, the M5 and the M6 have the same size.
Further preferably, the curvature compensation module comprises field effect transistors M1, M2, M3, M4, M7, M8 and M9; resistors R8, R9, and R10; an amplifier OP 2; the field effect transistors M1-M4, M7 and M8 are PMOS transistors. M9 is an NMOS tube; the curvature compensation module further comprises a resistor Rco;
one end of the resistor Rco is connected with the band gap reference core module, and the other end of the resistor Rco is grounded; the method specifically comprises the following steps: the resistor Rco is connected in series between the resistor R2 in the band gap reference core module and the ground; namely: one end of the resistor Rco is connected with a resistor R2 in the band-gap reference core module, and the other end of the resistor Rco is grounded; the non-inverting terminal of the amplifier OP2 is connected with the Vbgr node, the inverting terminal node M and the output terminal of the field effect transistor M9; the source of the field effect transistor M9 is connected with the power supply VDD, the drain and one end of the resistor R10 is connected with the node M; resistors R8-R10 are connected in series: the other end of the resistor R10 and one end of the resistor R9 are connected to the node H, the other end of the resistor R9 and one end of the resistor R8 are connected to the node L, and the other end of the resistor R8 is grounded;
the source electrode of the field effect transistor M1, the source electrode of the M2 and the drain electrode of the M7 are connected; the source electrode of the field effect transistor M3, the source electrode of the M4 and the drain electrode of the M8 are connected; the source stages of M7 and M8 are connected with a power supply VDD; the gates of M7 and M8 are connected to node Vpbias; the node Vpbias is the gate of M5 of the self-biasing module; the gate connection nodes VPTAT of M1 and M3; the gates of M2 and M4 are connected to nodes L and H, respectively; the drains of M2 and M3 are grounded; the drains of M1 and M4 are connected to one end of resistor Rco.
Even more preferably, the M7 and M8 have the same size.
Still further preferably, the bandgap reference core module includes trimming circuits Rt1 and Rt2, and the contact ports are respectively connected to the input terminals Vinp and Vinn of the amplifier OP 1.
In order to adjust the output voltage to meet the requirements of different applications:
more preferably, the resistor R5 in the voltage generation module includes a trimming circuit Rt3, and the resistor R5 is a potentiometer Rt3 and R50 connected in series.
Even more preferably, the trimming circuit comprises n trimming modules T0 to Tn connected in series; each fine tuning module comprises a logic control unit L, a switch device K and a fine tuning resistor RT; the total number of the logic control unit L, the switching device K and the trimming resistor RT of the n-bit trimming module is K0 to Kn, L0 to Ln and RT0 to RTn; the trimming circuit also comprises a digit m of a control signal, and the control signal is connected with the logic control unit L; n and m are positive integers greater than 1;
the output of the logic control unit L controls the on state of the switching device K, and when the switching device K of the corresponding node is turned on, the node is connected to the output terminal; when the switching device K is turned off, the corresponding node is disconnected from the output terminal.
According to a second aspect of the present invention, the present invention provides a method for generating a low temperature floating bandgap reference voltage, comprising the following steps:
step 1: generating a primary reference voltage;
step 2: generating a reference voltage before compensation by base current correction and a primary reference voltage;
and step 3: generating a low temperature drift bandgap reference voltage.
In order to make the temperature characteristic of the reference voltage better:
preferably, step 2 may be followed by step 21: carrying out nonlinear compensation on the reference voltage before compensation; the nonlinear curvature compensation is that the curvature compensation module generates nonlinear curvature compensation current which generates voltage through a resistor for compensation.
The specific step 21 is dynamic adjustment compensation; the dynamic adjustment compensation is to monitor the change of the positive temperature coefficient voltage VPTAT, continuously adjust the size of the compensation current and compensate the high-order term in the band gap reference BE junction voltage VBE. This can effectively reduce the temperature coefficient of the reference voltage.
Further preferably, the method further comprises a trimming step, and the trimming step is to trim the resistor.
Further preferably, the resistance trimming is to perform resistance trimming on an input terminal of the amplifier generating the primary reference voltage;
more preferably, the resistance trimming is to perform resistance trimming on a proportional resistance generating the low-temperature drift bandgap reference voltage.
It is further preferred that the resistance trimming is realized by a difference of the series resistance access.
Further preferably, when the resistance of the input terminal of the amplifier generating the primary reference voltage is adjusted, the resistances of the two inputs of the amplifier are adjusted in opposite directions.
More preferably, the step length n of the resistance trimming and the bit number m of the control signal are used; m and n have a relationship of 2mN; m and n are positive integers greater than 1.
According to a third aspect of the invention, the invention provides a chip applying a low temperature floating bandgap reference voltage circuit and method, comprising:
preferably, the low-temperature floating band gap reference voltage circuit and the method are applied to a power management chip.
Preferably, the low temperature floating bandgap reference voltage circuit and method is applied to chips such as an analog/digital converter, a digital/analog converter, a dynamic memory or a Flash memory.
The invention has the following advantages:
the band-gap reference voltage source circuit realizes the band-gap reference voltage source circuit with ultrahigh precision and ultralow temperature drift coefficient, and can provide high-stability reference voltage for the circuit application with higher reference voltage requirement.
Simulation results show that the temperature drift coefficient of the reference voltage output by the circuit is only 0.7ppm and the voltage change is only 0.4mV within a wide temperature range of-55-150 ℃. The circuit structure is easy to realize, has low process requirements and is suitable for various engineering applications.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 a schematic representation of a Brokaw bandgap cell.
FIG. 2 is a schematic diagram of a low temperature floating bandgap reference voltage circuit of the present invention.
FIG. 3 is a block diagram of a low temperature drift bandgap reference voltage circuit of the present invention.
FIG. 4 shows a first embodiment of a low temperature floating bandgap reference voltage circuit.
FIG. 5 shows a second embodiment of the low temperature floating bandgap reference voltage circuit of the present invention.
FIG. 6 shows a simulation result of the low-temperature floating bandgap reference voltage circuit of the present invention.
FIG. 7 shows the second simulation result of the low-temperature floating bandgap reference voltage circuit of the present invention.
FIG. 8 shows a third embodiment of the low temperature floating bandgap reference voltage circuit of the present invention.
Fig. 9 shows a first embodiment of a temperature compensation coefficient adjustment structure in a low-temperature floating bandgap reference voltage circuit according to the present invention.
Fig. 10 shows a second embodiment of a temperature compensation coefficient adjustment structure in a low-temperature floating bandgap reference voltage circuit according to the present invention.
FIG. 11 is a diagram of the low temperature floating bandgap reference voltage circuit of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The basic idea of a bandgap reference is to eliminate the temperature-dependent term in the base-emitter voltage VBE of a bipolar transistor, resulting in a bandgap voltage. VBE is
Figure BDA0001851025300000091
Where VG0 is the deduced bandgap voltage of silicon at 0K kelvin, T is the kelvin absolute temperature, Tr is the reference temperature, VBE0 is the base-emitter voltage at the reference temperature Tr, η is a positive process-dependent constant, and θ represents the temperature-dependent order of the collector current IC. VBE has a negative temperature coefficient, typically between-1.7 mV/C and-2 mV/C.
The invention provides a low-temperature floating band gap reference voltage circuit, a method and application thereof. The band-gap reference core circuit has the characteristics of wide low temperature drift range and high precision, and the current is corrected through a resistor (a resistor connected to the base of a triode) by utilizing the exponential characteristic of the base current to the temperature, so that the output voltage is corrected. Meanwhile, a curvature compensation module capable of generating curvature-upward parabolic trend current is added to compensate high-order temperature nonlinear terms in the reference voltage. The voltage provided by the power supply can be applied to a power Management chip (BMIC Battery Management IC) or other chips. Other chips may be analog-to-digital converters (ADCs), digital-to-analog converters (DACs), dynamic memory (DRAMs), Flash memory, etc.
The invention is realized based on a Brokaw band gap unit, the principle is shown in a low-temperature drift band gap reference voltage circuit principle diagram of FIG. 2, and the following can be known from FIG. 2: firstly, a primary reference voltage Vref (generated based on a Brokaw bandgap cell) generates a reference voltage Vref before compensation after being corrected and operated with a base current; the reference voltage Vref before compensation is generated after the base current correction operation may be output as a bandgap reference voltage.
In order to enable the bandgap reference voltage to have a lower temperature drift, a wider temperature range and higher precision, further, the reference voltage before compensation is subjected to nonlinear compensation operation, and the nonlinear curvature compensation current Ico compensates the reference voltage Vref before compensation, that is, the nonlinear curvature compensation current Ico generates voltage through a resistor and further compensates the reference voltage Vref before compensation; and finally generating the final reference voltage Vref.
The low-temperature drift band gap reference voltage circuit is specifically introduced as follows:
as shown in the block diagram of the low-temperature drift bandgap reference voltage circuit in fig. 3, the low-temperature drift bandgap reference voltage circuit includes a self-bias module 10, a bandgap reference core module 11, a curvature compensation module 12, and a voltage generation module 13.
The function of the self-bias module 10 is to provide bias (bias current or bias voltage) to other modules and can act as a start-up circuit during power-up of the power supply.
The band-gap reference core module 11 is used for generating a primary reference voltage, and meanwhile, the band-gap reference module comprises a base current correction resistor and generates a reference voltage before compensation after the base current correction operation;
it should be noted here that the primary reference voltage is generated based on a Brokaw bandgap cell. A base current correction resistor is added into the base of a triode pair in a Brokaw band gap unit, so that a reference voltage before compensation is generated after correction operation is carried out.
The curvature compensation module 12 is used for performing non-linear curvature compensation on the reference voltage before compensation. The nonlinear curvature compensation process comprises the following steps: the curvature compensation module 12 generates a non-linear curvature compensation current Ico, which generates a voltage through a resistor to compensate for a pre-compensation reference voltage Vref.
The voltage generation module 13 processes the compensated reference voltage to generate a final reference voltage Vref.
The following describes each module of the low-temperature floating band gap reference voltage circuit according to the embodiment of the present invention:
the first preferred embodiment:
as shown in fig. 4, the first embodiment of the low-temperature bandgap reference voltage circuit includes a self-bias module 10, a bandgap reference core module 11, and a voltage generation module 13 according to fig. 4.
The self-bias module 10 includes field effect transistors (MOS transistors) M5 and M6; triodes Q3 and Q4, resistors R6 and R7; the field effect transistors M5 and M6 are PMOS tubes; the transistor Q3 is a PNP transistor, and the transistor Q4 is an NPN transistor.
The source electrodes of the field effect transistors M6 and M5 are connected with a power supply VDD, and the grid electrode of the field effect transistor M5 is connected with the grid electrode of M6 and the drain electrode of M5; the field effect transistors M6 and M5 form a current mirror; the drain of the field effect transistor M6 and one end of the resistor R7 are connected to the point C and are used as the first output end of the self-bias module 10 to be connected with the band-gap reference core module 11; the point B at the other end of the resistor R7 is connected with the base electrode of the triode Q4 and the emitting electrode of the triode Q3; an emitter E point of the triode Q4 is connected with one end of the resistor R6; the other end of the resistor R6 is grounded; the collector of the transistor Q3 is grounded, and the base of the transistor Q3 is used as the second output end of the self-bias module 10 and is connected with the bandgap reference core module 11.
The self-starting process of the self-bias module 10 is as follows: the voltages at the point C and the point B are increased, the BE junctions of the transistors Q3 and Q4 are conducted, and the transistors Q3 and Q4 start the band-gap reference core module 11.
The band-gap reference core module 11 is generated based on a Brokaw band-gap unit and comprises triodes Q1, Q2 and Q5; resistors R01, R02, R1, R2 and R3; an amplifier OP 1; r3 is a base current correction resistor; the transistors Q1, Q2, and Q5 are NPN transistors.
The collector of the triode Q5 is connected with a power supply VDD, the base of the triode Q5 is connected with the first output end of the self-bias module 10, and the emitter D point of the triode Q5 is connected with one end of the resistors R01 and R02; the triodes Q1 and Q2 form a triode pair, collectors of the triodes Q1 and Q2 are respectively connected with the other ends of the resistors R01 and R02, collectors of the triodes Q1 and Q2 are respectively connected with an inverting input end and a non-inverting input end of the amplifier OP1, bases of the triodes Q1 and Q2 are connected together through R3, a point A of a base of the triode Q1 is connected with a second output end of the self-bias module 10 and is used as a first output end Vbgr of the band-gap reference core module 11 to be connected with the voltage generation module 13; the output end of the amplifier OP1 is used as the second output end of the bandgap reference core module 11 and is connected to the voltage generation module 13; an emitter of the triode Q1 is connected with one end of the resistor R2; an emitter of the triode Q2 is connected with one end of the resistor R2 through the resistor R1; the other end of the resistor R2 is connected to ground.
The voltage generation module 13 includes a field effect transistor M10, resistors R4 and R5; the field effect transistor M10 is a PMOS transistor.
The source of the field effect transistor M10 is connected with a power supply VDD, the gate of the field effect transistor M10 is connected with the second output end of the band gap reference core module 11, the drain of the field effect transistor M10 is connected with one end of the resistor R4 together to be output as a final reference voltage Vref; the other end of the resistor R4 and one end of the resistor R5 are connected with a first output end of the band-gap reference core module 11; the other end of the resistor R5 is connected to ground.
The low temperature floating bandgap reference voltage circuit of fig. 4, which is implemented based on a Brokaw bandgap cell, mainly generates a positive temperature coefficient voltage VPTAT at a node between resistors R1 and R2 by a difference Δ VBE between base-emitter voltages of Q1 and Q2 to compensate a linear term in a negative temperature coefficient in VBE of Q1, thereby implementing first-order temperature compensation.
Figure BDA0001851025300000121
Where k is the boltzmann constant, Q is the amount of charge, and N is the ratio of the emitter junction areas of Q1 and Q2.
Self-biasing module 10 in one embodiment is effective to provide bias to other modules in the circuit and can act as a start-up circuit during power-up of the power supply.
In the first embodiment, the emitter of the Q3 is connected with the base of the Q4, and the Q3 and the Q4 form a cascaded source follower structure. M5 and M6 have the same size.
In connection with the different nodes (A, B, C, D, E) shown in the first embodiment of the low temperature floating bandgap reference voltage circuit of FIG. 4:
wherein the voltage at point E is Vbgr + VBE 3-VBE 4, (where Vbgr is the voltage value of node A) and the bias current I0 is obtained
Figure BDA0001851025300000122
The voltage at point E has a positive temperature coefficient, where R6 selects a resistor with a positive temperature coefficient, making the bias current I0 more stable. The VBE of Q5 is used to counteract the VBE of Q3 as much as possible, so as to provide a relatively stable input voltage VD (i.e., the voltage of node D) for the bandgap reference core block 11:
VD＝Vbgr+I0R7(4)
since M5 and M6 constitute current mirrors and have the same size, the currents of the M5 and M6 drains are equal.
The band gap voltage Vbgr is usually only about 1.2V, and the reference voltage required in the application is not only 1.2V depending on the case. Different voltage values need to be generated by the voltage generation module 13. In the voltage generation module 13, Vref (i.e., the final reference voltage) is obtained by the resistor voltage divider networks R4 and R5.
In the first embodiment of fig. 4, the base currents Ib1, Ib2 and Ib3 of the transistors Q1, Q2 and Q3 generate voltage drops through the resistor R4, and unnecessary temperature-dependent terms are introduced into Vref, as shown in formula (5)
Figure BDA0001851025300000131
In equation, Vref _ nc and Vbgr are no longer linearly dependent due to the influence of the base current. In ideal conditions Vbgr is a temperature independent value, whereas the base current affects the temperature coefficient of the output voltage. The expression of the base current is an exponential function dependent on temperature
Figure BDA0001851025300000132
Therefore, a resistor R3 is added in the circuit to eliminate the influence of the base current on the output voltage, and the output voltage is compensated by using the exponential characteristic of the base current. R3 changed Vbgr value, as in formula (7)
Figure BDA0001851025300000133
Substitution of formula (7) into (5) gives
Figure BDA0001851025300000134
Wherein x is R4/R5, y is R2/R1, and K0 is the coefficient of negative temperature coefficient voltage VBE. K1 is the first order temperature compensation coefficient, and K2 is the higher order temperature compensation coefficient. Wherein the first order temperature compensation coefficient K1 is primarily related to the ratio of R2 and R1, and the high order temperature compensation coefficient K2 is primarily related to the magnitudes of R3 and z. Wherein the value of z is determined by the ratio of the magnitudes of the currents Ib3 and Ib 2.
Figure BDA0001851025300000141
Thus, the ratio of R2 and R1 determines the first order temperature compensation coefficient K1, while the magnitudes of R4 and R5 determine the value of Vref _ nc, and R6 determines the magnitude of I0, thereby determining the ratio of current Ib3 to current Ib 2. After the above coefficients are determined, the available R3 determines the high order temperature compensation coefficient K2. Therefore, the negative influence of the base current of the bipolar transistor on the final reference voltage Vref _ nc can be eliminated, and the reference voltage can be further compensated.
It should be noted that Vref _ nc is referred to as Vref in fig. 4, and the above formula is denoted as Vref _ nc mainly for the purpose of making a difference from Vref in the following second embodiment, which means that it is the final reference voltage Vref without undergoing nonlinear curvature compensation.
The second preferred embodiment:
the second preferred embodiment of the present invention is an improvement based on the first preferred embodiment, and corresponding contents in the first embodiment can be referred to where this embodiment is not mentioned.
Through the temperature compensation of the base current correction resistor, the obtained output voltage Vref has a downward curvature parabolic change trend and has a low temperature drift coefficient. In order to further improve the temperature drift tendency of the output voltage Vref under high-temperature and low-temperature conditions, it is considered to add a curvature compensation module in the circuit to compensate for Vref. The curvature compensation method adopts the idea of dynamic adjustment, and continuously adjusts the size of the compensation current Ico by monitoring the change of the positive temperature coefficient voltage VPTAT (proportional to absolute temperature), thereby realizing the compensation of high-order terms in VBE and effectively reducing the temperature coefficient of the reference voltage.
As shown in the curvature compensation diagram of the second embodiment of the low temperature floating bandgap reference voltage circuit in fig. 5, a curvature compensation module 12 is added on the basis of the base current calibration of the first embodiment. It should be noted that for convenience of illustration and description of the operation of the curvature compensation module 12, only the curvature compensation module 12 and its associated components are shown.
The curvature compensation module 12 comprises
Field-effect transistors M1, M2, M3, M4, M7, M8, and M9; resistors R8, R9, and R10; an amplifier OP 2; the field effect transistors M1-M4, M7 and M8 are PMOS transistors. M9 is an NMOS tube; the curvature compensation module 12 also includes a resistor Rco.
The series connection between the resistor R2 and ground in the bandgap reference core module 11 increases the resistance Rco. Namely: one end of the resistor Rco is connected with the resistor R2, and the other end is grounded.
The non-inverting terminal of the amplifier OP2 is connected with the Vbgr node, the inverting terminal node M and the output terminal of the field effect transistor M9; the source of the field effect transistor M9 is connected with the power supply VDD, the drain and one end of the resistor R10 is connected with the node M; resistors R8-R10 are connected in series: the other end of the resistor R10 and one end of the resistor R9 are connected to the node H, the other end of the resistor R9 and one end of the resistor R8 are connected to the node L, and the other end of the resistor R8 is grounded.
M1 and M2, M3 and M4 constitute two sets of differential pair transistors: the source electrode of the field effect transistor M1, the source electrode of the M2 and the drain electrode of the M7 are connected; the source electrode of the field effect transistor M3, the source electrode of the M4 and the drain electrode of the M8 are connected; the source stages of M7 and M8 are connected with a power supply VDD; the gates of M7 and M8 are connected to node Vpbias; the nodes Vpbias are the gate of M5 and the gate of M6 (not shown in FIG. 5); the gate connection nodes VPTAT of M1 and M3; the gates of M2 and M4 are connected to nodes L and H, respectively; the drains of M2 and M3 are grounded; the drains of M1 and M4 are connected to one end of resistor Rco.
M7 and M8 are the same size, and form a current mirror with M5 and M6. Currents Is1 and Is2 with the same magnitude are obtained at the drains of M7 and M8 respectively. The current of the drain connected between M1 and M4 is the error correction current Ico.
The gates of transistors M1 and M3 are connected to the positive temperature coefficient voltage VPTAT in the Bandgap core. Under the action of the amplifiers OP2 and M9 (here, M9 is a source follower), the voltage at point M is equal to the node Vbgr, and the nodes H, L between the series resistors R10, R9 and R8 provide voltages Vh and Vl with different magnitudes, as shown in formula (10).
Figure BDA0001851025300000161
In the circuit, the PMOS transistors M1 to M4 work in a weak inversion region, and the subthreshold region current is
Figure BDA0001851025300000162
Current through two pairs of differential pair transistors is
Is＝Is1＝Is2＝ID1+ID2＝ID3+ID4(12)
The drain currents ID1 and ID4 of M1 and M4 obtained in combination of (11) and (12), respectively, are
Figure BDA0001851025300000163
When the circuit IS in a low temperature environment, VPTAT IS low, and ID1 obtained from equation (13) IS approximately equal to IS, i.e. the current from IS mostly passes through M1, ID1 IS high, and ID4 IS low and IS approximately equal to 0. ID1 becomes progressively smaller as the temperature increases. When the temperature exceeds Tmid (where Tmid is the middle of the temperature range), ID1 gradually decreases to 0 and ID4 begins to increase. When the circuit IS operated under high temperature conditions, VPTAT IS greater than VH, and ID4 IS approximately equal to IS obtained from equation (13), when ID1 IS lower. The sum of currents ID1 and ID4 is the compensation current Ico, which is passed through a resistor Rco in the bandgap reference so that Vref is compensated primarily by ID1 at low temperatures and by ID4 at high temperatures. During temperature variations, when VPTAT IS equal to VH or VL, the compensation current Ico IS equal to IS/2.
Combining the result of equation (8), the final Vref is shown in equation (14).
Figure BDA0001851025300000171
And (3) carrying out simulation on the parameter graphs obtained in the first preferred embodiment and the second preferred embodiment.
As shown in FIG. 6, which is a simulation result of the low temperature floating bandgap reference voltage circuit of the present invention, FIG. 6 shows a trend graph of ID1, ID4 and Ico with temperature. The trend of the slope change of ID1 and ID4 can be shown by comparison with a linear straight line. Two of the intersections are slope transition points of the current curve and represent points where VPTAT is equal to VL and VH, respectively. The values of VL and VH can be changed by adjusting the sizes of the series resistors R10, R9 and R8, so that the exponential change track of the compensation current is changed, and the best curvature compensation effect is realized.
As shown in fig. 7, which is a simulation result of the low temperature floating bandgap reference voltage circuit of the present invention, fig. 7 is a graph comparing Vref before curvature compensation, curvature compensation current Ico and Vref after curvature compensation.
The pre-curvature compensation Vref (the uppermost plot in figure 7) behaves as a downward opening parabolic curve over the temperature range of-55 c to 150 c. The curvature compensation current Ico (middle diagram in fig. 7) exhibits a parabolic curve with an upward opening in the temperature range of-55 c to 150 c. The curvature compensation current Ico generates a compensation voltage through the compensation resistor Rco, and is superimposed with Vref to obtain a curvature-compensated Vref voltage (the lowermost diagram in fig. 7). The Vref voltage after curvature compensation is represented as a curve with double wave peaks in the temperature range of-55-150 ℃, and the difference of the simulation result of the maximum voltage and the minimum voltage is only 0.3 mV.
The third preferred embodiment:
the third preferred embodiment of the present invention is an improvement based on the first preferred embodiment and the second preferred embodiment, and reference may be made to corresponding contents in the first preferred embodiment and the second preferred embodiment, where this embodiment is not mentioned in part.
On the basis of the first preferred embodiment and the second preferred embodiment, in order to avoid performance degradation caused by process variation or mismatch to the circuit, a trimming circuit is further added in the structure for correcting the circuit after production is completed.
As shown in fig. 8, the third embodiment of the low temperature drift bandgap reference voltage circuit of the present invention, as shown in fig. 8, the trimming circuit for temperature drift coefficient in the bandgap reference core module 11 includes two potentiometers Rt1 and Rt2, whose contact point ports are respectively connected to the input terminals Vinp and Vinn of the amplifier OP 1. It should be noted that fig. 8 only shows a part of the bandgap reference core module 11, and it should be emphasized that the improvement is performed by taking the second preferred embodiment as an example, and the similar improvement can be performed by the first preferred embodiment, and the detailed description is omitted here.
As can be seen from fig. 8, R5 in the voltage generating module 13 also includes a potentiometer Rt3 as a trimming circuit, i.e., R5 is a series of potentiometers Rt3 and R50. The voltage regulator is used for regulating the output voltage to meet the requirements of different applications.
Fig. 9 shows a specific principle of a potentiometer according to a first embodiment of the temperature compensation coefficient trimming structure in the low temperature floating bandgap reference voltage circuit of the present invention, and as can be seen from fig. 9, the potentiometer includes n trimming modules T0 to Tn connected in series. In each trimming module it contains a logic control unit L, a switching device K and a trimming resistor RT. The total of the logic control unit L, the switching device K and the trimming resistor RT for the n-bit trimming module is K0 to Kn, L0 to Ln, RT0 to RTn.
The potentiometer operates on the principle that the position of the output terminal in the series resistor is adjusted, and an input m-bit coded (shown as a 4-bit code in fig. 9) signal closes only one switch at a time. Resistors RT0 to RTN are connected in series, the output of the logic control unit L controls the on state of the switching device K, and when the switching device K of the corresponding node is turned on, the node is connected to the output terminal; when the switching device K is turned off, the corresponding node is disconnected from the output terminal.
A node to be trimmed is led out from the n-bit trimming module connected in series, and fig. 9 illustrates an input terminal Vout of OP1 as an example.
The trimming circuit is connected in series in the circuit. The step length n of trimming by the trimming circuit and the number of bits of the control signal (i.e. the number of bits m input to the logic control unit) determine the range of trimming and the number of trimming points. Their relationship is2m＝n。
Here, m is 4 and n is 16. Namely a 4-bit trimming structure, and 16 trimming points are provided. When the circuit needs to adjust the temperature coefficient, the position of the contact point is changed.
In fig. 8 the two potentiometers are adjusted in opposite directions. As shown in fig. 8, where the total size of Rt1 and Rt2 is Rta + Rtb, where Rta is Rtb is n · R, and when the circuit is adjusted, Rta is (n + x) · R and Rtb is (n-x) · R, where x is a value between-n and n, the ratio of the two positive temperature coefficient currents IPTAT1 and IPTAT2 is IPTAT1
κ＝IPTAT2/IPTAT1＝(x+n)/(x-n) (15)
Thus obtaining the modified positive temperature coefficient voltage of
Figure BDA0001851025300000191
There are several implementations of the potentiometer, and another implementation is shown in fig. 10, which is an embodiment of the temperature compensation coefficient trimming structure in the low-temperature floating bandgap reference voltage circuit of the present invention, and it includes n-bit trimming modules T0 to Tn connected in series. In each trimming module it contains a logic control unit L, a transmission gate Tr, a not gate N and a trimming resistor RT. For N-bit trimming module logic control unit L, transmission gate Tr NOT gate N and trimming resistor RT, the total is L0 to Ln, Tr0 to Trn, N0 to Nn, RT0 to RTn. Its advantage is high control consistency and no detailed description.
For convenience of explanation and understanding, the overall circuit diagram of the invention is given, as shown in fig. 10, the overall circuit diagram of the low-temperature floating bandgap reference voltage circuit of the invention is shown, and as can be seen from fig. 10, the circuit diagram is a combination of the first preferred embodiment, the second preferred embodiment and the third preferred embodiment.
Based on the foregoing preferred embodiments, the present invention further provides a method for generating a low-temperature floating bandgap reference voltage, comprising the following steps:
step 1: generating a primary reference voltage;
step 2: generating a reference voltage before compensation by base current correction and a primary reference voltage;
and step 3: generating a low temperature drift bandgap reference voltage.
In order to make the temperature characteristic of the reference voltage better:
step 2 may be followed by step 21: carrying out nonlinear compensation on the reference voltage before compensation; the nonlinear curvature compensation is that the curvature compensation module generates nonlinear curvature compensation current which generates voltage through a resistor for compensation.
The specific step 21 is dynamic adjustment compensation; the dynamic adjustment compensation is to monitor the change of the positive temperature coefficient voltage VPTAT, continuously adjust the size of the compensation current and compensate the high-order term in the band gap reference BE junction voltage VBE. This can effectively reduce the temperature coefficient of the reference voltage.
In the method, the resistance trimming method further comprises a trimming step, wherein the trimming step refers to trimming the resistance.
The resistance trimming can be carried out in two parts:
to avoid performance degradation to the circuit caused by process variations or mismatches: performing resistance trimming on the input end of the amplifier generating the primary reference voltage;
in order to adjust the output voltage to meet the requirements of different applications: and (3) carrying out resistance trimming on the proportional resistor generating the low-temperature floating band gap reference voltage.
The resistance trimming can be realized by different access of series resistors. When the resistance of the input end of the amplifier in the generation of the primary reference voltage is adjusted, the resistance of the two input ends of the amplifier is adjusted in the opposite direction.
The relation between the step length n of the resistance trimming and the digit m of the control signal is2mN; m and n are positive integers greater than 1.
Compared with the prior art, the invention has the advantages that:
the band-gap reference voltage source circuit realizes the band-gap reference voltage source circuit with ultrahigh precision and ultralow temperature drift coefficient, and can provide high-stability reference voltage for the circuit application with higher reference voltage requirement. Simulation results show that the temperature drift coefficient of the reference voltage output by the circuit is only 0.7ppm and the voltage change is only 0.4mV within a wide temperature range of-55-150 ℃. The circuit structure is easy to realize, has low process requirements and is suitable for various engineering applications.
It should be noted that the bandgap reference voltage source circuit with high-order temperature compensation shown in the present invention is only a preferred example for illustrating the present invention, and does not limit the protection scope of the present invention. Any changes made according to the scope of the present invention, including the replacement of PNP transistor with NPN transistor, the replacement of PMOS transistor with NMOS transistor, the changes to the local structure of the circuit, the changes to the circuit implementation method under the concept provided by the present invention, and other insubstantial substitutions, modifications, or embellishments, fall within the scope of the present invention.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

Claims (19)

1. A low temperature floating bandgap reference voltage circuit comprising:
the device comprises a self-biasing module, a band-gap reference core module and a voltage generation module;
the self-bias module provides bias voltage and bias current;
the self-bias module is used as a self-starting circuit in the power-on process of a power supply;
the band-gap reference core module is composed of Brokaw band-gap units and generates a primary reference voltage;
the band-gap reference core module comprises a base current correction resistor; adding a base current correction resistor into the base of a triode pair in the Brokaw band gap unit, and generating a reference voltage before compensation after correction operation is carried out; the correction resistor eliminates the influence of base current on the reference voltage, and the exponential characteristic of the base current is utilized to compensate the reference voltage;
the voltage generation module generates a final reference voltage;
the low-temperature drift band gap reference voltage circuit also comprises a curvature compensation module;
the curvature compensation module performs nonlinear curvature compensation on the reference voltage before compensation;
the nonlinear curvature compensation is that a curvature compensation module generates nonlinear curvature compensation current which generates voltage through a resistor for compensation;
the curvature compensation module comprises field effect transistors M1, M2, M3, M4, M7, M8, and M9; resistors R8, R9, and R10; an amplifier OP 2; the field effect transistors M1-M4, M7 and M8 are PMOS tubes; m9 is an NMOS tube; the curvature compensation module further comprises a resistor Rco;
one end of the resistor Rco is connected with the band gap reference core module, and the other end of the resistor Rco is grounded; the non-inverting terminal of the amplifier OP2 is connected with the node Vbgr, the inverting terminal node M and the output terminal of the amplifier is connected with the gate of the field effect transistor M9; the source of the field effect transistor M9 is connected with the power supply VDD, the drain and one end of the resistor R10 is connected with the node M; resistors R8-R10 are connected in series: the other end of the resistor R10 and one end of the resistor R9 are connected to the node H, the other end of the resistor R9 and one end of the resistor R8 are connected to the node L, and the other end of the resistor R8 is grounded;
the source electrode of the field effect transistor M1, the source electrode of the M2 and the drain electrode of the M7 are connected; the source electrode of the field effect transistor M3, the source electrode of the M4 and the drain electrode of the M8 are connected; the source stages of M7 and M8 are connected with a power supply VDD; the gates of M7 and M8 are connected to node Vpbias; the node Vpbias is the gate of the self-biasing module M5; the gate connection nodes VPTAT of M1 and M3; the gates of M2 and M4 are connected to nodes L and H, respectively; the drains of M2 and M3 are grounded; the drains of M1 and M4 are connected to one end of resistor Rco.
2. The low temperature floating bandgap reference voltage circuit of claim 1, wherein:
the M7 and the M8 have the same size.
3. The low temperature floating bandgap reference voltage circuit of claim 1, wherein:
the self-biasing module comprises field effect transistors M5 and M6; triodes Q3 and Q4, resistors R6 and R7; the field effect transistors M5 and M6 are PMOS tubes; the triode Q3 is a PNP triode and the triode Q4 is an NPN triode;
the source electrodes of the field effect transistors M6 and M5 are connected with a power supply VDD, and the grid electrode of the field effect transistor M5 is connected with the grid electrode of M6 and the drain electrode of M5; the field effect transistors M6 and M5 form a current mirror; the drain of the field effect transistor M6 and one end of the resistor R7 are connected to the point C and are used as the first output end of the self-bias module to be connected with the band-gap reference core module; the point B at the other end of the resistor R7 is connected with the base electrode of the triode Q4 and the emitting electrode of the triode Q3; an emitter E point of the triode Q4 is connected with one end of the resistor R6; the other end of the resistor R6 is grounded; the collector of the triode Q3 is grounded, and the base of the triode Q3 is used as a second output end of the self-bias module and is connected with the band-gap reference core module.
4. The low temperature floating bandgap reference voltage circuit of claim 3, wherein:
the M5 and the M6 have the same size.
5. The low temperature floating bandgap reference voltage circuit of claim 1, wherein:
the band-gap reference core module comprises triodes Q1, Q2 and Q5; resistors R01, R02, R1, R2 and R3; an amplifier OP 1; r3 is a base current correction resistor; the transistors Q1, Q2, and Q5 are NPN transistors;
the collector of the triode Q5 is connected with a power supply VDD, the base of the triode Q5 is connected with the first output end of the self-bias module, and the emitter D point of the triode Q5 is connected with one end of the resistors R01 and R02; the triodes Q1 and Q2 form a triode pair, collectors of the triodes Q1 and Q2 are respectively connected with the other ends of the resistors R01 and R02, collectors of the triodes Q1 and Q2 are respectively connected with the inverting input end and the non-inverting input end of the amplifier OP1, bases of the triodes Q1 and Q2 are connected together through R3, a point A of a base of the triode Q1 is connected with a second output end of the self-bias module and is used as a first output end Vbgr of the band-gap reference core module to be connected with the voltage generation module; the output end of the amplifier OP1 is used as the second output end of the band-gap reference core module and is connected with the voltage generation module; an emitter of the triode Q1 is connected with one end of the resistor R2; an emitter of the triode Q2 is connected with one end of the resistor R2 through the resistor R1; the other end of the resistor R2 is connected to ground.
6. The low temperature floating bandgap reference voltage circuit of claim 5, wherein:
the band-gap reference core module comprises trimming circuits Rt1 and Rt2, and contact point ports are respectively connected with input ends Vinp and Vinn of an amplifier OP 1.
7. The low temperature floating bandgap reference voltage circuit of claim 1, wherein:
the voltage generation module comprises a field effect transistor M10, a resistor R4 and a resistor R5; the field effect transistor M10 is a PMOS tube;
the source of the field effect transistor M10 is connected with a power supply VDD, the gate of the field effect transistor M10 is connected with the second output end of the band-gap reference core module, the drain of the field effect transistor M10 is connected with one end of the resistor R4 together to be output as a final reference voltage Vref; the other end of the resistor R4 and one end of the resistor R5 are connected with a first output end of the band-gap reference core module; the other end of the resistor R5 is connected to ground.
8. The low temperature floating bandgap reference voltage circuit of claim 7, wherein:
the resistor R5 in the voltage generation module comprises a trimming circuit Rt3, and the resistor R5 is a potentiometer Rt3 and a potentiometer R50 which are connected in series.
9. The low temperature floating bandgap reference voltage circuit of any of claims 6 or 8, wherein:
the trimming circuit comprises trimming modules T0-Tn with n bits connected in series; each fine tuning module comprises a logic control unit L, a switch device K and a fine tuning resistor RT; the total number of the logic control unit L, the switching device K and the trimming resistor RT of the n-bit trimming module is K0 to Kn, L0 to Ln and RT0 to RTn; the trimming circuit also comprises a digit m of a control signal, and the control signal is connected with the logic control unit L; n and m are positive integers greater than 1;
the output of the logic control unit L controls the on state of the switching device K, and when the switching device K of the corresponding node is turned on, the node is connected to the output terminal; when the switching device K is turned off, the corresponding node is disconnected from the output terminal.
10. A method for generating a low temperature floating bandgap reference voltage of the low temperature floating bandgap reference voltage circuit of any of claims 1 to 9, said method comprising the steps of:
step 1: generating a primary reference voltage;
step 2: generating a reference voltage before compensation by base current correction and a primary reference voltage; the base current correction is carried out through a calibration resistor; the correction resistor eliminates the influence of base current on the reference voltage, and the exponential characteristic of the base current is utilized to compensate the reference voltage;
and step 3: generating a low temperature drift band gap reference voltage;
after the step 2, carrying out nonlinear compensation on the reference voltage before compensation; the nonlinear curvature compensation is that the curvature compensation module generates nonlinear curvature compensation current which generates voltage through a resistor for compensation.
11. The method of generating a low temperature floating bandgap reference voltage of claim 10, wherein:
the nonlinear compensation of the reference voltage before compensation is dynamic adjustment compensation;
the dynamic adjustment compensation is as follows: and monitoring the change of the positive temperature coefficient voltage VPTAT, and continuously adjusting the magnitude of the compensation current to compensate the high-order term in the band gap reference BE junction voltage VBE.
12. The method of generating a low temperature floating bandgap reference voltage of claim 11, wherein:
the method further comprises a trimming step, wherein the trimming step refers to trimming the resistor.
13. The method of low temperature floating bandgap reference voltage generation according to claim 12, wherein:
the resistance trimming is realized by different access of series resistors.
14. The method of generating a low temperature floating bandgap reference voltage of claim 13, wherein:
step length n of the resistor trimming and the digit m of the control signal;
m and n have a relationship of 2m＝n；
m and n are positive integers greater than 1.
15. The method of generating a low temperature floating bandgap reference voltage of claim 12, wherein:
and the resistance trimming is to perform resistance trimming on the input end of the amplifier in the generation of the primary reference voltage.
16. The method of generating a low temperature floating bandgap reference voltage of claim 13, wherein:
when the resistance of the input end of the amplifier in the generation of the primary reference voltage is adjusted, the resistance of the two input ends of the amplifier is adjusted in the opposite direction.
17. The method of generating a low temperature floating bandgap reference voltage of claim 12, wherein:
and the resistance trimming is to perform resistance trimming on a proportional resistor generating the low-temperature drift band-gap reference voltage.
18. A chip using the method for generating a low temperature-drift bandgap reference voltage according to any one of claims 10 to 17, wherein:
the low-temperature drift band-gap reference voltage circuit and the method are applied to a power management chip.
19. A chip using the method for generating a low temperature-drift bandgap reference voltage according to any one of claims 10 to 17, wherein:
the low temperature drift band gap reference voltage circuit and the method are applied to an analog-to-digital converter, a digital-to-analog converter, a dynamic memory or a Flash memory chip.
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