CN116504827B - Hemt外延片及其制备方法、hemt - Google Patents
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Abstract
本发明公开了一种HEMT外延片及其制备方法、HEMT,所述HEMT外延片包括衬底及依次层叠于所述衬底上的电子阻挡层、高阻层、沟道层、势垒层、极化层和GaN帽层;所述电子阻挡层包括依次层叠在所述衬底上的掺Mg的GaN层、BN层和Si3N4层;所述极化层包括依次层叠在所述势垒层上的GaN层、YAlN层和AlGaN层。本发明提供的HEMT外延片能限制二维电子气,具有更好的关断能力和更好的开启能力,并降低短沟道效应的影响和更低的表面接触电阻。
Description
技术领域
本发明涉及光电技术领域,尤其涉及一种HEMT外延片及其制备方法、HEMT。
背景技术
随着科技的发展,高性能高效率的半导体电力电子器件在当今社会显得尤为重要。传统的Si基半导体电力电子器件由于材料本身的限制,其性能和效率已经难以有很大的提高。以GaN为代表的宽禁带半导体由于具有大禁带宽度、高击穿场强、高电子迁移率等优良特性,十分适合制备高性能高效率的电力电子器件。GaN异质结场效应晶体管(HFET)常常被称为GaN高电子迁移率晶体管(HEMT)。而在AlGaN/GaN的HFET中,2DEG(二维电子气)载流子密度由AlGaN势垒层的成分和厚度决定,对于P-GaN栅HFET,P-GaN层能耗尽2DEG,但是,要确保2DEG在零栅极偏置时完全耗尽,即获得增强型器件,或者说为了获得较大阈值的增强型器件,如大于1V阈值电压,AlGaN势垒层必须足够薄,这就会限制非栅控接入区域中的载流子密度。
发明内容
本发明所要解决的技术问题在于,提供一种HEMT外延片,其限制二维电子气,具有更好的关断能力和更好的开启能力,并降低短沟道效应的影响和更低的表面接触电阻。
本发明所要解决的技术问题还在于,提供一种HEMT外延片的制备方法,其工艺简单,能够稳定制得发光效率良好的HEMT外延片。
为了解决上述技术问题,本发明提供了一种HEMT外延片,包括衬底及依次层叠于所述衬底上的电子阻挡层、高阻层、沟道层、势垒层、极化层和GaN帽层;
所述电子阻挡层包括依次层叠在所述衬底上的掺Mg的GaN层、BN层和Si3N4层;
所述极化层包括依次层叠在所述势垒层上的GaN层、YAlN层和AlGaN层;
所述掺Mg的GaN层的Mg掺杂浓度为1×1016atoms/cm3~2×1017atoms/cm3。
在一种实施方式中,所述掺Mg的GaN层的厚度为100nm~700nm;
所述BN层的厚度为100nm~200nm;
所述Si3N4层的厚度为100nm~200nm。
在一种实施方式中,所述极化层的厚度为10nm~20nm。
在一种实施方式中,所述YAlN层的Y组分为0.1~0.2。
为解决上述问题,本发明还提供了一种HEMT外延片的制备方法,包括以下步骤:
S1、准备衬底;
S2、在所述衬底上依次沉积电子阻挡层、高阻层、沟道层、势垒层、极化层和GaN帽层;
所述电子阻挡层包括依次层叠在所述衬底上的掺Mg的GaN层、BN层和Si3N4层;
所述极化层包括依次层叠在所述势垒层上的GaN层、YAlN层和AlGaN层;
所述掺Mg的GaN层的Mg掺杂浓度为1×1016atoms/cm3~2×1017atoms/cm3。
在一种实施方式中,所述掺Mg的GaN层的生长温度为650℃~800℃;
所述BN层的生长温度为950℃~1000℃;
所述Si3N4层的生长温度为950℃~1000℃;
所述极化层的生长温度为1000℃~1050℃。
在一种实施方式中,所述掺Mg的GaN层的生长压力为260torr~500torr;
所述BN层的生长压力为100torr~200torr;
所述Si3N4层的生长压力为100torr~200torr;
所述极化层的生长压力为50torr~200torr。
在一种实施方式中,所述掺Mg的GaN层的V/III比为200~1000;
所述BN层的V/III比为200~1000;
所述极化层的V/III比为500~1000。
相应地,本发明还提供了一种HEMT,所述HEMT包括上述的HEMT外延片。
实施本发明,具有如下有益效果:
本发明提供的HEMT外延片,其设有特定结构的电子阻挡层和极化层,所述电子阻挡层包括依次层叠在所述衬底上的掺Mg的GaN层、BN层和Si3N4层;所述极化层包括依次层叠在所述势垒层上的GaN层、YAlN层和AlGaN层。
所述电子阻挡层中,掺Mg的GaN层可以限制由于衬底所带来的电子,降低静电击穿的风险,同时Mg掺杂可以减少电子的移动速度。BN层能够使掺Mg的GaN层上的三维成核层形成的岛之间加速合并,形成高质量的电子阻挡层,进一步降低与衬底之间的晶格失配和热失配,从而减少位错的产生和裂纹,降低位错的产生。Si3N4层改变位错延伸方向,使之相交发生湮灭,减少漏电通道。
所述极化层中GaN层、YAlN层和AlGaN层共同构成一个特殊结构的异质结,增加了器件的自发和压电电荷极化,即应变相关的电荷极化,使得其二维电子气(2DEG)薄层电荷的载流子密度提高数倍,与此同时,应变驰豫问题也得到了很好的控制,这一特殊的异质结结构增强了器件射频性能和可靠性。
附图说明
图1为本发明提供的HEMT外延片的结构示意图;
图2为本发明提供的HEMT外延片的制备方法的流程图;
图3为本发明提供的HEMT外延片的制备方法的步骤S2的流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚,下面对本发明作进一步地详细描述。
除非另外说明或存在矛盾之处,本文中使用的术语或短语具有以下含义:
本发明中,“优选”仅为描述效果更好的实施方式或实施例,应当理解,并不构成对本发明保护范围的限制。
本发明中,以开放式描述的技术特征中,包括所列举特征组成的封闭式技术方案,也包括包含所列举特征的开放式技术方案。
本发明中,涉及到数值区间,如无特别说明,则包括数值区间的两个端点。
为解决上述问题,本发明提供了一种HEMT外延片,如图1所示,包括衬底1及依次层叠于所述衬底1上的电子阻挡层2、高阻层3、沟道层4、势垒层5、极化层6和GaN帽层7;
所述电子阻挡层2包括依次层叠在所述衬底1上的掺Mg的GaN层21、BN层22和Si3N4层23;
所述极化层6包括依次层叠在所述势垒层5上的GaN层61、YAlN层62和AlGaN层63;
所述掺Mg的GaN层的Mg掺杂浓度为1×1016atoms/cm3~2×1017atoms/cm3。
本发明提供的HEMT外延片,其在衬底上设置特定结构的电子阻挡层,下文对所述电子阻挡层的具体结构进行进一步描述。
在一种实施方式中,所述掺Mg的GaN层21的厚度为100nm~700nm;所述掺Mg的GaN层21的示例性厚度为200nm、300nm、500nm、600nm,但不限于此。优选地,所述掺Mg的GaN层21的Mg掺杂浓度为5×1016atoms/cm3~1×1017atoms/cm3。在一种实施方式中,所述BN层22的厚度为100nm~200nm;所述BN层22的示例性厚度为120nm、140nm、160nm、180nm,但不限于此。在一种实施方式中,所述Si3N4层23的厚度为100nm~200nm;所述Si3N4层23的示例性厚度为120nm、140nm、160nm、180nm,但不限于此。
所述电子阻挡层中,掺Mg的GaN层可以限制由于衬底所带来的电子,降低静电击穿的风险,同时Mg掺杂可以减少电子的移动速度。BN层能够使掺Mg的GaN层上的三维成核层形成的岛之间加速合并,形成高质量的电子阻挡层,进一步降低与衬底之间的晶格失配和热失配,从而减少位错的产生和裂纹,降低位错的产生。Si3N4层改变位错延伸方向,使之相交发生湮灭,减少漏电通道。
本发明提供的HEMT外延片,其在势垒层5上设置特定结构的极化层6,下文对所述极化层6的具体结构进行进一步描述。
在一种实施方式中,所述极化层6的厚度为10nm~20nm;所述极化层6的示例性厚度为12nm、14nm、16nm、18nm,但不限于此。在一种实施方式中,所述YAlN层62的Y组分为0.1~0.2。优选地,所述YAlN层62的Y组分为0.11~0.19。所述极化层中GaN层61、YAlN层62和AlGaN层63共同构成一个特殊结构的异质结,增加了器件的自发和压电电荷极化,即应变相关的电荷极化,使得其二维电子气(2DEG)薄层电荷的载流子密度提高数倍,与此同时,应变驰豫问题也得到了很好的控制,这一特殊的异质结结构增强了器件射频性能和可靠性。
相应地,本发明提供了一种HEMT外延片的制备方法,如图2所示,包括以下步骤:
S1、准备衬底1;
在一种实施方式中,所述衬底可选用硅衬底。
S2、在所述衬底1上依次沉积电子阻挡层2、高阻层3、沟道层4、势垒层5、极化层6和GaN帽层7。
如图3所示,步骤S2包括以下步骤:
S21、在衬底1上沉积电子阻挡层2。
在一种实施方式中,所述掺Mg的GaN层的生长温度为650℃~800℃;所述BN层的生长温度为950℃~1000℃;所述Si3N4层的生长温度为950℃~1000℃;所述掺Mg的GaN层的生长压力为260torr~500torr;所述BN层的生长压力为100torr~200torr;所述Si3N4层的生长压力为100torr~200torr;所述掺Mg的GaN层的V/III比为200~1000;所述BN层的V/III比为200~1000。
S22、在电子阻挡层2上沉积高阻层3。
在一种实施方式中,控制生长温度在1000℃~1020℃,生长压力在50torr~200torr,通入Ga源和乙烯和NH3,沉积自掺碳高阻GaN外延层,其厚度为2μm~3μm,碳掺杂浓度为5×1018atoms/cm3~1×1019atoms/cm3。
优选地,控制生长温度在1010℃,生长压力在150torr,厚度为2.5μm,碳掺杂浓度为5×1018atoms/cm3。
S23、在高阻层3上沉积沟道层4。
在一种实施方式中,控制生长温度在1030℃~1080℃,反应腔压力维持100torr~300torr,通入NH3、TMGa,生长厚度为200nm~500nm的GaN沟道层。
优选地,控制生长温度在1050℃,反应腔压力维持200torr,通入NH3、TMGa,生长厚度为350nm的GaN沟道层。
S24、在沟道层4上沉积势垒层5。
在一种实施方式中,控制生长温度在1030℃~1080℃,反应腔压力维持在50torr~200torr,通入NH3、TMGa、TMAl,生长厚度为20nm~30nm的AlyGa1-yN势垒层,y为0.15~0.30。
优选地,控制生长温度在1050℃,反应腔压力维持在150torr,通入NH3、TMGa、TMAl,生长厚度为25nm的AlyGa1-yN势垒层,y为0.25。
S25、在势垒层5上沉积极化层6。
在一种实施方式中,所述极化层的生长温度为1000℃~1050℃,所述极化层的生长压力为50torr~200torr,所述极化层的V/III比为500~1000,通入相应的Ga源、Al源、Y源或N源,完成极化层的沉积。
S26、在极化层6上沉积GaN帽层7。
在一种实施方式中,控制反应腔温度在1030℃~1080℃,反应腔压力维持在50torr~200 torr,通入NH3、TMGa,生长厚度为2nm~5nm的GaN帽层。
优选地,控制反应腔温度在1060℃,反应腔压力维持在150 torr,通入NH3、TMGa,生长厚度为5nm的GaN帽层。
相应地,本发明还提供了一种HEMT,所述HEMT包括上述的HEMT外延片。所述HEMT的光电效率得到有效提升,且其他项电学性能良好。
下面以具体实施例进一步说明本发明:
实施例1
本实施例提供一种HEMT外延片,包括衬底及依次层叠于所述衬底上的电子阻挡层、高阻层、沟道层、势垒层、极化层和GaN帽层;
所述电子阻挡层包括依次层叠在所述衬底上的掺Mg的GaN层、BN层和Si3N4层;
所述极化层包括依次层叠在所述势垒层上的GaN层、YAlN层和AlGaN层。
其中,所述掺Mg的GaN层的厚度为400nm,所述BN层的厚度为150nm,所述Si3N4层的厚度为150nm,极化层的厚度为15nm,所述掺Mg的GaN层的Mg掺杂浓度为1×1017atoms/cm3,所述YAlN层的Y组分为0.15。
实施例2
本实施例提供一种HEMT外延片,与实施例1不同之处在于:所述掺Mg的GaN层的厚度为100nm,所述BN层的厚度为100nm,所述Si3N4层的厚度为100nm。其余皆与实施例1相同。
实施例3
本实施例提供一种HEMT外延片,与实施例1不同之处在于:极化层的厚度为20nm。其余皆与实施例1相同。
对比例1
本对比例与实施例1不同之处在于,所述电子阻挡层不包括Mg的GaN层,仅包括BN层和Si3N4层,其余皆与实施例1相同。
对比例2
本对比例与实施例1不同之处在于,所述电子阻挡层不包括BN层,仅包括Mg的GaN层和Si3N4层,其余皆与实施例1相同。
对比例3
本对比例与实施例1不同之处在于,所述电子阻挡层不包括Si3N4层,仅包括BN层和Mg的GaN层,其余皆与实施例1相同。
对比例4
本对比例与实施例1不同之处在于,所述极化层不包括GaN层,仅包括YAlN层和AlGaN层,其余皆与实施例1相同。
对比例5
本对比例与实施例1不同之处在于,所述极化层不包括YAlN层,仅包括GaN层和AlGaN层,其余皆与实施例1相同。
对比例6
本对比例与实施例1不同之处在于,所述极化层不包括AlGaN层,仅包括GaN层和YAlN层,其余皆与实施例1相同。
以实施例1~实施例3和对比例1~对比例6制得HEMT外延片使用相同芯片工艺条件制备成10×24mil的芯片,分别抽取300颗HEMT芯片,测试芯片的光电性能,以对比例1为基础,计算各实施例和对比例的抗静电能力提升率和外观良率提升率,具体测试结果如表1所示。
表1实施例1~实施例3和对比例1~对比例6制得HEMT的性能测试结果
由上述结果可知,本发明提供的HEMT外延片,其设有特定结构的电子阻挡层和极化层,所述电子阻挡层包括依次层叠在所述衬底上的掺Mg的GaN层、BN层和Si3N4层;所述极化层包括依次层叠在所述势垒层上的GaN层、YAlN层和AlGaN层。
所述电子阻挡层中,掺Mg的GaN层可以限制由于衬底所带来的电子,降低静电击穿的风险,同时Mg掺杂可以减少电子的移动速度。BN层能够使掺Mg的GaN层上的三维成核层形成的岛之间加速合并,形成高质量的电子阻挡层,进一步降低与衬底之间的晶格失配和热失配,从而减少位错的产生和裂纹,降低位错的产生。Si3N4层改变位错延伸方向,使之相交发生湮灭,减少漏电通道。
所述极化层中GaN层、YAlN层和AlGaN层共同构成一个特殊结构的异质结,增加了器件的自发和压电电荷极化,即应变相关的电荷极化,使得其二维电子气(2DEG)薄层电荷的载流子密度提高数倍,与此同时,应变驰豫问题也得到了很好的控制,这一特殊的异质结结构增强了器件射频性能和可靠性。
以上所述是发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也视为本发明的保护范围。
Claims (9)
1.一种HEMT外延片,其特征在于,包括衬底及依次层叠于所述衬底上的电子阻挡层、高阻层、沟道层、势垒层、极化层和GaN帽层;
所述电子阻挡层包括依次层叠在所述衬底上的掺Mg的GaN层、BN层和Si3N4层;
所述极化层包括依次层叠在所述势垒层上的GaN层、YAlN层和AlGaN层;
所述掺Mg的GaN层的Mg掺杂浓度为1×1016atoms/cm3~2×1017atoms/cm3。
2.如权利要求1所述的HEMT外延片,其特征在于,所述掺Mg的GaN层的厚度为100nm~700nm;
所述BN层的厚度为100nm~200nm;
所述Si3N4层的厚度为100nm~200nm。
3.如权利要求1所述的HEMT外延片,其特征在于,所述极化层的厚度为10nm~20nm。
4.如权利要求1所述的HEMT外延片,其特征在于,所述YAlN层的Y组分为0.1~0.2。
5.一种如权利要求1~4任一项所述的HEMT外延片的制备方法,其特征在于,包括以下步骤:
S1、准备衬底;
S2、在所述衬底上依次沉积电子阻挡层、高阻层、沟道层、势垒层、极化层和GaN帽层;
所述电子阻挡层包括依次层叠在所述衬底上的掺Mg的GaN层、BN层和Si3N4层;
所述极化层包括依次层叠在所述势垒层上的GaN层、YAlN层和AlGaN层;
所述掺Mg的GaN层的Mg掺杂浓度为1×1016atoms/cm3~2×1017atoms/cm3。
6.如权利要求5所述的HEMT外延片的制备方法,其特征在于,所述掺Mg的GaN层的生长温度为650℃~800℃;
所述BN层的生长温度为950℃~1000℃;
所述Si3N4层的生长温度为950℃~1000℃;
所述极化层的生长温度为1000℃~1050℃。
7.如权利要求5所述的HEMT外延片的制备方法,其特征在于,所述掺Mg的GaN层的生长压力为260torr~500torr;
所述BN层的生长压力为100torr~200torr;
所述Si3N4层的生长压力为100torr~200torr;
所述极化层的生长压力为50torr~200torr。
8.如权利要求5所述的HEMT外延片的制备方法,其特征在于,所述掺Mg的GaN层的V/III比为200~1000;
所述BN层的V/III比为200~1000;
所述极化层的V/III比为500~1000。
9.一种HEMT,其特征在于,所述HEMT包括如权利要求1~4任一项所述的HEMT外延片。
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