CN116436420A - High-performance low-noise amplifier - Google Patents
High-performance low-noise amplifier Download PDFInfo
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- CN116436420A CN116436420A CN202310708018.6A CN202310708018A CN116436420A CN 116436420 A CN116436420 A CN 116436420A CN 202310708018 A CN202310708018 A CN 202310708018A CN 116436420 A CN116436420 A CN 116436420A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
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Abstract
The invention belongs to the technical field of amplifiers, in particular to a high-performance low-noise amplifier, which comprises a Bypass channel circuit, wherein when the control voltage is high, the Bypass channel circuit works in a Bypass mode, and a radio frequency signal input end is fed into three serially connected depletion type PHEMT pipes through a blocking capacitor C3 and is fed into an output end RFOUT through a blocking capacitor C4; when the control voltage is at a low level, operating in an LNA mode; the signal amplifying circuit comprises an enhanced PHEMT tube M1, wherein two ends of the enhanced PHEMT tube M1 are connected with a radio frequency signal input end and a radio frequency signal output end to amplify a radio frequency signal; the linearity enhancement circuit is connected with the source electrode of the enhanced PHEMT tube M1 in the signal amplification circuit and provides a low negative gate source voltage for the enhanced PHEMT tube M1. The Bypass scheme of the invention has the advantage that the gain drop amount is less than 0.5dB when the output power is increased to 10 dBm. A nearly double linearity improvement can be achieved.
Description
Technical Field
The invention belongs to the technical field of amplifiers, and particularly relates to a high-performance low-noise amplifier.
Background
In modern wireless communication system receivers, in order to be able to withstand the adverse effects of channel saturation or signal compression and even device damage that may be caused by large signal inputs, it is required that the low noise amplifier chip must be able to pass the large signal at the input directly to the output, i.e. Bypass function, as shown in fig. 1.
Under GaAs technology, the Bypass channel often employs a depletion Mode PHEMT tube (deeted Mode) to implement an ultra low loss rf switch, as shown in fig. 2. M3, M4, M5 are 3 depletion type PHEMT pipes connected in series, the resistor R3, the resistor R4, the resistor R5 are respectively the grid bias resistor of depletion type PHEMT pipe M3, depletion type PHEMT pipe M4, depletion type PHEMT pipe M5, the control voltage EN_BYP connects the control voltage to the grid of depletion type PHEMT pipe M3, depletion type PHEMT pipe M4, depletion type PHEMT pipe M5 through the resistor R3, the resistor R4, the resistor R5 to control the on or off state of depletion type PHEMT pipe M3, depletion type PHEMT pipe M4, depletion type PHEMT pipe M5. When EN_BYP is at a high level, the depletion type PHEMT tube M3, the depletion type PHEMT tube M4 and the depletion type PHEMT tube M5 are started, and the amplifier works in a Bypass mode; when en_byp is low, depletion type PHEMT tube M3, depletion type PHEMT tube M4, depletion type PHEMT tube M5 is turned off and the amplifier operates in LNA mode. C3 and C4 are blocking capacitors, and in the Bypass mode, the radio frequency signal RFIN is fed into the switching depletion type PHEMT tube M3, the depletion type PHEMT tube M4 and the depletion type PHEMT tube M5 through the blocking capacitor C3 and then is fed into the output end RFOUT through the blocking capacitor C4.
In general, there is a large leakage current in the gate of the enhanced PHEMT in GaAs process, and especially when the size of the enhanced PHEMT is large, the leakage current increases to several tens microamps, which makes the off state of the enhanced PHEMT very undesirable. In order to meet the amplification gain requirement in the LNA mode, the size of the amplifying tube in the signal amplifying circuit is usually relatively large, and when the amplifier works in the Bypass mode, the gate of the amplifying tube is connected to the ground through a resistor, but due to the leakage current of the gate of the amplifying tube, a part of radio frequency signals flow to the gate of the amplifying tube, so that great harmonic distortion is caused, and the linearity of the amplifier in the Bypass mode is greatly limited.
Ideally, the gain versus output power curve approaches a straight line, i.e., the gain does not change with increasing output power, but rather, the gain decreases with increasing output power due to non-linearities in the circuit. The effect achieved by the conventional Bypass scheme is that as shown in fig. 3, when the output power is increased from-10 dBm to 0dBm, the gain is drastically reduced, and the linearity is seriously deteriorated.
Disclosure of Invention
The invention aims to solve the technical problem that serious harmonic distortion occurs when an amplifier works in a Bypass mode, so that linearity is reduced sharply, and provides a high-performance low-noise amplifier.
The present invention has been achieved in such a way that,
a high performance low noise amplifier comprising:
when the control voltage EN_BYP is high, the Bypass channel circuit works in a Bypass mode, and a radio frequency signal input end RFIN is fed into three serially connected depletion type PHEMT tubes through a blocking capacitor C3 and is fed into an output end RFOUT through a blocking capacitor C4; when the control voltage en_byp is low level, operating in the LNA mode;
the signal amplifying circuit comprises an enhanced PHEMT tube M1, two ends of which are connected with a radio frequency signal input end RFIN and an output end RFOUT for amplifying radio frequency signals;
the linearity enhancement circuit is connected with the source electrode of the enhanced PHEMT tube M1 in the signal amplification circuit and provides a low negative gate source voltage for the enhanced PHEMT tube M1.
Further, the signal amplifying circuit comprises an enhanced PHEMT tube M1, an enhanced logic tube M7, an inductor Ls, an inductor Ld, a blocking capacitor C1, a blocking capacitor C2 and a resistor R1; wherein,,
the grid electrode of the enhanced PHEMT tube M1 is connected to a radio frequency signal input end RFIN through a blocking capacitor C1;
the drain electrode of the enhanced PHEMT tube M1 is connected to the output end RFOUT through a blocking capacitor C2 and is connected to a power supply VDD through an inductor Ld;
the grid electrode of the enhanced PHEMT tube M1 is connected with bias voltage Vb1 through a resistor R1 and is connected to the drain electrode of an enhanced logic tube M7, the source electrode of the enhanced logic tube M7 is grounded, and the grid electrode of the enhanced logic tube M7 is connected with control voltage EN_BYP;
the source electrode of the enhanced PHEMT tube M1 is connected with a linearity enhancement circuit through an inductance Ls.
Further, the linearity enhancement circuit includes: an enhanced PHEMT tube M2, an enhanced logic tube M6, a resistor R2 and a diode D1, wherein,
the drain electrode of the enhanced PHEMT tube M2 is connected to the drain electrode of the enhanced logic tube M6 through a diode D1, the source electrode of the enhanced PHEMT tube M2 is grounded, and the grid electrode of the enhanced PHEMT tube M2 is connected with a control voltage EN_LNA; the source electrode of the enhanced logic tube M6 is grounded, the grid electrode of the enhanced logic tube M6 is connected with the control voltage EN_LNA, and the drain electrode of the enhanced logic tube M6 is connected with a power supply through a resistor R2.
Further, the control voltage en_lna is inverted from the control voltage en_byp.
Further, when the low noise amplifier is operated in the LNA mode, when the control voltage en_byp is at a low level, the control voltage en_lna is at a high level, and the gate voltage Vg1 of the enhanced PHEMT tube M1 is equal to the bias voltage Vb1; the enhanced PHEMT tube M2 and the enhanced logic tube M6 are turned on, the drain voltage of the enhanced logic tube M6 and the drain voltage Vd2 of the enhanced PHEMT tube M2 are grounded, and the diode D1 is not conducted.
Further, when the low noise amplifier works in the Bypass mode, the control voltage en_byp is at a high level, the control voltage en_lna is at a low level, and the gate voltage Vg 1=0v of the enhanced PHEMT tube M1; the enhanced PHEMT transistor M2 and the enhanced logic transistor M6 are turned off, the power supply voltage VDD generates a high voltage Vd2 at the drain of the enhanced PHEMT transistor M2 through the resistor R2 and the diode D1, and a low negative voltage difference Vgs1 is generated between the gate voltage and the source voltage of the enhanced PHEMT transistor M1.
Compared with the prior art, the invention has the beneficial effects that:
the linearity enhancement circuit adopted by the invention can greatly improve the linearity performance of the amplifier in the Bypass mode. As shown in fig. 5, the lower curve is the gain versus output power curve in the conventional Bypass scheme, and the upper curve is the gain versus output power curve in the Bypass scheme of the present invention. When the output power is increased to 10dBm, the gain of the traditional Bypass scheme is reduced by nearly 1.5dB, and the gain reduction of the Bypass scheme of the invention is less than 0.5dB. From the comparison graph of the traditional Bypass scheme curve, the invention can realize nearly double linearity improvement.
Drawings
FIG. 1 is a schematic diagram of a Bypass function in the prior art;
FIG. 2 is a schematic diagram of a conventional amplifier Bypass mode and LNA mode integrated circuit in the prior art;
FIG. 3 is a graph of linearity degradation in Bypass mode for a conventional implementation of the prior art;
FIG. 4 is a schematic circuit diagram of a low noise amplifier Bypass mode linearity enhancement circuit according to an embodiment of the present invention;
fig. 5 illustrates a linearity enhancement effect achieved by the circuit according to the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the following examples in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 4, a high performance low noise amplifier, comprising:
the Bypass channel circuit 1 works in Bypass mode when the control voltage EN_BYP is high, and the radio frequency signal input end RFIN is fed into three serially connected depletion type PHEMT tubes through a blocking capacitor C3 and is fed into the output end RFOUT through a blocking capacitor C4; when the control voltage en_byp is low level, operating in the LNA mode;
the signal amplifying circuit 2 comprises an enhanced PHEMT tube M1, two ends of which are connected with a radio frequency signal input end RFIN and an output end RFOUT and amplify radio frequency signals;
the linearity enhancement circuit 3 is connected with the source electrode of the enhanced PHEMT tube M1 in the signal amplification circuit and provides a low negative gate source voltage for the enhanced PHEMT tube M1.
The signal amplifying circuit of the low noise amplifier provided by the invention consists of an enhanced PHEMT tube M1, an enhanced logic tube M7, an inductor Ls, an inductor Ld, a capacitor C1, a capacitor C2 and a resistor R1.
The grid electrode of the enhanced PHEMT tube M1 is connected to a radio frequency signal input end RFIN through a blocking capacitor C1;
the drain electrode of the enhanced PHEMT tube M1 is connected to the output end RFOUT through a blocking capacitor C2 and is connected to a power supply VDD through an inductor Ld;
the grid electrode of the enhanced PHEMT tube M1 is connected with bias voltage Vb1 through a resistor R1 and is connected to the drain electrode of an enhanced logic tube M7, the source electrode of the enhanced logic tube M7 is grounded, and the grid electrode of the enhanced logic tube M7 is connected with control voltage EN_BYP;
the source electrode of the enhanced PHEMT tube M1 is connected with a linearity enhancement circuit through an inductance Ls.
When the control voltage en_byp is at a low level, the enhanced logic tube M7 is turned off, and the bias voltage Vb1 is applied to the gate of the enhanced PHEMT tube M1 through the bias resistor R1, so that the enhanced PHEMT tube M1 operates in a signal amplifying state. The radiofrequency signal RFIN is fed into the grid electrode of the enhanced PHEMT tube M1 through the blocking capacitor C1, then amplified to the drain electrode of the enhanced PHEMT tube M1 through the enhanced PHEMT tube M1, and finally fed into the output end RFOUT through the blocking capacitor C2. The source of the enhanced PHEMT tube M1 is connected to the linearity enhancement circuit through an inductance Ls, and the drain of the enhanced PHEMT tube M1 is connected to the power supply VDD through an inductance Ld to provide sufficient signal amplification gain.
When the control voltage en_byp is at a high level, the enhancement logic tube M7 is turned on, and the bias voltage Vb1 is connected to the ground through the enhancement logic tube M7, so that the gate Vg1 of the enhancement PHEMT tube M1 is also connected to the ground through the resistor R1 and the enhancement logic tube M7, thereby turning off the enhancement PHEMT tube M1.
The linearity enhancement circuit of the present invention includes: an enhanced PHEMT tube M2, an enhanced logic tube M6, a resistor R2 and a diode D1, wherein,
the drain electrode of the enhanced PHEMT tube M2 is connected to the drain electrode of the enhanced logic tube M6 through a diode D1, the source electrode of the enhanced PHEMT tube M2 is grounded, and the grid electrode of the enhanced PHEMT tube M2 is connected with a control voltage EN_LNA; the source electrode of the enhanced logic tube M6 is grounded, the grid electrode of the enhanced logic tube M6 is connected with the control voltage EN_LNA, and the drain electrode of the enhanced logic tube M6 is connected with a power supply through a resistor R2.
An enhanced PHEMT tube is inserted between the inductor Ls and ground, with its drain connected to the inductor Ls, its source connected to ground, and its gate connected to the control voltage en_lna. The control voltage en_lna is inverted from the control voltage en_byp, and when the control voltage en_byp is at a high level, the control voltage en_lna is at a low level; when the control voltage en_byp is at a low level, the control voltage en_lna is at a high level. The enhanced logic tube M6, the resistor R2 and the diode D1 form an enhanced PHEMT tube M2 drain voltage Vd2 generating circuit.
When the low noise amplifier works in the LNA mode, when the control voltage EN_BYP is low, the control voltage EN_LNA is high, and the gate voltage Vg1 of the enhanced PHEMT tube M1 is equal to the bias voltage Vb1; the enhanced PHEMT tube M2 and the enhanced logic tube M6 are turned on, the drain voltage of the enhanced logic tube M6 and the drain voltage Vd2 of the enhanced PHEMT tube M2 are grounded, and the diode D1 is not conducted.
When the low noise amplifier works in the Bypass mode, the control voltage EN_BYP is high level, the control voltage EN_LNA is low level, and the gate voltage Vg1=0V of the enhanced PHEMT tube M1; m2, M6 are turned off, the power supply voltage VDD generates a relatively high voltage Vd2 at the drain of the enhancement mode PHEMT transistor M2 through the resistor R2 and the diode D1, which is approximately equal to VDD-Vd1 (Vd 1 is the on voltage of the diode D1), if vdd=5v, vd1=0.7v, vd2=5v-0.7v=4.3v, and m1 source voltage Vs 1=vd2=4.3v. The difference Vgs1 between the gate voltage and the source voltage of M1 is equal to Vg1-Vs1 = 0V-4.3V = -4.3V. In Bypass mode, vgs 1=0v of the enhancement mode PHEMT tube M1 in fig. 2, the presence of gate leakage current causes incomplete turn-off of enhancement mode PHEMT tube M1; in the scheme of the invention, the Vgs1 of the enhanced PHEMT tube M1 is a very low negative voltage, so that the turn-off state of the enhanced PHEMT tube M1 is ideal enough, and the harmonic distortion and linearity performance are improved.
It should be noted that, in fig. 4, two control voltages en_byp are controlled by one control signal, and two control voltages en_lna are controlled by one control signal. But the control voltage en_lna is inverted from the control voltage en_byp, and when the control voltage en_byp is at a high level, the control voltage en_lna is at a low level, and vice versa.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (6)
1. A high performance low noise amplifier comprising:
when the control voltage EN_BYP is high, the Bypass channel circuit works in a Bypass mode, and a radio frequency signal input end RFIN is fed into three serially connected depletion type PHEMT tubes through a blocking capacitor C3 and is fed into an output end RFOUT through a blocking capacitor C4; when the control voltage en_byp is low level, operating in the LNA mode;
the signal amplifying circuit comprises an enhanced PHEMT tube M1, two ends of which are connected with a radio frequency signal input end RFIN and an output end RFOUT for amplifying radio frequency signals;
the linearity enhancement circuit is connected with the source electrode of the enhanced PHEMT tube M1 in the signal amplification circuit and provides a low negative gate source voltage for the enhanced PHEMT tube M1.
2. The high performance low noise amplifier according to claim 1, wherein the signal amplifying circuit comprises an enhanced PHEMT tube M1, an enhanced logic tube M7, an inductor Ls, an inductor Ld, a blocking capacitor C1, a blocking capacitor C2, and a resistor R1; wherein,,
the grid electrode of the enhanced PHEMT tube M1 is connected to a radio frequency signal input end RFIN through a blocking capacitor C1;
the drain electrode of the enhanced PHEMT tube M1 is connected to the output end RFOUT through a blocking capacitor C2 and is connected to a power supply VDD through an inductor Ld;
the grid electrode of the enhanced PHEMT tube M1 is connected with bias voltage Vb1 through a resistor R1 and is connected to the drain electrode of an enhanced logic tube M7, the source electrode of the enhanced logic tube M7 is grounded, and the grid electrode of the enhanced logic tube M7 is connected with control voltage EN_BYP;
the source electrode of the enhanced PHEMT tube M1 is connected with a linearity enhancement circuit through an inductance Ls.
3. The high performance low noise amplifier of claim 2, wherein said linearity enhancement circuit comprises: an enhanced PHEMT tube M2, an enhanced logic tube M6, a resistor R2 and a diode D1, wherein,
the drain electrode of the enhanced PHEMT tube M2 is connected to the drain electrode of the enhanced logic tube M6 through a diode D1, the source electrode of the enhanced PHEMT tube M2 is grounded, and the grid electrode of the enhanced PHEMT tube M2 is connected with a control voltage EN_LNA; the source electrode of the enhanced logic tube M6 is grounded, the grid electrode of the enhanced logic tube M6 is connected with the control voltage EN_LNA, and the drain electrode of the enhanced logic tube M6 is connected with a power supply through a resistor R2.
4. A high performance low noise amplifier according to claim 3, wherein the control voltage en_lna is inverted from the control voltage en_byp.
5. The high performance low noise amplifier according to claim 4, wherein when the low noise amplifier is operated in the LNA mode, when the control voltage en_byp is low, the control voltage en_lna is high, and the gate voltage Vg1 of the enhancement mode PHEMT tube M1 is equal to the bias voltage Vb1; the enhanced PHEMT tube M2 and the enhanced logic tube M6 are turned on, the drain voltage of the enhanced logic tube M6 and the drain voltage Vd2 of the enhanced PHEMT tube M2 are grounded, and the diode D1 is not conducted.
6. A high performance low noise amplifier according to claim 4, wherein,
when the low noise amplifier works in the Bypass mode, the control voltage EN_BYP is high level, the control voltage EN_LNA is low level, and the gate voltage Vg1=0V of the enhanced PHEMT tube M1; the enhanced PHEMT transistor M2 and the enhanced logic transistor M6 are turned off, the power supply voltage VDD generates a high voltage Vd2 at the drain of the enhanced PHEMT transistor M2 through the resistor R2 and the diode D1, and a low negative voltage difference Vgs1 is generated between the gate voltage and the source voltage of the enhanced PHEMT transistor M1.
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Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288609B1 (en) * | 2000-02-29 | 2001-09-11 | Motorola, Inc. | Gain controllable low noise amplifier with automatic linearity enhancement and method of doing same |
| US20010029172A1 (en) * | 1999-12-29 | 2001-10-11 | Woo-Yong Lee | Low-noise amplifier for a mobile communication terminal |
| CN1514539A (en) * | 2002-12-12 | 2004-07-21 | 新日本无线株式会社 | Gain changeable amplifier |
| JP2009005092A (en) * | 2007-06-21 | 2009-01-08 | New Japan Radio Co Ltd | Variable-gain low noise amplifier |
| JP2009225342A (en) * | 2008-03-18 | 2009-10-01 | New Japan Radio Co Ltd | Variable-gain low noise amplifier |
| CN106656071A (en) * | 2016-12-30 | 2017-05-10 | 杭州迦美信芯通讯技术有限公司 | Uniform matching system with bypass channel and low-noise amplifier and used for 5GHz WiFi communication |
| US20180076774A1 (en) * | 2016-09-14 | 2018-03-15 | Skyworks Solutions, Inc. | Radio-frequency amplifier having active gain bypass circuit |
| CN207706134U (en) * | 2017-10-20 | 2018-08-07 | 江苏卓胜微电子股份有限公司 | A kind of low-noise amplifier |
| CN109194291A (en) * | 2018-09-06 | 2019-01-11 | 南京国博电子有限公司 | A kind of one chip low-noise amplifier of the high-gain High Linear with bypass functionality |
| CN110729973A (en) * | 2019-09-16 | 2020-01-24 | 广东工业大学 | HEMT low noise amplifier bypass structure |
| CN111600555A (en) * | 2020-06-02 | 2020-08-28 | 西安博瑞集信电子科技有限公司 | Switch low noise amplifier |
| CN111600556A (en) * | 2020-06-30 | 2020-08-28 | 河北新华北集成电路有限公司 | Low noise amplifier and radio frequency receiver |
| CN112953419A (en) * | 2021-03-04 | 2021-06-11 | 电子科技大学 | Nonlinear cancellation power amplifier based on cascode structure |
| CN113315477A (en) * | 2021-05-13 | 2021-08-27 | 深圳市时代速信科技有限公司 | Radio frequency amplifier and control method thereof |
| CN115441838A (en) * | 2022-09-15 | 2022-12-06 | 深圳飞骧科技股份有限公司 | Low noise amplifier and radio frequency chip |
| CN116131770A (en) * | 2023-04-18 | 2023-05-16 | 成都明夷电子科技有限公司 | High-integration-level high-linearity low-noise amplifier |
-
2023
- 2023-06-15 CN CN202310708018.6A patent/CN116436420B/en active Active
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010029172A1 (en) * | 1999-12-29 | 2001-10-11 | Woo-Yong Lee | Low-noise amplifier for a mobile communication terminal |
| US6288609B1 (en) * | 2000-02-29 | 2001-09-11 | Motorola, Inc. | Gain controllable low noise amplifier with automatic linearity enhancement and method of doing same |
| CN1514539A (en) * | 2002-12-12 | 2004-07-21 | 新日本无线株式会社 | Gain changeable amplifier |
| JP2009005092A (en) * | 2007-06-21 | 2009-01-08 | New Japan Radio Co Ltd | Variable-gain low noise amplifier |
| JP2009225342A (en) * | 2008-03-18 | 2009-10-01 | New Japan Radio Co Ltd | Variable-gain low noise amplifier |
| US20180076774A1 (en) * | 2016-09-14 | 2018-03-15 | Skyworks Solutions, Inc. | Radio-frequency amplifier having active gain bypass circuit |
| CN106656071A (en) * | 2016-12-30 | 2017-05-10 | 杭州迦美信芯通讯技术有限公司 | Uniform matching system with bypass channel and low-noise amplifier and used for 5GHz WiFi communication |
| CN207706134U (en) * | 2017-10-20 | 2018-08-07 | 江苏卓胜微电子股份有限公司 | A kind of low-noise amplifier |
| CN109194291A (en) * | 2018-09-06 | 2019-01-11 | 南京国博电子有限公司 | A kind of one chip low-noise amplifier of the high-gain High Linear with bypass functionality |
| CN110729973A (en) * | 2019-09-16 | 2020-01-24 | 广东工业大学 | HEMT low noise amplifier bypass structure |
| CN111600555A (en) * | 2020-06-02 | 2020-08-28 | 西安博瑞集信电子科技有限公司 | Switch low noise amplifier |
| CN111600556A (en) * | 2020-06-30 | 2020-08-28 | 河北新华北集成电路有限公司 | Low noise amplifier and radio frequency receiver |
| CN112953419A (en) * | 2021-03-04 | 2021-06-11 | 电子科技大学 | Nonlinear cancellation power amplifier based on cascode structure |
| CN113315477A (en) * | 2021-05-13 | 2021-08-27 | 深圳市时代速信科技有限公司 | Radio frequency amplifier and control method thereof |
| CN115441838A (en) * | 2022-09-15 | 2022-12-06 | 深圳飞骧科技股份有限公司 | Low noise amplifier and radio frequency chip |
| CN116131770A (en) * | 2023-04-18 | 2023-05-16 | 成都明夷电子科技有限公司 | High-integration-level high-linearity low-noise amplifier |
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| CN116436420B (en) | 2023-08-22 |
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