CN111262534A - Self-adaptive bias circuit for power amplifier chip - Google Patents
Self-adaptive bias circuit for power amplifier chip Download PDFInfo
- Publication number
- CN111262534A CN111262534A CN202010193953.XA CN202010193953A CN111262534A CN 111262534 A CN111262534 A CN 111262534A CN 202010193953 A CN202010193953 A CN 202010193953A CN 111262534 A CN111262534 A CN 111262534A
- Authority
- CN
- China
- Prior art keywords
- transistor
- circuit
- power amplifier
- bias voltage
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003068 static effect Effects 0.000 claims abstract description 12
- 239000003990 capacitor Substances 0.000 claims description 33
- 230000003044 adaptive effect Effects 0.000 claims description 17
- 230000010354 integration Effects 0.000 abstract description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 8
- 238000004891 communication Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000010295 mobile communication Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a self-adaptive bias circuit for a power amplifier chip, which comprises a bias circuit, a feedback circuit and an amplifying circuit, wherein the bias circuit provides dynamic bias voltage and provides bias voltage for a transistor M2 in the amplifying circuit together with first static bias voltage Vg 1; as the power of the input radio frequency signal increases, the dynamic bias voltage provided to the transistor M2 is larger, and the transistor M2 self-adaptive linear compensation is realized; the feedback circuit is used for adjusting the radio frequency performance of the amplifier; the bias circuit converts the radio frequency signal into a direct current signal, and the direct current signal is a dynamic bias voltage generated by the bias circuit. The invention has simple structure, small size, self-adaptive bias function, does not need to artificially change the bias voltage of the amplifier, improves the linearity of the power amplifier, simultaneously considers the efficiency, and also improves the monolithic integration and the practicability.
Description
Technical Field
The invention relates to the technical field of microelectronics, semiconductors and communication, in particular to a self-adaptive bias circuit for a power amplifier chip.
Background
The radio frequency power amplifier is an important component of a mobile communication system, is used as a final amplifying unit of a transmitting channel, and is used for amplifying a low-power radio frequency signal and transmitting the amplified signal through an antenna. The design criteria of the rf power amplifier generally include output power, efficiency, gain, bandwidth, linearity, etc. The non-linearity of the rf power amplifier tends to generate unwanted frequency components, which severely affect the performance of the mobile communication system.
The conventional power amplifier may employ a Complementary Metal Oxide Semiconductor (CMOS), a gallium arsenide heterojunction bipolar transistor (GaAs HBT), a gallium arsenide pseudomorphic high electron mobility transistor (GaAs pHEMT), or the like as a power amplifying element. Although the radio frequency power amplifier realized by adopting the CMOS device has good compatibility and low cost, the radio frequency power amplifier has the defects of low linearity and low voltage withstanding value; although the power capacity of the radio frequency power amplifier realized by adopting the GaAs HBT device is large, the self-heating effect exists; the radio frequency power amplifier realized by adopting the GaAs pHEMT device generally uses load traction to find a maximum output power point to carry out output end matching. However, since the power amplifier is often operated in a non-maximum output power state, the power amplifier is required to have high efficiency in a wide operating range in order to improve the average efficiency of the power amplifier. Thus, design considerations generally compromise between efficiency and linearity, resulting in less than optimal design of the amplifier's linearity.
With the advent of the 5G era, higher demands have been made on performance indexes of communication systems. As an important component in a communication system, the linearity of a power amplifier is very important in the system. The microwave power transistor made of gallium arsenide (GaAs) material has the advantages of high efficiency, low noise power, strong radiation resistance and the like, wherein the GaAs pseudomorphic high electron mobility transistor (GaAs pHEMT) is more suitable for high-frequency high-power application. Therefore, the method for improving the linearity of the GaAspHEMT process power amplifier chip has great application value and practical significance.
Disclosure of Invention
An object of the present invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
The self-adaptive bias circuit for the power amplifier chip provided by the invention has the characteristics of simple structure, small size, improvement on the monolithic integration level, balance of the power amplifier in the two aspects of efficiency and linearity, improvement on the practicability of the power amplifier chip and the like.
To achieve these objects and other advantages in accordance with the purpose of the invention, an adaptive bias circuit for a power amplifier chip is provided, which includes a bias circuit, a feedback circuit, and an amplification circuit.
The bias circuit provides a dynamic bias voltage, and provides a bias voltage for a transistor M2 in the amplifying circuit together with a first static bias voltage Vg 1; as the power of the input radio frequency signal increases, the larger the dynamic bias voltage provided to the transistor M2, the more adaptive linearity compensation of the transistor M2 is achieved.
The feedback circuit is used to adjust the radio frequency performance of the amplifier.
The bias circuit converts the radio frequency signal into a direct current signal, and the direct current signal is a dynamic bias voltage generated by the bias circuit.
Further, the bias circuit comprises two resistors R1 and R2, a transistor M1 and a capacitor C1, wherein the resistor R1 and the capacitor C1 are connected in parallel, the first end of the resistor R1 is grounded, the second end of the resistor R1 is connected with the gate of the transistor M1, and the source and the drain of the transistor M1 are shorted and connected with the first end of the resistor R2;
further, the feedback circuit comprises two resistors R3 and R4 and a capacitor C2, wherein a first end of each of the resistors R3 and R4 is connected to a second end of the resistor R2, a second end of the resistor R3 is connected to a first end of the capacitor C4 and a gate of the transistor M2, and a second end of the resistor R4 is connected to a first end of the capacitor C2;
further, the amplifying circuit comprises two transistors M2 and M3, a source of the transistor M2 is grounded, a gate is connected with a first end of a capacitor C4, a drain is connected with a source of the transistor M3, a gate of the transistor M3 is connected with a first end of a capacitor C3, a drain is connected with a second end of the capacitor C2, a first end of the capacitor C5 and a first end of a choke inductor L1, and a second end of the capacitor C3 is grounded;
further, the first static bias voltage Vg1 is connected to the second terminal of the resistor R2, the first terminal of the resistor R3, and the first terminal of the resistor R4;
further, the power supply terminal is further included, and the power supply terminal is connected with the second terminal of the choke inductor L1;
further, a second static bias voltage Vg2 is preferably included, which is connected to the first terminal of capacitor C3, the gate of transistor M3.
The invention has the beneficial effects that: the self-adaptive bias circuit has the advantages of simple structure, small size, self-adaptive bias function, no need of manually changing the bias voltage of the amplifier, improvement of the linearity of the power amplifier, efficiency, single chip integration level and practicability.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an adaptive bias circuit for a power amplifier chip according to the present invention.
FIG. 2 is a graph comparing the simulation results of the output P1dB of the bias circuit of the present invention with the frequency variation.
Detailed Description
The present invention is further described in detail below with reference to the attached drawings so that those skilled in the art can implement the invention by referring to the description text.
It will be understood that terms such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
In one embodiment, as shown in fig. 1, an adaptive bias circuit 1 for a power amplifier chip includes a bias circuit 1, a feedback circuit 2, and an amplifying circuit 3.
The bias circuit 1 generates a dynamic bias voltage and provides a bias voltage for the transistor M2 in the amplifier circuit 3 with a first static bias voltage Vg 1.
The feedback circuit 2 optimizes the dynamic bias voltage generated by the bias circuit 1 and the first static bias voltage Vg1 to meet the usage requirements.
Specifically, the bias circuit 1 comprises two resistors R1 and R2, a transistor M1 and a capacitor C1, wherein the resistor R1 and the capacitor C1 are connected in parallel, a first end of the resistor R1 is grounded, a second end of the resistor R1 is connected with the gate of the transistor M1, and a source and a drain of the transistor M1 are shorted and connected with a first end of the resistor R2.
Specifically, the feedback circuit 2 includes two resistors R3 and R4 and a capacitor C2, a first end of each of the resistors R3 and R4 is connected to a second end of the resistor R2, a second end of the resistor R3 is connected to a first end of the capacitor C4 and a gate of the transistor M2, and a second end of the resistor R4 is connected to a first end of the capacitor C2.
Specifically, the amplifying circuit 3 includes two transistors M2 and M3, the source of the transistor M2 is grounded, the gate is connected to the first end of the capacitor C4, the drain is connected to the source of the transistor M3, the gate of the transistor M3 is connected to the first end of the capacitor C3, the drain is connected to the second end of the capacitor C2, the first end of the capacitor C5 and the first end of the choke inductor L1, and the second end of the capacitor C3 is grounded.
Specifically, the first static bias voltage Vg1 is connected to the second terminal of the resistor R2, the first terminal of the resistor R3, and the first terminal of the resistor R4.
Specifically, a power supply terminal connected to the second terminal of the choke inductance L1 is further included.
Specifically, a second static bias voltage Vg2 is further included, which is connected to the first terminal of the capacitor C3, the gate of the transistor M3.
In this embodiment, the adaptive bias circuit 1 for a power amplifier chip according to the present invention is further described:
the invention provides a dynamic bias voltage for the grid electrode of a common source transistor M2 through an adaptive bias circuit 1. The grid bias voltage of the common source transistor mainly comprises two parts which are superposed: first, the static bias voltage Vg 1; the second is the dynamic bias voltage generated by self-adaptive bias. The source and drain of the transistor M1 in the self-adaptive bias circuit 1 are short-circuited and used as a diode, due to the rectifying characteristic of the diode, a part of radio frequency signal energy is converted into a direct current signal, a voltage signal is superposed on the gate of the transistor M2 through the feedback circuit 2, the voltage swing of the output radio frequency signal is increased along with the increase of the power of the input radio frequency signal, and the voltage swing of the feedback through the feedback circuit 2 is increased. If the power of the input radio frequency signal is larger, the feedback voltage of the feedback circuit 2 is larger, and the dynamic voltage generated by the adaptive bias circuit 1 is also larger, the superimposed voltage provided to the gate of the common-source transistor M2 is also larger, so that the adaptive linear compensation of the transistor M2 is realized, and the output power of the 1dB compression point of the power amplifier is improved.
In this design, a part of the rf signal will leak, and this part of the signal will be shorted to ground from the capacitor C1. The linearized adaptive bias circuit 1 follows the input power change, and improves the efficiency at low output power and the linearity at high output power. Compared with the traditional power amplifier, the self-adaptive bias circuit 1 has the advantages of simple structure, small size and self-adaptive bias function, does not need to artificially change the bias voltage of the amplifier, improves the linearity of the power amplifier, simultaneously considers the efficiency, and also improves the monolithic integration level and the practicability.
As shown in fig. 2, comparing the output P1dB of the conventional power amplifier with the output P1dB of the power amplifier configured with the linearizing bias circuit 1 according to the present invention, the linearity of the power amplifier configured with the linearizing bias circuit 1 according to the present invention is significantly improved.
While embodiments of the invention have been disclosed above, it is not limited to the applications listed in the description and the embodiments. It can be applied to all kinds of fields suitable for the present invention. For those skilled in the art, according to the embodiment of the present invention, there may be variations in the specific implementation and application range, and the adaptive bias circuit described in the embodiment may be replaced by a diode; in the self-adaptive biasing circuit, the source electrode and the drain electrode of the transistor M1 are short-circuited and can also be changed into a mode of connecting a plurality of transistors in series or connecting a plurality of transistors in parallel; any self-adaptive bias circuit composed of diodes is used for the gate of the common-source transistor M2 in the embodiment, which is regarded as an application extension of the invention. It is therefore intended that the invention not be limited to the exact details and illustrations described and illustrated herein, but fall within the scope of the appended claims and equivalents thereof.
Claims (7)
1. An adaptive bias circuit for a power amplifier chip, comprising a bias circuit, a feedback circuit and an amplifying circuit,
the bias circuit provides a dynamic bias voltage, and provides a bias voltage for a transistor M2 in the amplifying circuit together with a first static bias voltage Vg 1; as the power of the input radio frequency signal increases, the dynamic bias voltage provided to the transistor M2 is larger, and the transistor M2 self-adaptive linear compensation is realized;
the feedback circuit is used for adjusting the radio frequency performance of the amplifier;
the bias circuit converts the radio frequency signal into a direct current signal, and the direct current signal is a dynamic bias voltage generated by the bias circuit.
2. The adaptive bias circuit for the power amplifier chip as claimed in claim 1, wherein the bias circuit comprises two resistors R1 and R2, a transistor M1 and a capacitor C1, the resistor R1 and the capacitor C1 are connected in parallel, a first end is grounded, a second end is connected with a gate of the transistor M1, and a source and a drain of the transistor M1 are shorted and connected with a first end of the resistor R2.
3. The adaptive bias circuit for the power amplifier chip as claimed in claim 1, wherein the feedback circuit comprises two resistors R3 and R4 and a capacitor C2, a first terminal of each of the resistors R3 and R4 is connected to a second terminal of the resistor R2, a second terminal of the resistor R3 is connected to a first terminal of the capacitor C4 and a gate of the transistor M2, and a second terminal of the resistor R4 is connected to a first terminal of the capacitor C2.
4. The adaptive bias circuit for the power amplifier chip as claimed in claim 1, wherein the amplifying circuit comprises two transistors M2 and M3, the source of the transistor M2 is connected to ground, the gate is connected to the first end of a capacitor C4, the drain is connected to the source of a transistor M3, the gate of the transistor M3 is connected to the first end of a capacitor C3, the drain is connected to the second end of a capacitor C2, the first end of C5 and the first end of a choke inductor L1, and the second end of the capacitor C3 is connected to ground.
5. The adaptive bias circuit for a power amplifier chip as claimed in claim 1, wherein the first static bias voltage Vg1 is connected to the second terminal of the resistor R2, the first terminal of the resistor R3 and the first terminal of the resistor R4.
6. The adaptive bias circuit for a power amplifier chip as claimed in claim 1, further comprising a power supply terminal connected to the second terminal of the choke inductor L1.
7. The adaptive bias circuit for a power amplifier chip as claimed in claim 1, further comprising a second static bias voltage Vg2, said second bias voltage being connected to the first terminal of the capacitor C3, the gate of the transistor M3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010193953.XA CN111262534B (en) | 2020-03-19 | 2020-03-19 | Self-adaptive bias circuit for power amplifier chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010193953.XA CN111262534B (en) | 2020-03-19 | 2020-03-19 | Self-adaptive bias circuit for power amplifier chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111262534A true CN111262534A (en) | 2020-06-09 |
| CN111262534B CN111262534B (en) | 2024-09-27 |
Family
ID=70954928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010193953.XA Active CN111262534B (en) | 2020-03-19 | 2020-03-19 | Self-adaptive bias circuit for power amplifier chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111262534B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111313844A (en) * | 2020-03-19 | 2020-06-19 | 西安博瑞集信电子科技有限公司 | Self-adaptive bias circuit applied to low-noise amplifier chip |
| CN112953411A (en) * | 2021-03-10 | 2021-06-11 | 西安博瑞集信电子科技有限公司 | Ultra-wideband power amplifier |
| CN115580233A (en) * | 2022-12-08 | 2023-01-06 | 西安博瑞集信电子科技有限公司 | Dynamic bias method and system of low-noise amplifier and dynamic bias circuit |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1381091A (en) * | 2000-03-28 | 2002-11-20 | 皇家菲利浦电子有限公司 | Dynamic bias boosting circuit for power amplifier |
| US20080164949A1 (en) * | 2007-01-05 | 2008-07-10 | City University Of Hong Kong | Wideband linearization and adaptive power management for microwave power amplifiers |
| CN101719776A (en) * | 2009-12-09 | 2010-06-02 | 中国科学院半导体研究所 | Radio frequency transmitting-receiving device |
| CN103023440A (en) * | 2012-12-20 | 2013-04-03 | 中国科学院微电子研究所 | Circuit for improving linearity of power amplifier |
| CN103166581A (en) * | 2013-01-25 | 2013-06-19 | 嘉兴联星微电子有限公司 | Radio frequency low noise amplifier with high linearity |
| US20140167854A1 (en) * | 2012-12-19 | 2014-06-19 | Advanced Semiconductor Engineering Inc. | Electronic system - radio frequency power amplifier and method for self-adjusting bias point |
| CN105191120A (en) * | 2013-03-14 | 2015-12-23 | 高通股份有限公司 | Adapative power amplifier |
| CN105811899A (en) * | 2016-04-18 | 2016-07-27 | 宜确半导体（苏州）有限公司 | Power amplifier output stage module and radio frequency front-end module |
| CN106571780A (en) * | 2016-11-17 | 2017-04-19 | 锐迪科微电子（上海）有限公司 | Adaptive biasing radio frequency power amplifier |
| CN109167574A (en) * | 2018-09-11 | 2019-01-08 | 西安交通大学 | Stack power amplifier and its dynamic bias network |
| CN109560777A (en) * | 2019-01-30 | 2019-04-02 | 周守佳 | A kind of active biased Cascode radio frequency amplifier |
| CN110086441A (en) * | 2019-04-29 | 2019-08-02 | 中国科学院微电子研究所 | Power amplifier |
| CN211791445U (en) * | 2020-03-19 | 2020-10-27 | 西安博瑞集信电子科技有限公司 | Self-adaptive bias circuit for power amplifier chip |
-
2020
- 2020-03-19 CN CN202010193953.XA patent/CN111262534B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1381091A (en) * | 2000-03-28 | 2002-11-20 | 皇家菲利浦电子有限公司 | Dynamic bias boosting circuit for power amplifier |
| US20080164949A1 (en) * | 2007-01-05 | 2008-07-10 | City University Of Hong Kong | Wideband linearization and adaptive power management for microwave power amplifiers |
| CN101719776A (en) * | 2009-12-09 | 2010-06-02 | 中国科学院半导体研究所 | Radio frequency transmitting-receiving device |
| US20140167854A1 (en) * | 2012-12-19 | 2014-06-19 | Advanced Semiconductor Engineering Inc. | Electronic system - radio frequency power amplifier and method for self-adjusting bias point |
| CN103023440A (en) * | 2012-12-20 | 2013-04-03 | 中国科学院微电子研究所 | Circuit for improving linearity of power amplifier |
| CN103166581A (en) * | 2013-01-25 | 2013-06-19 | 嘉兴联星微电子有限公司 | Radio frequency low noise amplifier with high linearity |
| CN105191120A (en) * | 2013-03-14 | 2015-12-23 | 高通股份有限公司 | Adapative power amplifier |
| CN105811899A (en) * | 2016-04-18 | 2016-07-27 | 宜确半导体（苏州）有限公司 | Power amplifier output stage module and radio frequency front-end module |
| CN106571780A (en) * | 2016-11-17 | 2017-04-19 | 锐迪科微电子（上海）有限公司 | Adaptive biasing radio frequency power amplifier |
| CN109167574A (en) * | 2018-09-11 | 2019-01-08 | 西安交通大学 | Stack power amplifier and its dynamic bias network |
| CN109560777A (en) * | 2019-01-30 | 2019-04-02 | 周守佳 | A kind of active biased Cascode radio frequency amplifier |
| CN110086441A (en) * | 2019-04-29 | 2019-08-02 | 中国科学院微电子研究所 | Power amplifier |
| CN211791445U (en) * | 2020-03-19 | 2020-10-27 | 西安博瑞集信电子科技有限公司 | Self-adaptive bias circuit for power amplifier chip |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111313844A (en) * | 2020-03-19 | 2020-06-19 | 西安博瑞集信电子科技有限公司 | Self-adaptive bias circuit applied to low-noise amplifier chip |
| CN112953411A (en) * | 2021-03-10 | 2021-06-11 | 西安博瑞集信电子科技有限公司 | Ultra-wideband power amplifier |
| CN115580233A (en) * | 2022-12-08 | 2023-01-06 | 西安博瑞集信电子科技有限公司 | Dynamic bias method and system of low-noise amplifier and dynamic bias circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111262534B (en) | 2024-09-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7928804B2 (en) | Power amplifier | |
| CN100466462C (en) | Dynamic bias circuit for a radio-frequency amplifier | |
| US7932782B2 (en) | Average power efficiency enhancement and linearity improvement of microwave power amplifiers | |
| CN213990604U (en) | Amplifier bias circuit and radio frequency power amplifier | |
| US7944306B2 (en) | Dual bias control circuit | |
| CN111262534B (en) | Self-adaptive bias circuit for power amplifier chip | |
| WO2017107949A1 (en) | Method for improving linearity of radio frequency power amplifier, compensation circuit and communication terminal | |
| CN104617905B (en) | Radio frequency amplifier and radio frequency amplification method | |
| CN105743450A (en) | Radio frequency power amplifier | |
| CN211791447U (en) | Bias circuit of radio frequency power amplifier and radio frequency power amplifier | |
| CN111313844A (en) | Self-adaptive bias circuit applied to low-noise amplifier chip | |
| CN107659278A (en) | A kind of Ka wave bands SiGe BiCMOS radio-frequency power amplifiers | |
| US11545944B2 (en) | Power amplifier circuit | |
| CN211579935U (en) | Self-adaptive bias circuit applied to low-noise amplifier chip | |
| CN114679140A (en) | High-linearity radio frequency power amplifier | |
| US11646704B2 (en) | Power amplifier circuit | |
| US20030201827A1 (en) | High frequency power amplifier module | |
| CN211791445U (en) | Self-adaptive bias circuit for power amplifier chip | |
| CN115913155B (en) | High-linearity power amplifier suitable for 5G system | |
| CN111756335A (en) | Radio frequency gain module amplifier chip | |
| KR20150076571A (en) | Linear power amplifier for wireless transmitter | |
| US20050083128A1 (en) | [power amplifier with active bias circuit] | |
| CN113131875B (en) | High-reliability low-noise amplifier | |
| CN204156827U (en) | A kind of wideband power amplifer chip for radar system and amplifier | |
| CN112152575A (en) | Low-noise amplifier circuit with high input dynamic range |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Country or region after: China Address after: Building 12, Hard Technology Enterprise Community, No. 3000 Biyuan Second Road, High tech Zone, Xi'an City, Shaanxi Province, 710065 Applicant after: Borui Jixin (Xi'an) Electronic Technology Co.,Ltd. Address before: 22nd floor, East Building, block B, Tengfei Kehui City, 88 Tiangu 7th Road, Yuhua Street office, high tech Zone, Xi'an, Shaanxi 710000 Applicant before: XI'AN BORUI JIXIN ELECTRONIC TECHNOLOGY Co.,Ltd. Country or region before: China |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |