CN115913155B - High-linearity power amplifier suitable for 5G system - Google Patents
High-linearity power amplifier suitable for 5G system Download PDFInfo
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Abstract
The invention discloses a high-linearity power amplifier suitable for a 5G system, which comprises a radio frequency amplifying unit, an adaptive bias unit, a bias voltage detecting unit and a low envelope impedance unit. The radio frequency amplifying unit comprises a plurality of cascaded amplifying circuits, and HBT transistors Q of the amplifying circuits of the final stage n The collector of (2) is connected with the output matching network, and the base is connected with the output matching network through a resistor R m+1 The self-adaptive bias circuit is connected with the final stage; one end of the bias voltage detecting unit is arranged at the resistor R m+1 Between the self-adaptive bias circuits of the final stage, and the other end is connected with a low envelope impedance unit, the low envelope impedance unit is connected with the HBT transistor Q n Is connected to the base of the transistor. Because the low-envelope impedance unit has the frequency selection characteristic, the low-envelope impedance unit constantly presents a high configuration at the working frequency of the power amplifier, and a controllable low-resistance envelope frequency-to-ground path is provided for the input end of the final-stage amplifying tube of the amplifier at the baseband frequency, thereby inhibiting the adverse effect of the memory effect on the linearity of the linear power amplifier.
Description
Technical Field
The invention belongs to the technical field of radio frequency front-end equipment, and particularly relates to a high-linearity power amplifier suitable for a 5G system.
Background
The following 5G (fifth generation mobile communication) technology lays a solid wireless communication technology foundation for human beings to enter the 4.0 era of industry by virtue of the advantages of high speed, low time delay, high mobility, high connection capability, high flow density, high energy efficiency, low cost and the like. The 5G system adopts a Multiple Input Multiple Output (MIMO) architecture, and as the 5G needs to realize ultra-high transmission speed, the spread spectrum bandwidth is widened, and the spectrum utilization rate is improved, which are two methods for increasing the wireless transmission speed. But the frequency of the signal is improved, the bandwidth is increased, the modulation mode is more complex, the peak-to-average ratio is further increased, and the complex scenes put higher performance demands on the linearization technology of the radio frequency front end. Therefore, this requires the power amplifier in the 5G system to have high linearity characteristics to reduce the error rate and parasitic interference of the communication system.
The power amplifier is used as a key device at the tail end of the transmitter to directly determine the performance of the transmitter, and the linearity of the whole communication system can be obviously improved by improving the linearization level of the power amplifier because the power amplifier is the device with the strongest nonlinearity in the whole wireless communication system.
Because the HBT device has the advantages of high power density, higher breakdown voltage, higher current amplification factor beta, single power supply and the like in the sub-6GHz frequency band, the GaAs HBT device is widely applied to the design of a sub-6GHz frequency band power amplifier. As shown in fig. 1, the conventional linear power amplifier generally adopts a 2-stage or 3-stage cascade amplifying structure because the single-stage amplifier cannot meet the requirement of the system on the power gain of the device. The emitter junction voltage of HBT transistors decreases with increasing input power, while operating point drift can cause a decrease in transconductance, which in turn can produce gain compression and phase distortion. HBT transistor Q 2a HBT transistor Q 3a HBT transistor Q 4a Resistance R 1a Resistance R 2a And capacitor C 3a Self-adaptive bias HBT transistor Q forming first stage amplifier 6a HBT transistor Q 7a HBT transistor Q 8a Resistance R 3a Resistance R 4a And capacitor C 4a The self-adaptive bias structure can well inhibit bias point drift of the HBT transistor due to self-heating effect, improve linearity of the power amplifier and improve output power.
The adaptive bias structure adopted by the traditional linear power amplifier is high in resistance to the radio frequency signal in the working frequency, so that the modulation effect of the bias circuit on the radio frequency signal is avoided. But due to the resistance R in the adaptive biasing structure in conventional linear power amplifiers 4a And HBT transistor Q 5a The grid is connected to make the envelope frequency impedance of the RF signal higher, and for the envelope frequency of the RF signal, the second-order intermodulation of the RF signal and the RF carrier signal just falls on the side band of the signal, so the self-adaptive bias structureThe introduction of the circuit is very easy to cause the bias circuit to generate envelope modulation, generate obvious memory effect, and obviously deteriorate the linearity index of the linear power amplifier along with the increase of output power and the improvement of signal bandwidth. At present, with the great improvement of the 5G working bandwidth, the influence of the memory effect on the linearity of the power amplifier is more serious, and the design and application of the linear power amplifier under a large signal bandwidth are severely limited. Therefore, this problem is to be solved.
Disclosure of Invention
The present invention aims to provide a high-linearity power amplifier suitable for a 5G system, which aims to solve the above problems.
The invention is realized mainly by the following technical scheme:
a high-linearity power amplifier suitable for 5G system, including radio frequency amplifying unit, self-adaptive bias unit, bias voltage detection unit and low envelope impedance unit; the radio frequency amplifying unit comprises a plurality of cascaded amplifying circuits, and the adaptive bias unit is provided with a plurality of adaptive bias circuits corresponding to the plurality of amplifying circuits; the amplifying circuit comprises an HBT transistor Q n The HBT transistor Q n The emitter of the final stage is grounded, and the HBT transistor Q of the amplifying circuit of the final stage n The collector of (a) is connected with an output matching network; the self-adaptive bias circuit passes through a resistor R m+1 HBT transistor Q of amplification circuit n Is connected with the base electrode of the transistor; one end of the bias voltage detection unit is arranged on the self-adaptive bias circuit and the resistor R of the final stage m+1 The other end of the low-envelope impedance unit is connected with the low-envelope impedance unit;
the low envelope impedance unit comprises a resistor R t Inductance L t Capacitance C t And pHEMT transistor M t pHEMT transistor M t Gate pass resistance R of (2) t Is connected with the bias voltage detection unit, and the source electrode is connected with the inductor L t A resistor R connected to the first end of the final stage and the drain thereof respectively m+1 HBT transistor Q of amplifying circuit of final stage n Is connected with the base electrode of the transistor; inductance L t A second terminal of (C) and a capacitor C t Is connected to the first end of the capacitor C t Is grounded;
the bias voltage detection unit is used for detecting the voltage signal of the self-adaptive bias circuit of the final stage, amplifying the voltage signal and inputting the amplified voltage signal into the low-envelope impedance unit to serve as the pHEMT transistor M of the low-envelope impedance unit t To be the gate control signal of the final stage of the amplifying circuit n The input provides a controllable low-impedance envelope frequency to ground path, thereby suppressing adverse effects of memory effects on the linearity of the linear power amplifier.
In order to better realize the invention, the bias voltage detection unit further comprises a resistor R h Resistance R h+1 Resistance R h+2 Resistance R h+3 Resistance R h+4 Diode D h And HBT transistor Q h The method comprises the steps of carrying out a first treatment on the surface of the The resistor R h An adaptive bias circuit and a resistor R arranged at the first end of the final stage m+1 And the second ends are respectively connected with the resistor R h+2 Is a first terminal of diode D h Is connected with the anode of the diode D h Negative electrode of (2) and resistor R h+1 Is connected with the first end of the resistor R h+1 Is grounded; resistor R h+2 And HBT transistor Q h Is connected to the base of HBT transistor Q h Emitter and resistor R of (2) h+4 Is connected with the first end of the resistor R h+4 Is grounded at the second end of the resistor R h+3 Is connected to a power source and the second terminals are respectively connected to HBT transistor Q h Collector, resistor R of (2) t Is connected to the first end of the housing.
To better implement the present invention, further, the adaptive bias circuit includes an HBT transistor Q m HBT transistor Q m+1 HBT transistor Q m+2 Resistance R m And capacitor C m The method comprises the steps of carrying out a first treatment on the surface of the Resistor R m Is connected to a power source and the second terminal is connected to the HBT transistor Q m Collector, base and capacitor C of (C) m First end of (1), HBT transistor Q m+2 Is connected with the base electrode of the transistor; HBT transistor Q m Emitter and HBT transistor Q m+1 Is connected with the base and the collector of the transistor Q m+1 Emitter of (c)Grounded, capacitor C m Is grounded; HBT transistor Q m+2 The collector of (C) is connected with a power supply, and the emitter is connected with a resistor R m+1 Is connected to the first end of the housing; resistance R of the bias voltage detection unit h Resistors R respectively connected with the self-adaptive bias circuit of the final stage m+1 HBT transistor Q of an adaptive bias circuit of a final stage m+2 Emitter connection of (c).
In order to better realize the invention, the amplifying circuit further comprises an inductor L n Capacitance C n The HBT transistor Q n Collector and inductance L of (2) n Is connected with the first end of the inductor L n Is connected with a power supply; capacitor C of amplifying circuit of first stage n Is connected with the first end of the signal input end IN n A second end of the input matching network is connected with the first end of the input matching network, and the second end of the input matching network is connected with the HBT transistor Q of the amplifying circuit of the first stage n Is connected with the base electrode of the transistor; capacitor C of the amplifying circuit of the final stage n Is connected with the first end of the inductor L n A first end connected to the signal output end OUT n And (5) connection.
In order to better realize the invention, the radio frequency amplifying unit further comprises two cascaded amplifying circuits, and the adaptive bias unit is correspondingly provided with two adaptive bias circuits.
To better implement the invention, further, the input matching network is connected with the HBT transistor Q of the amplifying circuit of the first stage n A first-stage self-adaptive bias circuit is arranged between the bases of the first-stage self-adaptive bias circuit; HBT transistor Q of amplifying circuit of the first stage n HBT transistor Q of amplifying circuit of collector and final stage n An inter-stage matching network is arranged between the bases of the stages, and the inter-stage matching network is connected with an HBT transistor Q of an amplifying circuit of a final stage n An adaptive bias circuit of a final stage is arranged between the bases of the pair of transistors.
In order to better implement the invention, further, the inductance L n Is a choke inductance for powering the amplifying circuit.
The beneficial effects of the invention are as follows:
the invention is added with the bias voltage detection unit and the low envelope impedance unit on the basis of the traditional linear power amplifier, can reduce the influence of the memory effect on the linear power amplifier under the condition of large working bandwidth, and improves the linearity of the linear power amplifier.
The linear power amplifier memory effect is mainly caused by envelope modulation generated by the signal at the input end of the final amplifying tube. When the output power is smaller, the linearity of the linear power amplifier is higher, the memory effect is smaller, and the linearity of the radio frequency signal output by the transmitter is hardly influenced, so that the pHEMT transistor in the low-envelope impedance unit presents a high configuration in order to achieve the conventional electrical characteristics of the linear power amplifier such as small signal gain, temperature stability and the like. With the gradual increase of the output power, the bias voltage detection unit detects the gradually increased voltage signal, the gradually increased voltage signal becomes a grid control signal of the pHEMT transistor in the low-envelope impedance unit after amplification, and the magnitude of the impedance value of the low-envelope impedance channel in the access signal path is controlled by the conduction degree of the pHEMT transistor. Because the low-envelope impedance unit has the frequency selection characteristic, the low-envelope impedance unit constantly presents a high configuration at the working frequency of the power amplifier, and a controllable low-resistance envelope frequency-to-ground path is provided for the input end of the final amplification tube of the linear power amplifier at the baseband frequency, thereby inhibiting the adverse effect of the memory effect on the linearity of the linear power amplifier.
Drawings
FIG. 1 is a circuit schematic of a conventional linear power amplifier;
FIG. 2 is a circuit schematic of a high linearity power amplifier of the present invention;
FIG. 3 is a graph showing the variation of the output third-order intermodulation point of a conventional linear power amplifier with the output power;
fig. 4 is a graph showing the output third-order intermodulation point of the high-linearity power amplifier according to the present invention.
Detailed Description
Example 1:
a high-linearity power amplifier suitable for 5G system comprises a radio frequency amplifying unit and an adaptive bias unitA bias voltage detection unit and a low envelope impedance unit; the radio frequency amplifying unit comprises a plurality of cascaded amplifying circuits, and the adaptive bias unit is provided with a plurality of adaptive bias circuits corresponding to the plurality of amplifying circuits; the amplifying circuit comprises an HBT transistor Q n The HBT transistor Q n The emitter of the final stage is grounded, and the HBT transistor Q of the amplifying circuit of the final stage n The collector of (a) is connected with an output matching network; the self-adaptive bias circuit passes through a resistor R m+1 HBT transistor Q of amplification circuit n Is connected with the base electrode of the transistor; one end of the bias voltage detection unit is arranged on the self-adaptive bias circuit and the resistor R of the final stage m+1 And the other end is connected to the low envelope impedance unit.
The low envelope impedance unit comprises a resistor R t Inductance L t Capacitance C t And pHEMT transistor M t pHEMT transistor M t Gate pass resistance R of (2) t Is connected with the bias voltage detection unit, and the source electrode is connected with the inductor L t A resistor R connected to the first end of the final stage and the drain thereof respectively m+1 HBT transistor Q of amplifying circuit of final stage n Is connected with the base electrode of the transistor; inductance L t A second terminal of (C) and a capacitor C t Is connected to the first end of the capacitor C t Is grounded. In use, the resistance R in the low envelope impedance unit t Mainly plays a role of radio frequency signal isolation, and an inductor L t Capacitance C t The composed signal path presents low resistance at envelope frequency, presents high resistance at linear power amplifier working frequency, and the control voltage provided by the bias voltage detection unit can control pHEMT transistor M t So that it exhibits variable resistance characteristics.
The bias voltage detection unit is used for detecting the voltage signal of the self-adaptive bias circuit of the final stage, amplifying the voltage signal and inputting the amplified voltage signal into the low-envelope impedance unit to serve as the pHEMT transistor M of the low-envelope impedance unit t To be the gate control signal of the final stage of the amplifying circuit n The input terminal provides a controllable low-resistance envelope frequency to ground path, thereby inhibiting the memory effect from dealing with linear power amplifierThe linearity of the amplifier is adversely affected.
Preferably, the bias voltage detecting unit includes a resistor R h Resistance R h+1 Resistance R h+2 Resistance R h+3 Resistance R h+4 Diode D h And HBT transistor Q h The method comprises the steps of carrying out a first treatment on the surface of the The resistor R h An adaptive bias circuit and a resistor R arranged at the first end of the final stage m+1 And the second ends are respectively connected with the resistor R h+2 Is a first terminal of diode D h Is connected with the anode of the diode D h Negative electrode of (2) and resistor R h+1 Is connected with the first end of the resistor R h+1 Is grounded; resistor R h+2 And HBT transistor Q h Is connected to the base of HBT transistor Q h Emitter and resistor R of (2) h+4 Is connected with the first end of the resistor R h+4 Is grounded at the second end of the resistor R h+3 Is connected to a power source and the second terminals are respectively connected to HBT transistor Q h Collector, resistor R of (2) t Is connected to the first end of the housing.
Preferably, the adaptive bias circuit includes an HBT transistor Q m HBT transistor Q m+1 HBT transistor Q m+2 Resistance R m And capacitor C m The method comprises the steps of carrying out a first treatment on the surface of the Resistor R m Is connected to a power source and the second terminal is connected to the HBT transistor Q m Collector, base and capacitor C of (C) m First end of (1), HBT transistor Q m+2 Is connected with the base electrode of the transistor; HBT transistor Q m Emitter and HBT transistor Q m+1 Is connected with the base and the collector of the transistor Q m+1 Grounded emitter, capacitor C m Is grounded; HBT transistor Q m+2 The collector of (C) is connected with a power supply, and the emitter is connected with a resistor R m+1 Is connected to the first end of the housing; resistance R of the bias voltage detection unit h Resistors R respectively connected with the self-adaptive bias circuit of the final stage m+1 HBT transistor Q of an adaptive bias circuit of a final stage m+2 Emitter connection of (c).
The invention is added with the bias voltage detection unit and the low envelope impedance unit on the basis of the traditional linear power amplifier, can reduce the influence of the memory effect on the linear power amplifier under the condition of large working bandwidth, and improves the linearity of the linear power amplifier.
The linear power amplifier memory effect is mainly caused by envelope modulation generated by the signal at the input end of the final amplifying tube. When the output power is smaller, the linearity of the linear power amplifier is higher, the memory effect is smaller, and the linearity of the radio frequency signal output by the transmitter is hardly influenced, so that the pHEMT transistor in the low-envelope impedance unit presents a high configuration in order to achieve the conventional electrical characteristics of the linear power amplifier such as small signal gain, temperature stability and the like. With the gradual increase of the output power, the bias voltage detection unit detects the gradually increased voltage signal, the gradually increased voltage signal becomes a grid control signal of the pHEMT transistor in the low-envelope impedance unit after amplification, and the magnitude of the impedance value of the low-envelope impedance channel in the access signal path is controlled by the conduction degree of the pHEMT transistor. Because the low-envelope impedance unit has the frequency selection characteristic, the low-envelope impedance unit constantly presents a high configuration at the working frequency of the power amplifier, and a controllable low-resistance envelope frequency-to-ground path is provided for the input end of the final amplification tube of the linear power amplifier at the baseband frequency, thereby inhibiting the adverse effect of the memory effect on the linearity of the linear power amplifier.
Example 2:
a high linearity power amplifier suitable for 5G system includes radio frequency amplifying unit, self-adapting bias unit, bias voltage detecting unit and low envelope impedance unit. The radio frequency amplifying unit comprises a plurality of cascaded amplifying circuits, and the adaptive bias unit is provided with a plurality of adaptive bias circuits corresponding to the plurality of amplifying circuits; the amplifying circuit of the final stage comprises an HBT transistor Q n The HBT transistor Q n The emitter of the capacitor is grounded, and the collector is connected with an output matching network; the self-adaptive bias circuit of the final stage passes through a resistor R m+1 HBT transistor Q of amplifying circuit with final stage n Is connected with the base electrode of the transistor; one end of the bias voltage detection unit is arranged on the resistor R m+1 Between the self-adaptive bias circuit of the final stage and the other end is connected with a low envelope impedance unit, and the low envelope impedance unit is connected with the HBT transistorQ n Is connected to the base of the transistor.
The bias voltage detection unit is used for detecting the voltage signal of the self-adaptive bias circuit of the final stage, amplifying the voltage signal and inputting the amplified voltage signal into the low-envelope impedance unit to serve as the pHEMT transistor M of the low-envelope impedance unit t To be the gate control signal of the final stage of the amplifying circuit n The input provides a controllable low-impedance envelope frequency to ground path, thereby suppressing adverse effects of memory effects on the linearity of the linear power amplifier.
Preferably, the amplifying circuit of the final stage further comprises an inductance L n Capacitance C n HBT transistor Q n An output matching network, the HBT transistor Q n The emitter of (2) is grounded, and the collector is respectively connected with the inductor L n A first end of the output matching network is connected with the inductor L n The second end of the output matching network is respectively connected with the power supply and the capacitor C n Is connected with the first end of the capacitor C n A second terminal of (2) and a signal output terminal OUT n And (5) connection.
Preferably, the amplifying circuit of the first stage comprises an inductance L n Capacitance C n HBT transistor Q n Input matching network, capacitor C n Is connected with the first end of the signal input end IN n A second end is connected with the first end of the input matching network, and the second end of the input matching network is respectively connected with the HBT transistor Q n Is connected with the base electrode of the self-adaptive bias circuit, and the HBT transistor Q n Grounded emitter of (1), and HBT transistor Q n Collector of (a) is respectively connected with inductance L n First end and interstage matching network connection, inductance L n Is connected to a power source. Wherein the inductance L 1b And the choke inductance is used for supplying power to the amplifying circuit.
During operation, the RF signal is fed through the signal input IN n Into a high-linearity power amplifier, through the capacitor C of the amplifying circuit of the first stage n Then, the signal is input into an input matching network to change impedance, and passes through an HBT transistor Q of an amplifying circuit of the first stage n Amplifying the signals, sequentially processing the signals by an amplifying circuit in an intermediate cascade connection, and finally passing through an interstageAfter the impedance of the signal is changed by the matching network, the signal is amplified by the HBT transistor Q of the amplifying circuit of the final stage n Amplifying the signal again, changing the impedance of the signal through an output matching network, and passing through a capacitor C of an amplifying circuit of the final stage n Then, by the signal output terminal OUT n And outputting.
Preferably, the self-adaptive bias circuit can restrain bias point drift of the HBT transistor due to self-heating effect, improve linearity of the power amplifier and improve output power. The adaptive bias circuit includes an HBT transistor Q m HBT transistor Q m+1 HBT transistor Q m+2 Resistance R m Resistance R m+1 And capacitor C m The method comprises the steps of carrying out a first treatment on the surface of the Resistor R m Is connected to a power source and the second terminal is connected to the HBT transistor Q m Collector, base and capacitor C of (C) m First end of (1), HBT transistor Q m+2 Is connected with the base electrode of the transistor; HBT transistor Q m Emitter and HBT transistor Q m+1 Is connected with the base and the collector of the transistor Q m+1 Grounded emitter, capacitor C m Is grounded; HBT transistor Q m+2 The collector of (C) is connected with a power supply, and the emitter is connected with a resistor R m+1 Is connected to the first end of the housing; resistance R of the bias voltage detection unit h The first end of the self-adaptive bias circuit is respectively connected with the resistor R of the final stage m+1 First end of (1), HBT transistor Q m+2 Emitter connection of (c).
HBT transistor Q m HBT transistor Q m+1 The base and collector of the diode are shorted to form a dual diode series structure. Through HBT transistor Q m+2 HBT transistor Q of post-flow amplifying circuit n Current magnitude and HBT transistor Q m The current is proportional to the current. And as the input power increases, HBT transistor Q m+2 V also occurs in BE junction diodes be The voltage decreases. And HBT transistor Q m And HBT transistor Q m+1 Series to HBT transistor Q m+2 Provides a relatively stable diode clamping voltage at the base of (a) and thus HBT transistor Q m+2 V of (2) be HBT transistor Q capable of compensating amplifying circuit by voltage reduction n Upper BE knotThe voltage decreases as the input power increases. Decoupling capacitor C m Inhibit HBT transistor Q m+2 The base node voltage changes, increasing the linear power level of the HBT power amplifier. The self-adaptive bias structure of each stage of amplifier is identical and has consistent functions.
Preferably, the low envelope impedance unit comprises a resistor R t Inductance L t Capacitance C t And pHEMT transistor M t pHEMT transistor M t Gate pass resistance R of (2) t Connected to the bias voltage detecting unit, pHEMT transistor M t Source electrode of (d) and inductance L t Is connected with the first end of the resistor R m+1 HBT transistor Q of amplifying circuit of final stage n Is connected with the base electrode of the transistor; inductance L t A second terminal of (C) and a capacitor C t Is connected to the first end of the capacitor C t Is grounded.
In use, the resistance R in the low envelope impedance unit t Mainly plays a role of radio frequency signal isolation, and an inductor L t Capacitance C t The composed signal path presents low resistance at envelope frequency, presents high resistance at linear power amplifier working frequency, and the control voltage provided by the bias voltage detection unit can control pHEMT transistor M t So that it exhibits variable resistance characteristics.
Preferably, the bias voltage detecting unit includes a resistor R h Resistance R h+1 Resistance R h+2 Resistance R h+3 Resistance R h+4 Diode D h And HBT transistor Q h The method comprises the steps of carrying out a first treatment on the surface of the Resistor R h Respectively with resistor R m+1 The emitter of HBT transistor of the self-adaptive bias circuit of the final stage is connected with the second end of HBT transistor and the second end of HBT transistor is respectively connected with resistor R h+2 Is a first terminal of diode D h Is connected with the anode of the diode D h Negative electrode of (2) and resistor R h+1 Is connected with the first end of the resistor R h+1 Is grounded; resistor R h+2 And HBT transistor Q h Is connected to the base of HBT transistor Q h Emitter and resistor R of (2) h+4 Is connected with the first end of the resistor R h+4 Is grounded at the second end of the resistor R h+3 Is connected to a power source and the second terminals are respectively connected to HBT transistor Q h The collector of said low envelope impedance unit, resistance R t Is connected to the first end of the housing.
With the increase of the output power of the linear power amplifying circuit, the self-adaptive bias circuit of the final amplifying circuit passes through the resistor R m+1 Is also gradually increased, and thus, the current of the transistor Q can be obtained in the HBT m+2 The emitter obtains a voltage value V which increases with the increase of the output power 1 HBT transistor Q h For applying voltage V 1 Amplifying, diode D h For compensating HBT transistor Q h V which occurs with increasing temperature of BE junction(s) be Voltage drop, ensure HBT transistor Q 9b Has a temperature uniformity. Resistor R h Resistance R h+1 Diode D h Co-determining HBT transistor Q h Direct current operating point of (2), resistance R h+3 Resistance R h+4 For setting an output level representative value of the bias voltage detecting unit.
Example 3:
a high linearity power amplifier suitable for 5G applications, as shown in fig. 2, includes a radio frequency amplifying unit, an adaptive bias unit, a bias voltage detecting unit, and a low envelope impedance unit.
The radio frequency amplifying unit comprises a plurality of cascaded stages of amplifiers, and as shown in fig. 2, the circuit of the amplifier of the final stage comprises an inductor L 2b Capacitance C 4b HBT transistor Q 5b . HBT transistor Q 5b Emitter grounded, HBT transistor Q 5b Collector, inductance L 2b The first end is connected with the first end of the output matching network 1b, the inductance L 2b Second end and power VCC 1b A second end of the output matching network 1b is connected with a capacitor C 4b The first end is connected with a capacitor C 4b A second terminal and a signal output terminal OUT 1b And (5) connection.
The direct current bias unit comprises a plurality of adaptive biases corresponding to the amplifier settings. As shown in fig. 2, HBT transistor Q 6b HBT transistor Q 7b HBT transistor Q 8b Resistance R 3b Resistance R 4b And capacitor C 3b An adaptive bias of the final amplifier is formed. Resistor R 3b First end and power VCC 3b Connection, resistance R 3b Second terminal and HBT transistor Q 6b Collector, HBT transistor Q 6b Base, capacitor C 3b First end, HBT transistor Q 8b Base electrodes are connected together, HBT transistor Q 6b Emitter and HBT transistor Q 7b Base and HBT transistor Q 7b Collectors are connected together, HBT transistor Q 7b Grounded emitter, capacitor C 3b Second ground, HBT transistor Q 8b Collector and power supply VCC 2b And (5) connection.
The bias voltage detection unit comprises a resistor R 5b Resistance R 6b Resistance R 7b Resistance R 8b Resistance R 9b Diode D 1b And HBT transistor Q 9b . Resistor R 5b First end and resistor R 4b First end, HBT transistor Q 8b The emitters are connected together, the resistor R 5b Second end and resistor R 7b First end, diode D 1b The positive electrodes are connected together, diode D 1b Negative electrode and resistor R 6b The first end is connected with the resistor R 6b The second end is grounded, resistance R 7b Second terminal and HBT transistor Q 9b Base connection, HBT transistor Q 9b Emitter and resistor R 9b The first end is connected with the resistor R 9b The second end is grounded, resistance R 8b First end and power VCC 7b And (5) connection.
With the increase of the output power of the linear power amplifier, the resistor R is used for self-adaptive bias of the final amplifier 4b Is also gradually increased, and thus, can be applied to HBT transistor Q 8b The emitter obtains a voltage value V which increases with the increase of the output power 1 HBT transistor Q 9b For applying voltage V 1 Amplifying, diode D 1b For compensating HBT transistor Q 9b V which occurs with increasing temperature of BE junction(s) be Voltage drop, ensure HBT transistor Q 9b Has a temperature uniformity. Resistor R 5b Resistance R 6b Diode D 1b Co-determining HBT transistor Q 9b Direct current operating point of (2), resistance R 8b And resistance R 9b For setting an output level representative value of the bias voltage detecting unit.
The low envelope impedance unit comprises a resistor R 10b Inductance L 3b Capacitance C 5b And pHEMT transistor M 1b . Resistor R 10b First end and resistor R 8b Second terminal, HBT transistor Q 9b The collectors are connected together, resistor R 10b Second terminal and pHEMT transistor M 1b Gate connected, pHEMT transistor M 1b Source and inductance L 3b The first end is connected with the inductor L 3b Second end and capacitor C 5b The first end is connected with a capacitor C 5b Second ground, pHEMT transistor M 1b Drain and resistor R 4b Second end, second end of inter-stage matching network 1b, HBT transistor Q 5b The bases are connected together.
Resistor R in low envelope impedance unit 10b Mainly plays a role of radio frequency signal isolation, and an inductor L 3b And capacitor C 5b The composed signal path presents low resistance at envelope frequency, presents high resistance at linear power amplifier working frequency, and the control voltage provided by the bias voltage detection unit can control pHEMT transistor M 1b So that it exhibits variable resistance characteristics. pHEMT transistor M 1b And inductance L 3b Capacitance C 5b The controllable low-resistance envelope frequency-to-ground path is formed together, and the controllable low-resistance envelope frequency-to-ground path is provided for the input end of the final amplification tube of the linear power amplifier, so that adverse effects of memory effect on the linearity of the linear power amplifier are restrained.
Example 4:
a high linearity power amplifier suitable for 5G system, as shown in figure 2, includes a radio frequency amplifying unit, an adaptive bias unit, a bias voltage detecting unit and a low envelope impedance unit. Specifically, the radio frequency amplifying unit comprises a first-stage amplifier and a last-stage amplifier which are cascaded. The adaptive bias unit is correspondingly provided with an adaptive bias of the first-stage amplifier and an adaptive bias of the final-stage amplifier.
The radio frequency amplifying unit comprises an inductor L 1b Inductance L 2b Capacitance C 1b Capacitance C 4b HBT transistor Q 1b HBT transistor Q 5b Input matching network 1b 、 An inter-stage matching network 1b and an output matching network 1b. Capacitor C 1b First end and signal input end IN 1b Connection, capacitance C 1b A second terminal connected to the first terminal of the input matching network 1b, a HBT transistor Q 1b Emitter connected to ground, HBT transistor Q 1b Collector, inductance L 1b The first end is connected with the first end of the interstage matching network 1b, the inductance L 1b Second end and power VCC 4b Connection, HBT transistor Q 5b Emitter connected to ground, HBT transistor Q 5b Collector, inductance L 2b The first end is connected with the first end of the output matching network 1b, the inductance L 2b Second end and power VCC 1b A second end of the output matching network 1b is connected with a capacitor C 4b The first end is connected with a capacitor C 4b A second terminal and a signal output terminal OUT 1b And (5) connection.
In the adaptive bias unit, HBT transistor Q 2b HBT transistor Q 3b HBT transistor Q 4b Resistance R 1b Resistance R 2b And capacitor C 2b An adaptive bias for the first stage amplifier is composed. HBT transistor Q 6b HBT transistor Q 7b HBT transistor Q 8b Resistance R 3b Resistance R 4b And capacitor C 3b An adaptive bias for the second stage amplifier is composed. Resistor R 1b First end and power VCC 6b Connection, resistance R 1b Second terminal and HBT transistor Q 2b Collector, HBT transistor Q 2b Base, capacitor C 2b First end, HBT transistor Q 4b Base electrodes are connected together, HBT transistor Q 2b Emitter and HBT transistor Q 3b Base and HBT transistor Q 3b Collectors are connected together, HBT transistor Q 3b The emitter is connected with the ground, the capacitor C 2b The second terminal is connected to ground, HBT transistor Q 4b Collector and power supply VCC 5b Connection, HBT transistor Q 4b Emitter and resistor R 2b The first end is connected with the resistor R 2b Second end and input matching network 1b second end, HBT transistor Q 1b The bases are connected together, the resistor R 3b First end and power VCC 3b Connection, resistance R 3b Second terminal and HBT transistor Q 6b Collector, HBT transistor Q 6b Base, capacitor C 3b First end, HBT transistor Q 8b Base electrodes are connected together, HBT transistor Q 6b Emitter and HBT transistor Q 7b Base and HBT transistor Q 7b Collectors are connected together, HBT transistor Q 7b The emitter is connected with the ground, the capacitor C 3b The second terminal is connected to ground, HBT transistor Q 8b Collector and power supply VCC 2b And (5) connection.
The bias voltage detection unit comprises a resistor R 5b Resistance R 6b Resistance R 7b Resistance R 8b Resistance R 9b Diode D 1b And HBT transistor Q 9b . Resistor R 5b First end and resistor R 4b First end, HBT transistor Q 8b The emitters are connected together, the resistor R 5b Second end and resistor R 7b First end, diode D 1b The positive electrodes are connected together, diode D 1b Negative electrode and resistor R 6b The first end is connected with the resistor R 6b The second end is connected with the ground, and the resistor R 7b Second terminal and HBT transistor Q 9b Base connection, HBT transistor Q 9b Emitter and resistor R 9b The first end is connected with the resistor R 9b The second end is connected with the ground, and the resistor R 8b First end and power VCC 7b And (5) connection.
The low envelope impedance unit comprises a resistor R 10b Inductance L 3b Capacitance C 5b And pHEMT transistor M 1b . Resistor R 10b First end and resistor R 8b Second terminal, HBT transistor Q 9b The collectors are connected together, resistor R 10b Second terminal and pHEMT transistor M 1b Gate connection, pHEMT transistorM 1b Source and inductance L 3b The first end is connected with the inductor L 3b Second end and capacitor C 5b The first end is connected with a capacitor C 5b The second end is connected with the ground, pHEMT transistor M 1b Drain and resistor R 4b Second end, second end of inter-stage matching network 1b, HBT transistor Q 5b The bases are connected together.
As shown in fig. 2, the working principle of the present invention is as follows:
radio frequency signal passing through signal input IN 1b Into a high-linearity power amplifier through a capacitor C 1b Then, the signal is input into the input matching network 1b to change the impedance, and the signal is transmitted through the HBT transistor Q 1b Amplifying the signal, changing the impedance of the signal by the inter-stage matching network 1b, and then using the HBT transistor Q 5b Amplifying the signal again, changing the impedance of the signal via the output matching network 1b, and passing through the capacitor C 4b Then, by the signal output terminal OUT 1b And outputting.
In the DC bias unit, HBT transistor Q 2b HBT transistor Q 3b HBT transistor Q 4b Resistance R 1b Resistance R 2b And capacitor C 2b An adaptive bias comprising a first stage amplifier; HBT transistor Q 6b HBT transistor Q 7b HBT transistor Q 8b Resistance R 3b Resistance R 4b And capacitor C 3b An adaptive bias of the final amplifier is formed. In the adaptive bias of the final stage amplifier, HBT transistor Q 6b And HBT transistor Q 7b The base and collector of the tube are shorted to form a dual diode series structure. Through HBT transistor Q 8b Post-flow HBT transistor Q 5b Current magnitude and HBT transistor Q 6b The current is proportional to the current. And as the input power increases, HBT transistor Q 8b V also occurs in BE junction diodes be The voltage decreases. And HBT transistor Q 6b And HBT transistor Q 7b Series to HBT transistor Q 8b The transistor base provides a relatively stable diode clamping voltage, so that the HBT transistor Q 8b V of pipe be Voltage reduction can compensate for HBT transistor Q 5b The upper BE junction voltage decreases as the input power increases. Decoupling capacitor C 3b Inhibit HBT transistor Q 8b The base node voltage changes, increasing the linear power level of the HBT power amplifier. The self-adaptive bias structure of the first-stage amplifier is identical to that of the final-stage amplifier, and the functions are consistent. In summary, the self-adaptive bias structure can inhibit bias point drift of the HBT transistor due to self-heating effect, improve linearity of the power amplifier, and improve output power.
With the increase of the output power of the linear power amplifier, the resistor R is used for self-adaptive bias of the final amplifier 4b Is also gradually increased, and thus, can be applied to HBT transistor Q 8b The emitter obtains a voltage value V which increases with the increase of the output power 1 HBT transistor Q 9b For applying voltage V 1 Amplifying, diode D 1b For compensating HBT transistor Q 9b V which occurs with increasing temperature of BE junction(s) be Voltage drop, ensure HBT transistor Q 9b Has a temperature uniformity. Resistor R 5b Resistance R 6b Diode D 1b Co-determining HBT transistor Q 9b Direct current operating point of (2), resistance R 8b And resistance R 9b For setting an output level representative value of the bias voltage detecting unit.
Resistor R in low envelope impedance unit 10b Mainly plays a role of radio frequency signal isolation, and an inductor L 3b And capacitor C 5b The composed signal path presents low resistance at envelope frequency, presents high resistance at linear power amplifier working frequency, and the control voltage provided by the bias voltage detection unit can control pHEMT transistor M 1b So that it exhibits variable resistance characteristics.
pHEMT transistor M 1b And inductance L 3b Capacitance C 5b The controllable low-resistance envelope frequency-to-ground path is formed together, and the controllable low-resistance envelope frequency-to-ground path is provided for the input end of the final amplification tube of the linear power amplifier, so that adverse effects of memory effect on the linearity of the linear power amplifier are restrained.
As shown in fig. 3, the low-side and high-side output third-order intermodulation curves of the conventional linear power amplifier are unequal, and as the output power increases, the distance between the low-side and high-side output third-order intermodulation curves tends to be larger and larger. As shown in FIG. 4, the high-linearity power amplifier has high coincidence degree of the low-side and high-side output third-order intermodulation point curves, and the phenomenon that the distance between the low-side and high-side output third-order intermodulation point curves is increased obviously does not occur with the increase of output power.
The linear characteristic of a linear power amplifier is generally characterized by using a curve of output third-order intermodulation point of the linear power amplifier along with output power:
at the same output power, the smaller the output third-order intermodulation value is, the better the linearity is.
At the same output power, the higher the coincidence degree of the output third-order intermodulation point curves of the low side and the high side is, the better the linearity is.
Comparing fig. 3 and 4, it can be found that the high linearity power amplifier of the present invention is significantly superior to the conventional linear power amplifier.
The invention is added with the bias voltage detection unit and the low envelope impedance unit on the basis of the traditional linear power amplifier, can reduce the influence of the memory effect on the linear power amplifier under the condition of large working bandwidth, and improves the linearity of the linear power amplifier. The linear power amplifier memory effect is mainly caused by envelope modulation generated by the signal at the input end of the final amplifying tube. When the output power is smaller, the linearity of the linear power amplifier is higher, the memory effect is smaller, and the linearity of the radio frequency signal output by the transmitter is hardly influenced, so that the pHEMT transistor in the low-envelope impedance unit presents a high configuration in order to achieve the conventional electrical characteristics of the linear power amplifier such as small signal gain, temperature stability and the like.
With the gradual increase of the output power, the bias voltage detection unit detects the gradually increased voltage signal, the gradually increased voltage signal becomes a grid control signal of the pHEMT transistor in the low-envelope impedance unit after amplification, and the magnitude of the impedance value of the low-envelope impedance channel in the access signal path is controlled by the conduction degree of the pHEMT transistor. Because the low-envelope impedance unit has the frequency selection characteristic, the low-envelope impedance unit constantly presents a high configuration at the working frequency of the power amplifier, and a controllable low-resistance envelope frequency-to-ground path is provided for the input end of the final amplification tube of the linear power amplifier at the baseband frequency, thereby inhibiting the adverse effect of the memory effect on the linearity of the linear power amplifier.
The foregoing description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and any simple modification, equivalent variation, etc. of the above embodiment according to the technical matter of the present invention fall within the scope of the present invention.
Claims (6)
1. The high-linearity power amplifier suitable for the 5G system is characterized by comprising a radio frequency amplifying unit, an adaptive bias unit, a bias voltage detecting unit and a low envelope impedance unit; the radio frequency amplifying unit comprises a plurality of cascaded amplifying circuits, and the adaptive bias unit is provided with a plurality of adaptive bias circuits corresponding to the plurality of amplifying circuits; the amplifying circuit comprises an HBT transistor Q n The HBT transistor Q n Is grounded, HBT transistor Q of primary amplifying circuit n The base electrode of the (B) is connected with the input matching network, and the HBT transistor Q of the amplifying circuit of the final stage n The collector of (a) is connected with the output matching network, and the HBT transistor Q of the front and back adjacent amplifying circuits n The device is connected with the base electrode through the collector electrode, and an interstage matching network is arranged between the collector electrode and the base electrode; the self-adaptive bias circuit passes through a resistor R m+1 HBT transistor Q of amplification circuit n Is connected with the base electrode of the transistor; one end of the bias voltage detection unit is arranged on the self-adaptive bias circuit and the resistor R of the final stage m+1 The other end of the low-envelope impedance unit is connected with the low-envelope impedance unit;
the low envelope impedance unit comprises a resistor R t Inductance L t Capacitance C t And pHEMT transistor M t pHEMT transistor M t Gate pass resistance R of (2) t Is connected with the bias voltage detection unit, and the source electrode is connected with the inductor L t Is connected with the first end of the drain electrodeResistors R respectively connected with self-adaptive bias circuits of final stage m+1 HBT transistor Q of amplifying circuit of final stage n Is connected with the base electrode of the transistor; inductance L t A second terminal of (C) and a capacitor C t Is connected to the first end of the capacitor C t Is grounded;
the bias voltage detection unit is used for detecting the voltage signal of the self-adaptive bias circuit of the final stage, amplifying the voltage signal and inputting the amplified voltage signal into the low-envelope impedance unit to serve as the pHEMT transistor M of the low-envelope impedance unit t To be the gate control signal of the final stage of the amplifying circuit n The input end provides a controllable low-resistance envelope frequency to ground path, so that adverse effects of memory effect on linearity of the linear power amplifier are restrained;
the bias voltage detection unit comprises a resistor R h Resistance R h+1 Resistance R h+2 Resistance R h+3 Resistance R h+4 Diode D h And HBT transistor Q h The method comprises the steps of carrying out a first treatment on the surface of the The resistor R h An adaptive bias circuit and a resistor R arranged at the first end of the final stage m+1 And the second ends are respectively connected with the resistor R h+2 Is a first terminal of diode D h Is connected with the anode of the diode D h Negative electrode of (2) and resistor R h+1 Is connected with the first end of the resistor R h+1 Is grounded; resistor R h+2 And HBT transistor Q h Is connected to the base of HBT transistor Q h Emitter and resistor R of (2) h+4 Is connected with the first end of the resistor R h+4 Is grounded at the second end of the resistor R h+3 Is connected to a power source and the second terminals are respectively connected to HBT transistor Q h Collector, resistor R of (2) t Is connected to the first end of the housing.
2. A high linearity power amplifier suitable for use in a 5G system as defined in claim 1, wherein said adaptive biasing circuit comprises a HBT transistor Q m HBT transistor Q m+1 HBT transistor Q m+2 Resistance R m And capacitor C m The method comprises the steps of carrying out a first treatment on the surface of the Resistor R m Is connected to a power source and the second terminal is connected to the HBT transistor Q m Collector, base and capacitor C of (C) m First end of (1), HBT transistor Q m+2 Is connected with the base electrode of the transistor; HBT transistor Q m Emitter and HBT transistor Q m+1 Is connected with the base and the collector of the transistor Q m+1 Grounded emitter, capacitor C m Is grounded; HBT transistor Q m+2 The collector of (C) is connected with a power supply, and the emitter is connected with a resistor R m+1 Is connected to the first end of the housing; resistance R of the bias voltage detection unit h Resistors R respectively connected with the self-adaptive bias circuit of the final stage m+1 HBT transistor Q of an adaptive bias circuit of a final stage m+2 Emitter connection of (c).
3. The high linearity power amplifier of claim 1 wherein said amplifying circuit further comprises an inductance L n Capacitance C n The HBT transistor Q n Collector and inductance L of (2) n Is connected with the first end of the inductor L n Is connected with a power supply; capacitor C of amplifying circuit of first stage n Is connected with the first end of the signal input end IN n A second end of the input matching network is connected with the first end of the input matching network, and the second end of the input matching network is connected with the HBT transistor Q of the amplifying circuit of the first stage n Is connected with the base electrode of the transistor; capacitor C of the amplifying circuit of the final stage n Is connected with the first end of the inductor L n A first end connected to the signal output end OUT n And (5) connection.
4. A high linearity power amplifier adapted for use in a 5G system according to claim 3, wherein said radio frequency amplifying unit comprises two cascaded amplifying circuits, said adaptive biasing unit being provided with two adaptive biasing circuits, respectively.
5. The high linearity power amplifier of claim 4, wherein said input matching network and HBT transistor Q of the amplifying circuit of the first stage n Is not equal to the base of the (c)The self-adaptive bias circuit of the first stage is arranged between the first stage and the second stage; HBT transistor Q of amplifying circuit of the first stage n HBT transistor Q of amplifying circuit of collector and final stage n An inter-stage matching network is arranged between the bases of the stages, and the inter-stage matching network is connected with an HBT transistor Q of an amplifying circuit of a final stage n An adaptive bias circuit of a final stage is arranged between the bases of the pair of transistors.
6. A high linearity power amplifier suitable for use in a 5G system according to claim 3, wherein said inductance L n Is a choke inductance for powering the amplifying circuit.
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