WO2024099059A1 - Passive circuit in bypass mode of radio frequency receiving module, and radio frequency receiving module - Google Patents

Passive circuit in bypass mode of radio frequency receiving module, and radio frequency receiving module Download PDF

Info

Publication number
WO2024099059A1
WO2024099059A1 PCT/CN2023/125978 CN2023125978W WO2024099059A1 WO 2024099059 A1 WO2024099059 A1 WO 2024099059A1 CN 2023125978 W CN2023125978 W CN 2023125978W WO 2024099059 A1 WO2024099059 A1 WO 2024099059A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
receiving module
circuit
drain
capacitor
Prior art date
Application number
PCT/CN2023/125978
Other languages
French (fr)
Chinese (zh)
Inventor
贾钧浩
郭嘉帅
Original Assignee
深圳飞骧科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳飞骧科技股份有限公司 filed Critical 深圳飞骧科技股份有限公司
Publication of WO2024099059A1 publication Critical patent/WO2024099059A1/en

Links

Definitions

  • the utility model relates to the technical field of signal processing, and in particular to a passive circuit in a bypass mode of a radio frequency receiving module and a radio frequency receiving module.
  • the RF receiving circuit (RF receiving module) is an intermediate circuit used to receive signals and amplify them before outputting them to the next stage circuit.
  • the existing RF receiving circuit may receive a high-power signal. At this time, the signal does not need to be amplified, but the power signal needs to be attenuated so that the high-power signal is attenuated into the required power signal for output to the next stage circuit.
  • the existing RF receiving circuit only has a power amplifier for amplifying the signal, and there is no related circuit for attenuating the high-power signal. That is, the existing RF receiving circuit cannot attenuate the high-power signal.
  • the existing RF receiving circuit cannot attenuate the high-power signal.
  • the utility model aims to provide a passive circuit in a bypass mode of a radio frequency receiving module to solve the problem of the contradiction between the low power requirement of the next stage circuit of the existing low noise amplifier and the excessive power signal received by the radio frequency receiving circuit.
  • the utility model provides a wireless receiver in bypass mode.
  • a source circuit comprising a signal input terminal, a first capacitor, an attenuation circuit, a power supply inductor, a first transistor, a second transistor and a signal output terminal;
  • the first end of the first capacitor is connected to the signal input end, the first end of the attenuation circuit is connected to the second end of the first capacitor, and the second end of the attenuation circuit is connected to the signal output end;
  • a first end of the power supply inductor is connected to a power supply voltage, and a second end of the power supply inductor is connected to the signal output end;
  • the gate of the first transistor is connected to the signal input terminal, and the source of the first transistor is grounded;
  • the source of the second transistor is connected to the drain of the first transistor, the gate of the second transistor is connected to the power supply voltage, and the drain of the second transistor is respectively connected to the second end of the power supply inductor and the signal output end;
  • the passive circuit When the passive circuit is in the bypass mode of the RF receiving module, the signal received by the signal input end passes through the attenuation circuit, and the signal input by the signal input end is attenuated by the attenuation circuit and then output to the signal output end.
  • the attenuation circuit includes a third transistor, a first resistor, a fourth transistor, a second resistor, a fifth transistor, a third resistor, a sixth transistor, a fourth resistor and a fifth resistor;
  • the gate of the third transistor is connected to the first control electrode voltage, the source of the third transistor is connected to the second end of the first capacitor as the first end of the attenuation circuit, and the two ends of the first resistor are respectively connected to the source of the third transistor and the drain of the third transistor;
  • the gate of the fourth transistor is connected to the second control electrode voltage, the source of the fourth transistor is connected to the drain of the third transistor, and the two ends of the second resistor are respectively connected to the source of the fourth transistor and the drain of the fourth transistor;
  • a first end of the fifth resistor is connected to the drain of the fourth transistor, and a second end of the fifth resistor is grounded;
  • the gate of the fifth transistor is connected to the third control electrode voltage.
  • the source of the third resistor is connected to the first end of the fifth resistor, and the two ends of the third resistor are respectively connected to the source of the fifth transistor and the drain of the fifth transistor;
  • the gate of the sixth transistor is connected to the fourth control electrode voltage
  • the source of the sixth transistor is connected to the drain of the fifth transistor
  • the two ends of the fourth resistor are respectively connected to the source of the sixth transistor and the drain of the sixth transistor
  • the drain of the sixth transistor is connected to the signal output end as the second end of the attenuation circuit.
  • the attenuation circuit also includes a second capacitor and a seventh transistor; the first end of the second capacitor is connected to the first end of the fifth resistor, the drain of the seventh transistor is connected to the second end of the second capacitor, the gate of the seventh transistor is connected to the fifth control electrode voltage, and the source of the seventh transistor is grounded.
  • the attenuation circuit also includes a path inductor and an eighth transistor; the first end of the path inductor is connected to the signal input end, the drain of the eighth transistor is connected to the second end of the path inductor, the gate of the eighth transistor is connected to the sixth control electrode voltage, and the source of the eighth transistor is grounded; the gate of the first transistor is connected to the drain of the eighth transistor.
  • the attenuation circuit further includes a third capacitor, a first end of the third capacitor is connected to the drain of the sixth transistor, and a second end of the third capacitor is connected to the signal output end as the second end of the attenuation circuit.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all NMOS transistors.
  • the passive circuit further includes a fourth capacitor, a first end of the fourth capacitor is respectively connected to the drain of the second transistor and the second end of the power supply inductor, and a second end of the fourth capacitor is connected to the signal output end.
  • the passive circuit further includes a feedback inductor, a first end of the feedback inductor is connected to the source of the first transistor, and a second end of the feedback inductor is grounded.
  • the utility model provides a radio frequency receiving module, wherein the radio frequency receiving module includes the passive circuit in the bypass mode of the radio frequency receiving module as described above.
  • the passive circuit in the bypass mode of the RF receiving module of the utility model realizes the function of attenuating high-power signals by adding an attenuation circuit between the first capacitor and the signal output terminal for attenuating the signal input from the signal input terminal and then outputting it.
  • the high-power signal can then be attenuated into the required power signal to be output to the next-stage circuit, thus solving the contradiction between the low-power requirement of the next-stage circuit of the existing low-noise amplifier and the excessively high-power signal received by the RF receiving circuit.
  • FIG1 is a circuit diagram of a passive circuit in a bypass mode of a radio frequency receiving module provided by an embodiment of the present utility model.
  • An embodiment of the utility model provides a passive circuit 100 in a bypass mode of a radio frequency receiving module, as shown in FIG1 , comprising a signal input terminal VIN, a first capacitor C1, an attenuation circuit 10, a power supply inductor Ld, a first transistor M1, a second transistor M2 and a signal output terminal VOUT.
  • the passive circuit 100 in the bypass mode of the RF receiving module is hereinafter referred to as the passive circuit.
  • the first end of the first capacitor C1 is connected to the signal input terminal VIN.
  • One end is connected to the second end of the first capacitor C1 , and the second end of the attenuation circuit 10 is connected to the signal output end VOUT.
  • a first end of the power supply inductor Ld is connected to the power supply voltage VDD, and a second end of the power supply inductor Ld is connected to the signal output terminal VOUT.
  • a gate of the first transistor M1 is connected to the signal input terminal VIN, and a source of the first transistor M1 is grounded.
  • the source of the second transistor M2 is connected to the drain of the first transistor M1 , the gate of the second transistor M2 is connected to the power supply voltage Vb, and the drain of the second transistor M2 is respectively connected to the second end of the power supply inductor Ld and the signal output end VOUT.
  • the passive circuit 100 When the passive circuit 100 is in the RF receiving module bypass mode, the signal received by the signal input terminal VIN passes through the attenuation circuit 10, and the attenuation circuit 10 attenuates the signal input to the signal input terminal VIN and outputs it to the signal output terminal VOUT.
  • the attenuation circuit 10 includes a third transistor S3, a first resistor R1, a fourth transistor S4, a second resistor R2, a fifth transistor S5, a third resistor R3, a sixth transistor S6, a fourth resistor R4 and a fifth resistor R5.
  • the gate of the third transistor S3 is connected to the first control electrode voltage VG3
  • the source of the third transistor S3 is connected to the second end of the first capacitor C1 as the first end of the attenuation circuit 10
  • the two ends of the first resistor R1 are respectively connected to the source of the third transistor S3 and the drain of the third transistor S3.
  • the gate of the fourth transistor S4 is connected to the second control electrode voltage VG4, the source of the fourth transistor S4 is connected to the drain of the third transistor S3, and both ends of the second resistor R2 are connected to the source of the fourth transistor S4 and the drain of the fourth transistor S4 respectively.
  • a first end of the fifth resistor R5 is connected to the drain of the fourth transistor S4 , and a second end of the fifth resistor R5 is grounded.
  • the gate of the fifth transistor S5 is connected to the third control electrode voltage VG5, the source of the fifth transistor S5 is connected to the first end of the fifth resistor R5, and the two ends of the third resistor R3 are respectively connected to the source of the fifth transistor S5 and the drain of the fifth transistor S5.
  • the gate of the sixth transistor S6 is connected to the fourth control electrode voltage VG6.
  • the source of S6 is connected to the drain of the fifth transistor S5, the two ends of the fourth resistor R4 are respectively connected to the source of the sixth transistor S6 and the drain of the sixth transistor S6, and the drain of the sixth transistor S6 is connected to the signal output terminal VOUT as the second end of the attenuation circuit 10.
  • the attenuation circuit 10 further includes a second capacitor C2 and a seventh transistor S2.
  • the first end of the second capacitor C2 is connected to the first end of the fifth resistor R5, the drain of the seventh transistor S2 is connected to the second end of the second capacitor C2, the gate of the seventh transistor S2 is connected to the fifth control electrode voltage VG2, and the source of the seventh transistor S2 is grounded.
  • the source of the fifth transistor S5 is connected to the first end of the second capacitor C2 , that is, the source of the fifth transistor S5 is indirectly connected to the first end of the fifth resistor R5 through the first end of the second capacitor C2 .
  • the attenuation circuit 10 further includes a path inductor L1 and an eighth transistor S1 .
  • the first end of the path inductor L1 is connected to the signal input end VIN, the drain of the eighth transistor S1 is connected to the second end of the path inductor L1, the gate of the eighth transistor S1 is connected to the sixth control electrode voltage VG1, and the source of the eighth transistor S1 is grounded.
  • the gate of the first transistor M1 is connected to the drain of the eighth transistor S1 , that is, the gate of the first transistor M1 is indirectly connected to the signal input terminal VIN through the drain of the eighth transistor S1 and the path inductor L1 in sequence.
  • the attenuation circuit 10 also includes a third capacitor C3, a first end of the third capacitor C3 is connected to the drain of the sixth transistor S6; the second end of the third capacitor C3 is connected to the signal output terminal VOUT as the second end of the attenuation circuit 10, that is, the drain of the sixth transistor S6 is indirectly connected to the signal output terminal VOUT through the third capacitor C3.
  • the passive circuit 100 also includes a fourth capacitor C4, a first end of the fourth capacitor C4 is respectively connected to the drain of the second transistor M2 and the second end of the power supply inductor Ld, and a second end of the fourth capacitor C4 is connected to the signal output terminal VOUT, that is, the drain of the second transistor M2 and the second end of the power supply inductor Ld are indirectly connected to the signal output terminal VOUT through the fourth capacitor C4.
  • the passive circuit 100 further includes a feedback inductor Ls, a first end of the feedback inductor Ls is connected to the source of the first transistor M1, and a second end of the feedback inductor Ls is grounded.
  • the source of the transistor M1 is indirectly grounded through the feedback inductor Ls.
  • the feedback inductor Ls is the source negative feedback inductor of the first transistor M1.
  • the function of the feedback inductor Ls is to increase the real part of the input impedance, which can make matching more convenient and reduce the matching loss. At the same time, it can make the optimal noise source impedance and the conjugate matching impedance closer, and can also obtain a better noise factor and input matching.
  • the first transistor M1 , the second transistor M2 , the third transistor S3 , the fourth transistor S4 , the fifth transistor S5 , the sixth transistor S6 , the seventh transistor S2 and the eighth transistor S1 are all NMOS transistors.
  • the first capacitor C1 and the power supply inductor Ld form an output matching circuit of the low noise amplifier, and the power supply inductor Ld also plays the role of the power supply inductor, that is, the drain inductor of the low noise amplifier;
  • the first transistor M1 and the second transistor M2 form a low noise amplifier with a common source and common gate structure, that is, a transistor for signal amplification in the amplification mode;
  • the feedback inductor Ls is the source feedback inductor of the low noise amplifier;
  • the fourth capacitor C4 is a DC blocking capacitor at the output end in the amplification mode;
  • the first capacitor C1, the second capacitor C2 and the third capacitor C3 are all DC blocking capacitors, among which the third capacitor C3 also has a matching function;
  • the third transistor S3 to the eighth transistor S1 are MOS switch tubes,
  • the first resistor R1 to the fifth resistor R5 are parallel resistors of the drain and source of the third transistor S3 to the sixth transistor S6;
  • the sixth control electrode voltage VG1 controls the eighth transistor S1 to turn on
  • the fifth control electrode voltage VG2 controls the seventh transistor S2 to turn off
  • the first control electrode voltage VG3 to the fourth control electrode voltage VG6 respectively control the turning on of the third transistor S3 to the sixth transistor S6 to ensure that the power signal is attenuated from the bypass circuit (bypass path) before being output.
  • the first transistor M1 and the second transistor M2 do not have an amplification effect, and the signal input at the signal input terminal VIN no longer passes through the first transistor M1 and the second transistor M2; in the bypass mode, the third transistor S3 to the sixth transistor S6 in the attenuation circuit 10 are turned on, and the power signal passes through the bypass circuit, that is, when the third transistor S3 to the sixth transistor S6 are turned on,
  • the opened channel resistors, the first resistor R1 to the fourth resistor R4, and the fifth resistor R5 in parallel can be used to form a T-type attenuation circuit 10 (attenuation network).
  • the sixth control electrode voltage VG1 controls the eighth transistor S1 to turn on, forming a path from the signal input terminal VIN of the bypass circuit to the ground through the path inductor L1, thereby improving the input matching in the bypass mode, reducing input reflection, and obtaining a better eighth transistor S1.
  • the fifth control electrode voltage VG2 controls the turn-off of the seventh transistor S2, and the power signal is attenuated by the attenuation circuit 10 and then output to the signal output terminal VOUT;
  • the first control electrode voltage VG3 to the fourth control electrode voltage VG6 respectively control the turn-off of the third transistor S3 to the sixth transistor S6, and the first resistor R1 to the fourth resistor R4 can make the drain and source voltages of the third transistor S3 to the sixth transistor S6 consistent, thereby ensuring the turn-off of the switch; but at this time, the third transistor S3 to the sixth transistor S6 will have parasitic capacitance, and the power signal will leak from this path to the output end, resulting in the deterioration of the isolation of the circuit. Therefore, the fifth control electrode voltage VG2 is required to control the turn-on of the seventh transistor S2, so that the power signal leaked to the bypass path is pulled down to the ground
  • connections are all electrical connections or electrical connections, that is, the two or more connected devices are all electrically connected or electrically connected.
  • the passive circuit 100 in the bypass mode of the RF receiving module of the present embodiment realizes the function of attenuating high-power signals by adding an attenuation circuit 10 between the first capacitor C1 and the signal output terminal VOUT for attenuating the signal input at the signal input terminal VIN and then outputting it.
  • the high-power signal can then be attenuated into the required power signal to be output to the next-stage circuit, thus solving the contradiction between the low-power requirement of the next-stage circuit of the existing low-noise amplifier and the excessively high-power signal received by the RF receiving circuit.
  • the present invention also provides another embodiment, a radio frequency receiving module, wherein the radio frequency receiving module includes the passive circuit 100 in the bypass mode of the radio frequency receiving module in the above embodiment.
  • the RF receiving module in this embodiment includes the RF receiving module in the above embodiment
  • the passive circuit 100 in the module bypass mode can also achieve the technical effect achieved by the passive circuit 100 in the RF receiving module bypass mode in the above embodiment, which will not be elaborated here.

Landscapes

  • Amplifiers (AREA)

Abstract

Provided in the present application are a passive circuit in a bypass mode of a radio frequency receiving module, and a radio frequency receiving module. The passive circuit in the bypass mode of the radio frequency receiving module comprises a signal input end, a first capacitor, an attenuation circuit, a power supply inductor, a first transistor, a second transistor and a signal output end. By means of the passive circuit in the bypass mode of the radio frequency receiving module in the present application, the function of attenuating a high-power signal is achieved, such that the high-power signal can be attenuated into a required power signal to be output to a next-stage circuit, and the contradiction between a low-power requirement of the next-stage circuit of existing low-noise amplifiers and an overpower signal received by a radio frequency receiving circuit is thus solved.

Description

射频接收模组旁路模式下的无源电路及射频接收模组Passive circuit and RF receiving module in RF receiving module bypass mode 【技术领域】[Technical field]
本实用新型涉及信号处理技术领域，尤其涉及一种射频接收模组旁路模式下的无源电路及射频接收模组。The utility model relates to the technical field of signal processing, and in particular to a passive circuit in a bypass mode of a radio frequency receiving module and a radio frequency receiving module.
【背景技术】【Background technique】
射频接收电路(射频接收模组)是一种用于接收信号并将其放大后输出至下一级电路的中间电路。The RF receiving circuit (RF receiving module) is an intermediate circuit used to receive signals and amplify them before outputting them to the next stage circuit.
现有的射频接收电路在接收功率信号时，会存在接收到大功率信号的可能，此时的信号是不需要进行放大，而是需要将功率信号进行衰减，以使大功率信号衰减成所需的功率信号，以输出至下一级电路。When receiving a power signal, the existing RF receiving circuit may receive a high-power signal. At this time, the signal does not need to be amplified, but the power signal needs to be attenuated so that the high-power signal is attenuated into the required power signal for output to the next stage circuit.
但现有的射频接收电路中只存在对信号进行放大的功率放大器，并不存在对大功率信号进行衰减的相关电路，即现有射频接收电路并不能对大功率信号进行衰减，相应的则是现有的低噪声放大器的下一级电路低功率需求和射频接收电路接收到过大功率信号之间存在矛盾。However, the existing RF receiving circuit only has a power amplifier for amplifying the signal, and there is no related circuit for attenuating the high-power signal. That is, the existing RF receiving circuit cannot attenuate the high-power signal. Correspondingly, there is a contradiction between the low-power requirement of the next-stage circuit of the existing low-noise amplifier and the excessively high-power signal received by the RF receiving circuit.
因此，有必要提供一种射频接收模组旁路模式下的无源电路来解决上述问题。Therefore, it is necessary to provide a passive circuit in the bypass mode of the RF receiving module to solve the above problems.
【实用新型内容】[Contents of the utility model]
本实用新型的目的在于提供一种射频接收模组旁路模式下的无源电路，以解决现有的低噪声放大器的下一级电路低功率需求和射频接收电路接收到过大功率信号之间存在矛盾的问题。The utility model aims to provide a passive circuit in a bypass mode of a radio frequency receiving module to solve the problem of the contradiction between the low power requirement of the next stage circuit of the existing low noise amplifier and the excessive power signal received by the radio frequency receiving circuit.
第一方面，本实用新型提供了一种射频接收模组旁路模式下的无 源电路，其包括信号输入端、第一电容、衰减电路、供电电感、第一晶体管、第二晶体管以及信号输出端；In the first aspect, the utility model provides a wireless receiver in bypass mode. A source circuit, comprising a signal input terminal, a first capacitor, an attenuation circuit, a power supply inductor, a first transistor, a second transistor and a signal output terminal;
所述第一电容的第一端与所述信号输入端连接，所述衰减电路的第一端与所述第一电容的第二端连接，所述衰减电路的第二端与所述信号输出端连接；The first end of the first capacitor is connected to the signal input end, the first end of the attenuation circuit is connected to the second end of the first capacitor, and the second end of the attenuation circuit is connected to the signal output end;
所述供电电感的第一端连接至电源电压，所述供电电感的第二端与所述信号输出端连接；A first end of the power supply inductor is connected to a power supply voltage, and a second end of the power supply inductor is connected to the signal output end;
所述第一晶体管的栅极与所述信号输入端连接，所述第一晶体管的源极接地；The gate of the first transistor is connected to the signal input terminal, and the source of the first transistor is grounded;
所述第二晶体管的源极与所述第一晶体管的漏极连接，所述第二晶体管的栅极连接至供电电压，所述第二晶体管的漏极分别连接至所述供电电感的第二端及所述信号输出端；The source of the second transistor is connected to the drain of the first transistor, the gate of the second transistor is connected to the power supply voltage, and the drain of the second transistor is respectively connected to the second end of the power supply inductor and the signal output end;
所述无源电路处于所述射频接收模组旁路模式时，所述信号输入端接收的信号经过所述衰减电路，并通过所述衰减电路对所述信号输入端输入的信号进行衰减后输出至所述信号输出端。When the passive circuit is in the bypass mode of the RF receiving module, the signal received by the signal input end passes through the attenuation circuit, and the signal input by the signal input end is attenuated by the attenuation circuit and then output to the signal output end.
更优的，所述衰减电路包括第三晶体管、第一电阻、第四晶体管、第二电阻、第五晶体管、第三电阻、第六晶体管、第四电阻以及第五电阻；More preferably, the attenuation circuit includes a third transistor, a first resistor, a fourth transistor, a second resistor, a fifth transistor, a third resistor, a sixth transistor, a fourth resistor and a fifth resistor;
所述第三晶体管的栅极连接至第一控制极电压，所述第三晶体管的源极作为所述衰减电路的第一端与所述第一电容的第二端连接，所述第一电阻的两端分别连接至所述第三晶体管的源极和所述第三晶体管的漏极；The gate of the third transistor is connected to the first control electrode voltage, the source of the third transistor is connected to the second end of the first capacitor as the first end of the attenuation circuit, and the two ends of the first resistor are respectively connected to the source of the third transistor and the drain of the third transistor;
所述第四晶体管的栅极连接至第二控制极电压，所述第四晶体管的源极与所述第三晶体管的漏极连接，所述第二电阻的两端分别连接所述第四晶体管的源极和所述第四晶体管的漏极；The gate of the fourth transistor is connected to the second control electrode voltage, the source of the fourth transistor is connected to the drain of the third transistor, and the two ends of the second resistor are respectively connected to the source of the fourth transistor and the drain of the fourth transistor;
所述第五电阻的第一端与所述第四晶体管的漏极连接，所述第五电阻的第二端接地；A first end of the fifth resistor is connected to the drain of the fourth transistor, and a second end of the fifth resistor is grounded;
所述第五晶体管的栅极连接至第三控制极电压，所述第五晶体管 的源极与所述第五电阻的第一端连接，所述第三电阻的两端分别连接所述第五晶体管的源极和所述第五晶体管的漏极；The gate of the fifth transistor is connected to the third control electrode voltage. The source of the third resistor is connected to the first end of the fifth resistor, and the two ends of the third resistor are respectively connected to the source of the fifth transistor and the drain of the fifth transistor;
所述第六晶体管的栅极连接至第四控制极电压，所述第六晶体管的源极与所述第五晶体管的漏极连接，所述第四电阻的两端分别连接所述第六晶体管的源极和所述第六晶体管的漏极，所述第六晶体管的漏极作为所述衰减电路的第二端与所述信号输出端连接。The gate of the sixth transistor is connected to the fourth control electrode voltage, the source of the sixth transistor is connected to the drain of the fifth transistor, the two ends of the fourth resistor are respectively connected to the source of the sixth transistor and the drain of the sixth transistor, and the drain of the sixth transistor is connected to the signal output end as the second end of the attenuation circuit.
更优的，所述衰减电路还包括第二电容以及第七晶体管；所述第二电容的第一端与所述第五电阻的第一端连接，所述第七晶体管的漏极与所述第二电容的第二端连接，所述第七晶体管的栅极连接至第五控制极电压，所述第七晶体管的源极接地。More preferably, the attenuation circuit also includes a second capacitor and a seventh transistor; the first end of the second capacitor is connected to the first end of the fifth resistor, the drain of the seventh transistor is connected to the second end of the second capacitor, the gate of the seventh transistor is connected to the fifth control electrode voltage, and the source of the seventh transistor is grounded.
更优的，所述衰减电路还包括通路电感以及第八晶体管；所述通路电感的第一端与所述信号输入端连接，所述第八晶体管的漏极与所述通路电感的第二端连接，所述第八晶体管的栅极连接至第六控制极电压，所述第八晶体管的源极接地；所述第一晶体管的栅极与所述第八晶体管的漏极连接。More preferably, the attenuation circuit also includes a path inductor and an eighth transistor; the first end of the path inductor is connected to the signal input end, the drain of the eighth transistor is connected to the second end of the path inductor, the gate of the eighth transistor is connected to the sixth control electrode voltage, and the source of the eighth transistor is grounded; the gate of the first transistor is connected to the drain of the eighth transistor.
更优的，所述衰减电路还包括第三电容，所述第三电容的第一端与所述第六晶体管的漏极连接，所述第三电容的第二端作为所述衰减电路的第二端与所述信号输出端连接。More preferably, the attenuation circuit further includes a third capacitor, a first end of the third capacitor is connected to the drain of the sixth transistor, and a second end of the third capacitor is connected to the signal output end as the second end of the attenuation circuit.
更优的，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管以及所述第八晶体管均为NMOS管。More preferably, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all NMOS transistors.
更优的，所述无源电路还包括第四电容，所述第四电容的第一端分别与所述第二晶体管的漏极以及所述供电电感的第二端连接，所述第四电容的第二端与所述信号输出端连接。More preferably, the passive circuit further includes a fourth capacitor, a first end of the fourth capacitor is respectively connected to the drain of the second transistor and the second end of the power supply inductor, and a second end of the fourth capacitor is connected to the signal output end.
更优的，所述无源电路还包括反馈电感，所述反馈电感的第一端与所述第一晶体管的源极连接，所述反馈电感的第二端接地。More preferably, the passive circuit further includes a feedback inductor, a first end of the feedback inductor is connected to the source of the first transistor, and a second end of the feedback inductor is grounded.
第二方面，本实用新型提供了一种射频接收模组，所述射频接收模组包括如上所述的射频接收模组旁路模式下的无源电路。 In a second aspect, the utility model provides a radio frequency receiving module, wherein the radio frequency receiving module includes the passive circuit in the bypass mode of the radio frequency receiving module as described above.
与现有技术相比，本实用新型的射频接收模组旁路模式下的无源电路通过在第一电容和信号输出端之间增设用于对信号输入端输入的信号进行衰减后输出的衰减电路，从而实现了对大功率信号进行衰减的功能，进而可以使大功率信号衰减成所需的功率信号以输出至下一级电路，即解决了现有低噪声放大器的下一级电路低功率需求和射频接收电路接收到过大功率信号之间存在的矛盾。Compared with the prior art, the passive circuit in the bypass mode of the RF receiving module of the utility model realizes the function of attenuating high-power signals by adding an attenuation circuit between the first capacitor and the signal output terminal for attenuating the signal input from the signal input terminal and then outputting it. The high-power signal can then be attenuated into the required power signal to be output to the next-stage circuit, thus solving the contradiction between the low-power requirement of the next-stage circuit of the existing low-noise amplifier and the excessively high-power signal received by the RF receiving circuit.
【附图说明】【Brief Description of the Drawings】
为了更清楚地说明本实用新型实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本实用新型的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图，其中：In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:
图1为本实用新型实施例提供的一种射频接收模组旁路模式下的无源电路的电路图。FIG1 is a circuit diagram of a passive circuit in a bypass mode of a radio frequency receiving module provided by an embodiment of the present utility model.
【具体实施方式】【Detailed ways】
下面将结合本实用新型实施例中的附图，对本实用新型实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本实用新型的一部分实施例，而不是全部的实施例。基于本实用新型中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本实用新型保护的范围。The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
本实用新型实施例提供了一种射频接收模组旁路模式下的无源电路100，结合图1所示，其包括信号输入端VIN、第一电容C1、衰减电路10、供电电感Ld、第一晶体管M1、第二晶体管M2以及信号输出端VOUT。An embodiment of the utility model provides a passive circuit 100 in a bypass mode of a radio frequency receiving module, as shown in FIG1 , comprising a signal input terminal VIN, a first capacitor C1, an attenuation circuit 10, a power supply inductor Ld, a first transistor M1, a second transistor M2 and a signal output terminal VOUT.
其中，射频接收模组旁路模式下的无源电路100以下简称无源电路。The passive circuit 100 in the bypass mode of the RF receiving module is hereinafter referred to as the passive circuit.
第一电容C1的第一端与信号输入端VIN连接，衰减电路10的第 一端与第一电容C1的第二端连接，衰减电路10的第二端与信号输出端VOUT连接。The first end of the first capacitor C1 is connected to the signal input terminal VIN. One end is connected to the second end of the first capacitor C1 , and the second end of the attenuation circuit 10 is connected to the signal output end VOUT.
供电电感Ld的第一端连接至电源电压VDD，供电电感Ld的第二端与信号输出端VOUT连接。A first end of the power supply inductor Ld is connected to the power supply voltage VDD, and a second end of the power supply inductor Ld is connected to the signal output terminal VOUT.
第一晶体管M1的栅极与信号输入端VIN连接，第一晶体管M1的源极接地。A gate of the first transistor M1 is connected to the signal input terminal VIN, and a source of the first transistor M1 is grounded.
第二晶体管M2的源极与第一晶体管M1的漏极连接，第二晶体管M2的栅极连接至供电电压Vb，第二晶体管M2的漏极分别连接至供电电感Ld的第二端及信号输出端VOUT。The source of the second transistor M2 is connected to the drain of the first transistor M1 , the gate of the second transistor M2 is connected to the power supply voltage Vb, and the drain of the second transistor M2 is respectively connected to the second end of the power supply inductor Ld and the signal output end VOUT.
无源电路100处于射频接收模组旁路模式时，信号输入端VIN接收的信号经过衰减电路10，并通过衰减电路10对信号输入端VIN输入的信号进行衰减后输出至信号输出端VOUT。When the passive circuit 100 is in the RF receiving module bypass mode, the signal received by the signal input terminal VIN passes through the attenuation circuit 10, and the attenuation circuit 10 attenuates the signal input to the signal input terminal VIN and outputs it to the signal output terminal VOUT.
具体地，衰减电路10包括第三晶体管S3、第一电阻R1、第四晶体管S4、第二电阻R2、第五晶体管S5、第三电阻R3、第六晶体管S6、第四电阻R4以及第五电阻R5。Specifically, the attenuation circuit 10 includes a third transistor S3, a first resistor R1, a fourth transistor S4, a second resistor R2, a fifth transistor S5, a third resistor R3, a sixth transistor S6, a fourth resistor R4 and a fifth resistor R5.
其中，第三晶体管S3的栅极连接至第一控制极电压VG3，第三晶体管S3的源极作为衰减电路10的第一端与第一电容C1的第二端连接，第一电阻R1的两端分别连接至第三晶体管S3的源极和第三晶体管S3漏极。Among them, the gate of the third transistor S3 is connected to the first control electrode voltage VG3, the source of the third transistor S3 is connected to the second end of the first capacitor C1 as the first end of the attenuation circuit 10, and the two ends of the first resistor R1 are respectively connected to the source of the third transistor S3 and the drain of the third transistor S3.
第四晶体管S4的栅极连接至第二控制极电压VG4，第四晶体管S4的源极与第三晶体管S3的漏极连接，第二电阻R2的两端分别连接至第四晶体管S4的源极和第四晶体管S4漏极。The gate of the fourth transistor S4 is connected to the second control electrode voltage VG4, the source of the fourth transistor S4 is connected to the drain of the third transistor S3, and both ends of the second resistor R2 are connected to the source of the fourth transistor S4 and the drain of the fourth transistor S4 respectively.
第五电阻R5的第一端与第四晶体管S4的漏极连接，第五电阻R5的第二端接地。A first end of the fifth resistor R5 is connected to the drain of the fourth transistor S4 , and a second end of the fifth resistor R5 is grounded.
第五晶体管S5的栅极连接至第三控制极电压VG5，第五晶体管S5的源极与第五电阻R5的第一端连接，第三电阻R3的两端分别连接至第五晶体管S5的源极和第五晶体管S5漏极。The gate of the fifth transistor S5 is connected to the third control electrode voltage VG5, the source of the fifth transistor S5 is connected to the first end of the fifth resistor R5, and the two ends of the third resistor R3 are respectively connected to the source of the fifth transistor S5 and the drain of the fifth transistor S5.
第六晶体管S6的栅极连接至第四控制极电压VG6，第六晶体管 S6的源极与第五晶体管S5的漏极连接，第四电阻R4的两端分别连接至第六晶体管S6的源极和第六晶体管S6漏极，第六晶体管S6的漏极作为衰减电路10的第二端与信号输出端VOUT连接。The gate of the sixth transistor S6 is connected to the fourth control electrode voltage VG6. The source of S6 is connected to the drain of the fifth transistor S5, the two ends of the fourth resistor R4 are respectively connected to the source of the sixth transistor S6 and the drain of the sixth transistor S6, and the drain of the sixth transistor S6 is connected to the signal output terminal VOUT as the second end of the attenuation circuit 10.
具体地，衰减电路10还包括第二电容C2以及第七晶体管S2。Specifically, the attenuation circuit 10 further includes a second capacitor C2 and a seventh transistor S2.
其中，第二电容C2的第一端与第五电阻R5的第一端连接，第七晶体管S2的漏极与第二电容C2的第二端连接，第七晶体管S2的栅极连接至第五控制极电压VG2，第七晶体管S2的源极接地。Among them, the first end of the second capacitor C2 is connected to the first end of the fifth resistor R5, the drain of the seventh transistor S2 is connected to the second end of the second capacitor C2, the gate of the seventh transistor S2 is connected to the fifth control electrode voltage VG2, and the source of the seventh transistor S2 is grounded.
第五晶体管S5的源极与第二电容C2的第一端连接，即第五晶体管S5的源极通过第二电容C2的第一端间接与第五电阻R5的第一端连接。The source of the fifth transistor S5 is connected to the first end of the second capacitor C2 , that is, the source of the fifth transistor S5 is indirectly connected to the first end of the fifth resistor R5 through the first end of the second capacitor C2 .
具体地，衰减电路10还包括通路电感L1以及第八晶体管S1。Specifically, the attenuation circuit 10 further includes a path inductor L1 and an eighth transistor S1 .
其中，通路电感L1的第一端与信号输入端VIN连接，第八晶体管S1的漏极与通路电感L1的第二端连接，第八晶体管S1的栅极连接至第六控制极电压VG1，第八晶体管S1的源极接地。The first end of the path inductor L1 is connected to the signal input end VIN, the drain of the eighth transistor S1 is connected to the second end of the path inductor L1, the gate of the eighth transistor S1 is connected to the sixth control electrode voltage VG1, and the source of the eighth transistor S1 is grounded.
第一晶体管M1的栅极与第八晶体管S1的漏极连接，即第一晶体管M1的栅极依次通过第八晶体管S1的漏极以及通路电感L1间接与信号输入端VIN连接。The gate of the first transistor M1 is connected to the drain of the eighth transistor S1 , that is, the gate of the first transistor M1 is indirectly connected to the signal input terminal VIN through the drain of the eighth transistor S1 and the path inductor L1 in sequence.
具体地，衰减电路10还包括第三电容C3，第三电容C3的第一端与第六晶体管S6的漏极连接；第三电容C3的第二端作为衰减电路10的第二端与信号输出端VOUT连接，即第六晶体管S6的漏极通过第三电容C3间接与信号输出端VOUT连接。Specifically, the attenuation circuit 10 also includes a third capacitor C3, a first end of the third capacitor C3 is connected to the drain of the sixth transistor S6; the second end of the third capacitor C3 is connected to the signal output terminal VOUT as the second end of the attenuation circuit 10, that is, the drain of the sixth transistor S6 is indirectly connected to the signal output terminal VOUT through the third capacitor C3.
具体地，无源电路100还包括第四电容C4，第四电容C4的第一端分别与第二晶体管M2的漏极以及供电电感Ld的第二端连接，第四电容C4的第二端与信号输出端VOUT连接，即第二晶体管M2的漏极以及供电电感Ld的第二端通过第四电容C4间接与信号输出端VOUT连接。Specifically, the passive circuit 100 also includes a fourth capacitor C4, a first end of the fourth capacitor C4 is respectively connected to the drain of the second transistor M2 and the second end of the power supply inductor Ld, and a second end of the fourth capacitor C4 is connected to the signal output terminal VOUT, that is, the drain of the second transistor M2 and the second end of the power supply inductor Ld are indirectly connected to the signal output terminal VOUT through the fourth capacitor C4.
具体地，无源电路100还包括反馈电感Ls，反馈电感Ls的第一端与第一晶体管M1的源极连接，反馈电感Ls的第二端接地，即第一 晶体管M1的源极通过反馈电感Ls间接接地。反馈电感Ls为第一晶体管M1的源极负反馈电感，该反馈电感Ls的作用在于增加输入阻抗的实部，可以更方便进行匹配，减小匹配的耗损，同时可以使最佳噪声源阻抗和共轭匹配阻抗更靠近，还可以获得较好的噪声系数和输入匹配。Specifically, the passive circuit 100 further includes a feedback inductor Ls, a first end of the feedback inductor Ls is connected to the source of the first transistor M1, and a second end of the feedback inductor Ls is grounded. The source of the transistor M1 is indirectly grounded through the feedback inductor Ls. The feedback inductor Ls is the source negative feedback inductor of the first transistor M1. The function of the feedback inductor Ls is to increase the real part of the input impedance, which can make matching more convenient and reduce the matching loss. At the same time, it can make the optimal noise source impedance and the conjugate matching impedance closer, and can also obtain a better noise factor and input matching.
本实施例中，第一晶体管M1、第二晶体管M2、第三晶体管S3、第四晶体管S4、第五晶体管S5、第六晶体管S6、第七晶体管S2以及第八晶体管S1均为NMOS管。In this embodiment, the first transistor M1 , the second transistor M2 , the third transistor S3 , the fourth transistor S4 , the fifth transistor S5 , the sixth transistor S6 , the seventh transistor S2 and the eighth transistor S1 are all NMOS transistors.
本实施例中，第一电容C1和供电电感Ld组成低噪声放大器的输出匹配电路，同时供电电感Ld还起到供电电感的作用，即低噪声放大器的漏极电感；第一晶体管M1和第二晶体管M2组成共源共栅结构的低噪声放大器，即为放大模式下进行信号放大的晶体管；反馈电感Ls为低噪声放大器的源极反馈电感；第四电容C4为放大模式下输出端的隔直电容；第一电容C1、第二电容C2和第三电容C3均为隔直电容，其中第三电容C3也有匹配的作用；第三晶体管S3至第八晶体管S1为MOS开关管，第一电阻R1至第五电阻R5为第三晶体管S3至第六晶体管S6的漏极和源极的并联电阻；第一控制极电压VG3至第六控制极电压VG1为MOS开关的控制电压。In this embodiment, the first capacitor C1 and the power supply inductor Ld form an output matching circuit of the low noise amplifier, and the power supply inductor Ld also plays the role of the power supply inductor, that is, the drain inductor of the low noise amplifier; the first transistor M1 and the second transistor M2 form a low noise amplifier with a common source and common gate structure, that is, a transistor for signal amplification in the amplification mode; the feedback inductor Ls is the source feedback inductor of the low noise amplifier; the fourth capacitor C4 is a DC blocking capacitor at the output end in the amplification mode; the first capacitor C1, the second capacitor C2 and the third capacitor C3 are all DC blocking capacitors, among which the third capacitor C3 also has a matching function; the third transistor S3 to the eighth transistor S1 are MOS switch tubes, the first resistor R1 to the fifth resistor R5 are parallel resistors of the drain and source of the third transistor S3 to the sixth transistor S6; the first control electrode voltage VG3 to the sixth control electrode voltage VG1 are control voltages of the MOS switch.
本实施例中，当需要工作在旁路模式时，第六控制极电压VG1控制第八晶体管S1开启，第五控制极电压VG2控制第七晶体管S2关断，第一控制极电压VG3至第四控制极电压VG6分别控制第三晶体管S3至第六晶体管S6的开启，以保证功率信号从旁路电路(旁路通路)进行衰减后输出。In this embodiment, when it is necessary to work in the bypass mode, the sixth control electrode voltage VG1 controls the eighth transistor S1 to turn on, the fifth control electrode voltage VG2 controls the seventh transistor S2 to turn off, and the first control electrode voltage VG3 to the fourth control electrode voltage VG6 respectively control the turning on of the third transistor S3 to the sixth transistor S6 to ensure that the power signal is attenuated from the bypass circuit (bypass path) before being output.
本实施例中，射频接收模组旁路模式下的无源电路100在旁路模式下，第一晶体管M1和第二晶体管M2不具备放大作用，信号输入端VIN输入的信号不再从第一晶体管M1和第二晶体管M2通过；旁路模式下，衰减电路10中的第三晶体管S3至第六晶体管S6开启，功率信号从旁路电路通过，即第三晶体管S3至第六晶体管S6开启时， 可以利用其开启的沟道电阻第一电阻R1至第四电阻R4与并联的第五电阻R5组成一个T型的衰减电路10(衰减网络)，同时第六控制极电压VG1控制第八晶体管S1开启，形成从旁路电路的信号输入端VIN经过通路电感L1到地的通路，从而改善在旁路模式下的输入匹配，减小输入反射，获取更好的第八晶体管S1。In this embodiment, in the bypass mode of the passive circuit 100 of the RF receiving module, the first transistor M1 and the second transistor M2 do not have an amplification effect, and the signal input at the signal input terminal VIN no longer passes through the first transistor M1 and the second transistor M2; in the bypass mode, the third transistor S3 to the sixth transistor S6 in the attenuation circuit 10 are turned on, and the power signal passes through the bypass circuit, that is, when the third transistor S3 to the sixth transistor S6 are turned on, The opened channel resistors, the first resistor R1 to the fourth resistor R4, and the fifth resistor R5 in parallel can be used to form a T-type attenuation circuit 10 (attenuation network). At the same time, the sixth control electrode voltage VG1 controls the eighth transistor S1 to turn on, forming a path from the signal input terminal VIN of the bypass circuit to the ground through the path inductor L1, thereby improving the input matching in the bypass mode, reducing input reflection, and obtaining a better eighth transistor S1.
本实施例中，在第三晶体管S3至第六晶体管S6开启的情况下，第五控制极电压VG2控制第七晶体管S2的关断，功率信号经过衰减电路10衰减后输出到信号输出端VOUT；当电路不工作在旁路模式下时，第一控制极电压VG3至第四控制极电压VG6分别控制第三晶体管S3至第六晶体管S6的关断，第一电阻R1至第四电阻R4可以使第三晶体管S3至第六晶体管S6的漏极和源极的电压保持一致，保证开关的关断；但此时，第三晶体管S3至第六晶体管S6会有寄生电容的存在，功率信号会从此通路泄露到输出端，导致电路的隔离度恶化，因此，需要第五控制极电压VG2控制第七晶体管S2的开启，以令泄露到旁路通路的功率信号通过第二电容C2下拉到地，改善电路的隔离度。In this embodiment, when the third transistor S3 to the sixth transistor S6 are turned on, the fifth control electrode voltage VG2 controls the turn-off of the seventh transistor S2, and the power signal is attenuated by the attenuation circuit 10 and then output to the signal output terminal VOUT; when the circuit is not operating in the bypass mode, the first control electrode voltage VG3 to the fourth control electrode voltage VG6 respectively control the turn-off of the third transistor S3 to the sixth transistor S6, and the first resistor R1 to the fourth resistor R4 can make the drain and source voltages of the third transistor S3 to the sixth transistor S6 consistent, thereby ensuring the turn-off of the switch; but at this time, the third transistor S3 to the sixth transistor S6 will have parasitic capacitance, and the power signal will leak from this path to the output end, resulting in the deterioration of the isolation of the circuit. Therefore, the fifth control electrode voltage VG2 is required to control the turn-on of the seventh transistor S2, so that the power signal leaked to the bypass path is pulled down to the ground through the second capacitor C2, thereby improving the isolation of the circuit.
本实施例中所描述的“连接”均为电连接或电性连接，即连接的两个器件或多个器件均为电连接或电性连接。The “connections” described in this embodiment are all electrical connections or electrical connections, that is, the two or more connected devices are all electrically connected or electrically connected.
与现有技术相比，本实施例的射频接收模组旁路模式下的无源电路100通过在第一电容C1和信号输出端VOUT之间增设用于对信号输入端VIN输入的信号进行衰减后输出的衰减电路10，从而实现了对大功率信号进行衰减的功能，进而可以使大功率信号衰减成所需的功率信号以输出至下一级电路，即解决了现有低噪声放大器的下一级电路低功率需求和射频接收电路接收到过大功率信号之间存在的矛盾。Compared with the prior art, the passive circuit 100 in the bypass mode of the RF receiving module of the present embodiment realizes the function of attenuating high-power signals by adding an attenuation circuit 10 between the first capacitor C1 and the signal output terminal VOUT for attenuating the signal input at the signal input terminal VIN and then outputting it. The high-power signal can then be attenuated into the required power signal to be output to the next-stage circuit, thus solving the contradiction between the low-power requirement of the next-stage circuit of the existing low-noise amplifier and the excessively high-power signal received by the RF receiving circuit.
本实用新型还提供了另一实施例，一种射频接收模组，所述射频接收模组包括如上述实施例中的射频接收模组旁路模式下的无源电路100。The present invention also provides another embodiment, a radio frequency receiving module, wherein the radio frequency receiving module includes the passive circuit 100 in the bypass mode of the radio frequency receiving module in the above embodiment.
由于本实施例中的射频接收模组包括了上述实施例中的射频接收 模组旁路模式下的无源电路100，因此其也能达到上述实施例中射频接收模组旁路模式下的无源电路100所达到的技术效果，在此不作赘述。Since the RF receiving module in this embodiment includes the RF receiving module in the above embodiment The passive circuit 100 in the module bypass mode can also achieve the technical effect achieved by the passive circuit 100 in the RF receiving module bypass mode in the above embodiment, which will not be elaborated here.
以上所述的仅是本实用新型的实施方式，在此应当指出，对于本领域的普通技术人员来说，在不脱离本实用新型创造构思的前提下，还可以做出改进，但这些均属于本实用新型的保护范围。 The above is only an implementation method of the present invention. It should be pointed out that a person skilled in the art can make improvements without departing from the inventive concept of the present invention, but these improvements are within the protection scope of the present invention.

Claims (9)

  1. 一种射频接收模组旁路模式下的无源电路，其特征在于，包括信号输入端、第一电容、衰减电路、供电电感、第一晶体管、第二晶体管以及信号输出端；A passive circuit in a bypass mode of a radio frequency receiving module, characterized in that it comprises a signal input terminal, a first capacitor, an attenuation circuit, a power supply inductor, a first transistor, a second transistor and a signal output terminal;
    所述第一电容的第一端与所述信号输入端连接，所述衰减电路的第一端与所述第一电容的第二端连接，所述衰减电路的第二端与所述信号输出端连接；The first end of the first capacitor is connected to the signal input end, the first end of the attenuation circuit is connected to the second end of the first capacitor, and the second end of the attenuation circuit is connected to the signal output end;
    所述供电电感的第一端连接至电源电压，所述供电电感的第二端与所述信号输出端连接；A first end of the power supply inductor is connected to a power supply voltage, and a second end of the power supply inductor is connected to the signal output end;
    所述第一晶体管的栅极与所述信号输入端连接，所述第一晶体管的源极接地；The gate of the first transistor is connected to the signal input terminal, and the source of the first transistor is grounded;
    所述第二晶体管的源极与所述第一晶体管的漏极连接，所述第二晶体管的栅极连接至供电电压，所述第二晶体管的漏极分别连接至所述供电电感的第二端及所述信号输出端；The source of the second transistor is connected to the drain of the first transistor, the gate of the second transistor is connected to the power supply voltage, and the drain of the second transistor is respectively connected to the second end of the power supply inductor and the signal output end;
    所述无源电路处于所述射频接收模组旁路模式时，所述信号输入端接收的信号经过所述衰减电路，并通过所述衰减电路对所述信号输入端输入的信号进行衰减后输出至所述信号输出端。When the passive circuit is in the bypass mode of the RF receiving module, the signal received by the signal input end passes through the attenuation circuit, and the signal input by the signal input end is attenuated by the attenuation circuit and then output to the signal output end.
  2. 如权利要求1所述的射频接收模组旁路模式下的无源电路，其特征在于，所述衰减电路包括第三晶体管、第一电阻、第四晶体管、第二电阻、第五晶体管、第三电阻、第六晶体管、第四电阻以及第五电阻；The passive circuit in the bypass mode of the RF receiving module according to claim 1, characterized in that the attenuation circuit includes a third transistor, a first resistor, a fourth transistor, a second resistor, a fifth transistor, a third resistor, a sixth transistor, a fourth resistor and a fifth resistor;
    所述第三晶体管的栅极连接至第一控制极电压，所述第三晶体管的源极作为所述衰减电路的第一端与所述第一电容的第二端连接，所述第一电阻的两端分别连接至所述第三晶体管的源极和所述第三晶体管的漏极；The gate of the third transistor is connected to the first control electrode voltage, the source of the third transistor is connected to the second end of the first capacitor as the first end of the attenuation circuit, and the two ends of the first resistor are respectively connected to the source of the third transistor and the drain of the third transistor;
    所述第四晶体管的栅极连接至第二控制极电压，所述第四晶体管的源极与所述第三晶体管的漏极连接，所述第二电阻的两端分别连接所述第四晶体管的源极和所述第四晶体管的漏极； The gate of the fourth transistor is connected to the second control electrode voltage, the source of the fourth transistor is connected to the drain of the third transistor, and the two ends of the second resistor are respectively connected to the source of the fourth transistor and the drain of the fourth transistor;
    所述第五电阻的第一端与所述第四晶体管的漏极连接，所述第五电阻的第二端接地；A first end of the fifth resistor is connected to the drain of the fourth transistor, and a second end of the fifth resistor is grounded;
    所述第五晶体管的栅极连接至第三控制极电压，所述第五晶体管的源极与所述第五电阻的第一端连接，所述第三电阻的两端分别连接所述第五晶体管的源极和所述第五晶体管的漏极；The gate of the fifth transistor is connected to the third control electrode voltage, the source of the fifth transistor is connected to the first end of the fifth resistor, and the two ends of the third resistor are connected to the source of the fifth transistor and the drain of the fifth transistor respectively;
    所述第六晶体管的栅极连接至第四控制极电压，所述第六晶体管的源极与所述第五晶体管的漏极连接，所述第四电阻的两端分别连接所述第六晶体管的源极和所述第六晶体管的漏极，所述第六晶体管的漏极作为所述衰减电路的第二端与所述信号输出端连接。The gate of the sixth transistor is connected to the fourth control electrode voltage, the source of the sixth transistor is connected to the drain of the fifth transistor, the two ends of the fourth resistor are respectively connected to the source of the sixth transistor and the drain of the sixth transistor, and the drain of the sixth transistor is connected to the signal output end as the second end of the attenuation circuit.
  3. 如权利要求2所述的射频接收模组旁路模式下的无源电路，其特征在于，所述衰减电路还包括第二电容以及第七晶体管；所述第二电容的第一端与所述第五电阻的第一端连接，所述第七晶体管的漏极与所述第二电容的第二端连接，所述第七晶体管的栅极连接至第五控制极电压，所述第七晶体管的源极接地。The passive circuit in the bypass mode of the RF receiving module as described in claim 2 is characterized in that the attenuation circuit also includes a second capacitor and a seventh transistor; the first end of the second capacitor is connected to the first end of the fifth resistor, the drain of the seventh transistor is connected to the second end of the second capacitor, the gate of the seventh transistor is connected to the fifth control electrode voltage, and the source of the seventh transistor is grounded.
  4. 如权利要求3所述的射频接收模组旁路模式下的无源电路，其特征在于，所述衰减电路还包括通路电感以及第八晶体管；所述通路电感的第一端与所述信号输入端连接，所述第八晶体管的漏极与所述通路电感的第二端连接，所述第八晶体管的栅极连接至第六控制极电压，所述第八晶体管的源极接地；所述第一晶体管的栅极与所述第八晶体管的漏极连接。The passive circuit in the bypass mode of the RF receiving module as described in claim 3 is characterized in that the attenuation circuit also includes a path inductor and an eighth transistor; the first end of the path inductor is connected to the signal input end, the drain of the eighth transistor is connected to the second end of the path inductor, the gate of the eighth transistor is connected to the sixth control electrode voltage, and the source of the eighth transistor is grounded; the gate of the first transistor is connected to the drain of the eighth transistor.
  5. 如权利要求4所述的射频接收模组旁路模式下的无源电路，其特征在于，所述衰减电路还包括第三电容，所述第三电容的第一端与所述第六晶体管的漏极连接，所述第三电容的第二端作为所述衰减电路的第二端与所述信号输出端连接。The passive circuit in the bypass mode of the RF receiving module as described in claim 4 is characterized in that the attenuation circuit also includes a third capacitor, a first end of the third capacitor is connected to the drain of the sixth transistor, and a second end of the third capacitor is connected to the signal output end as the second end of the attenuation circuit.
  6. 如权利要求4所述的射频接收模组旁路模式下的无源电路，其特征在于，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管以及所述第八晶体管均为NMOS管。 The passive circuit in the bypass mode of the RF receiving module as described in claim 4 is characterized in that the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all NMOS transistors.
  7. 如权利要求1所述的射频接收模组旁路模式下的无源电路，其特征在于，所述无源电路还包括第四电容，所述第四电容的第一端分别与所述第二晶体管的漏极以及所述供电电感的第二端连接，所述第四电容的第二端与所述信号输出端连接。The passive circuit in the bypass mode of the RF receiving module as described in claim 1 is characterized in that the passive circuit also includes a fourth capacitor, a first end of the fourth capacitor is respectively connected to the drain of the second transistor and the second end of the power supply inductor, and a second end of the fourth capacitor is connected to the signal output end.
  8. 如权利要求1所述的射频接收模组旁路模式下的无源电路，其特征在于，所述无源电路还包括反馈电感，所述反馈电感的第一端与所述第一晶体管的源极连接，所述反馈电感的第二端接地。The passive circuit in the bypass mode of the RF receiving module as described in claim 1 is characterized in that the passive circuit also includes a feedback inductor, a first end of the feedback inductor is connected to the source of the first transistor, and a second end of the feedback inductor is grounded.
  9. 一种射频接收模组，其特征在于，所述射频接收模组包括权利要求1-8任意一项所述的射频接收模组旁路模式下的无源电路。 A radio frequency receiving module, characterized in that the radio frequency receiving module comprises the passive circuit in the radio frequency receiving module bypass mode as described in any one of claims 1-8.
PCT/CN2023/125978 2022-11-07 2023-10-23 Passive circuit in bypass mode of radio frequency receiving module, and radio frequency receiving module WO2024099059A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202222963335.6U CN218633923U (en) 2022-11-07 2022-11-07 Passive circuit under radio frequency receiving module bypass mode and radio frequency receiving module
CN202222963335.6 2022-11-07

Publications (1)

Publication Number Publication Date
WO2024099059A1 true WO2024099059A1 (en) 2024-05-16

Family

ID=85422310

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/125978 WO2024099059A1 (en) 2022-11-07 2023-10-23 Passive circuit in bypass mode of radio frequency receiving module, and radio frequency receiving module

Country Status (2)

Country Link
CN (1) CN218633923U (en)
WO (1) WO2024099059A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN218633923U (en) * 2022-11-07 2023-03-14 深圳飞骧科技股份有限公司 Passive circuit under radio frequency receiving module bypass mode and radio frequency receiving module

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100301942A1 (en) * 2009-05-28 2010-12-02 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Amplifier with bypass switch
CN106992795A (en) * 2015-09-08 2017-07-28 联发科技股份有限公司 Radio frequency receiver
US20210265965A1 (en) * 2020-02-25 2021-08-26 Smarter Microelectronics (Guang Zhou) Co., Ltd. Radio frequency power amplifier circuit and gain control method
US20220247364A1 (en) * 2021-01-29 2022-08-04 Skyworks Solutions, Inc. Multi-mode broadband low noise amplifier
CN218633923U (en) * 2022-11-07 2023-03-14 深圳飞骧科技股份有限公司 Passive circuit under radio frequency receiving module bypass mode and radio frequency receiving module

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100301942A1 (en) * 2009-05-28 2010-12-02 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Amplifier with bypass switch
CN106992795A (en) * 2015-09-08 2017-07-28 联发科技股份有限公司 Radio frequency receiver
US20210265965A1 (en) * 2020-02-25 2021-08-26 Smarter Microelectronics (Guang Zhou) Co., Ltd. Radio frequency power amplifier circuit and gain control method
US20220247364A1 (en) * 2021-01-29 2022-08-04 Skyworks Solutions, Inc. Multi-mode broadband low noise amplifier
CN218633923U (en) * 2022-11-07 2023-03-14 深圳飞骧科技股份有限公司 Passive circuit under radio frequency receiving module bypass mode and radio frequency receiving module

Also Published As

Publication number Publication date
CN218633923U (en) 2023-03-14

Similar Documents

Publication Publication Date Title
CN107332517B (en) High-linearity broadband stacked low-noise amplifier based on gain compensation technology
WO2016155614A1 (en) Cascode radio frequency power amplifier having improved efficiency
US7560994B1 (en) Systems and methods for cascode switching power amplifiers
CN100481714C (en) Amplifier circuit having improved linearity and frequency band using a MGTR
US20060097786A1 (en) Low noise and high gain low noise amplifier
US9935585B2 (en) RF amplifier operational in different power modes
CN108574464B (en) Low-power-consumption high-linearity dual-mode millimeter wave broadband stacked low-noise amplifier
CN104617905B (en) Radio frequency amplifier and radio frequency amplification method
WO2024099059A1 (en) Passive circuit in bypass mode of radio frequency receiving module, and radio frequency receiving module
CN107592081A (en) A kind of ultra wide band monolithic microwave integrated low-noise amplifier
CN103095224A (en) Complementary metal-oxide-semiconductor transistor (CMOS) broadband low-noise amplifier adopting noise cancellation technology
WO2024066713A1 (en) Multi-band gain-adjustable low noise amplifier
CN111600556A (en) Low noise amplifier and radio frequency receiver
CN110868165B (en) Multi-adaptability switchable on-chip low-noise amplifier and working method thereof
WO2024099060A1 (en) Passive circuit in radio frequency receiving module bypass mode, and radio frequency receiving module
CN116248052A (en) Low noise amplifier and radio frequency chip
CN109194291A (en) A kind of one chip low-noise amplifier of the high-gain High Linear with bypass functionality
CN111478671A (en) Novel low-noise amplifier applied to Sub-GHz frequency band
KR20120125811A (en) Power amplifier
CN117639683A (en) Balun-based high-OIP 2 balance amplifier
KR101590605B1 (en) Linear power amplifier for wireless transmitter
CN116032219A (en) High-linearity low-noise amplifier, chip and electronic equipment
CN109327194A (en) A kind of one chip low-noise amplifier of the broadband High Linear with bypass functionality
US7944308B2 (en) Amplifier circuit and the controlling method thereof
CN107528555B (en) Distributed amplifier