CN218633923U - Passive circuit under radio frequency receiving module bypass mode and radio frequency receiving module - Google Patents
Passive circuit under radio frequency receiving module bypass mode and radio frequency receiving module Download PDFInfo
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- CN218633923U CN218633923U CN202222963335.6U CN202222963335U CN218633923U CN 218633923 U CN218633923 U CN 218633923U CN 202222963335 U CN202222963335 U CN 202222963335U CN 218633923 U CN218633923 U CN 218633923U
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Abstract
The utility model provides a passive circuit and radio frequency receiving module under radio frequency receiving module bypass mode, wherein, passive circuit under radio frequency receiving module bypass mode includes signal input part, first electric capacity, decay circuit, power supply inductance, first transistor, second transistor and signal output part. The utility model discloses a passive circuit under radio frequency receiving module bypass mode has realized carrying out the function of decay to high-power signal, and then can make high-power signal decay become required power signal in order exporting to next stage circuit, has solved the contradiction that exists between current low noise amplifier's next stage circuit low power demand and radio frequency receiving circuit received the too big power signal promptly.
Description
[ technical field ] A method for producing a semiconductor device
The utility model relates to a signal processing technology field especially relates to a passive circuit and radio frequency receiving module under radio frequency receiving module bypass mode.
[ background of the invention ]
The rf receiving circuit (rf receiving module) is an intermediate circuit for receiving and amplifying signals and outputting the amplified signals to a next stage circuit.
When an existing radio frequency receiving circuit receives a power signal, the possibility of receiving a high-power signal exists, and the signal does not need to be amplified but the power signal needs to be attenuated, so that the high-power signal is attenuated into a required power signal to be output to a next-stage circuit.
However, the existing radio frequency receiving circuit only has a power amplifier for amplifying signals, and does not have a related circuit for attenuating high-power signals, that is, the existing radio frequency receiving circuit cannot attenuate high-power signals, and accordingly, a contradiction exists between the low power requirement of a next-stage circuit of the existing low noise amplifier and the receiving of the radio frequency receiving circuit for receiving the over-power signals.
Therefore, it is necessary to provide a passive circuit in the bypass mode of the rf receiving module to solve the above problems.
[ Utility model ] content
An object of the utility model is to provide a passive circuit under radio frequency receiving module bypass mode to there is the problem of contradiction between the next stage circuit low power demand and the radio frequency receiving circuit of solving current low noise amplifier received the too big power signal.
In a first aspect, the present invention provides a passive circuit in a bypass mode of a radio frequency receiving module, which includes a signal input terminal, a first capacitor, an attenuation circuit, a power supply inductor, a first transistor, a second transistor, and a signal output terminal;
the first end of the first capacitor is connected with the signal input end, the first end of the attenuation circuit is connected with the second end of the first capacitor, and the second end of the attenuation circuit is connected with the signal output end;
the first end of the power supply inductor is connected to a power supply voltage, and the second end of the power supply inductor is connected with the signal output end;
the grid electrode of the first transistor is connected with the signal input end, and the source electrode of the first transistor is grounded;
the source electrode of the second transistor is connected with the drain electrode of the first transistor, the grid electrode of the second transistor is connected with a power supply voltage, and the drain electrode of the second transistor is respectively connected with the second end of the power supply inductor and the signal output end;
when the passive circuit is in the bypass mode of the radio frequency receiving module, the signal received by the signal input end passes through the attenuation circuit, and is output to the signal output end after the signal input by the signal input end is attenuated by the attenuation circuit.
Preferably, the attenuation circuit comprises a third transistor, a first resistor, a fourth transistor, a second resistor, a fifth transistor, a third resistor, a sixth transistor, a fourth resistor and a fifth resistor;
the grid electrode of the third transistor is connected to a first control electrode voltage, the source electrode of the third transistor is used as a first end of the attenuation circuit and is connected with a second end of the first capacitor, and two ends of the first resistor are respectively connected to the source electrode of the third transistor and the drain electrode of the third transistor;
the grid electrode of the fourth transistor is connected to a second control electrode voltage, the source electrode of the fourth transistor is connected with the drain electrode of the third transistor, and two ends of the second resistor are respectively connected with the source electrode of the fourth transistor and the drain electrode of the fourth transistor;
a first end of the fifth resistor is connected with a drain electrode of the fourth transistor, and a second end of the fifth resistor is grounded;
a gate of the fifth transistor is connected to a third control voltage, a source of the fifth transistor is connected to a first end of the fifth resistor, and two ends of the third resistor are respectively connected to the source of the fifth transistor and the drain of the fifth transistor;
the grid electrode of the sixth transistor is connected to a fourth control electrode voltage, the source electrode of the sixth transistor is connected with the drain electrode of the fifth transistor, two ends of the fourth resistor are respectively connected with the source electrode of the sixth transistor and the drain electrode of the sixth transistor, and the drain electrode of the sixth transistor serves as the second end of the attenuation circuit and is connected with the signal output end.
Preferably, the attenuation circuit further comprises a second capacitor and a seventh transistor; the first end of the second capacitor is connected with the first end of the fifth resistor, the drain of the seventh transistor is connected with the second end of the second capacitor, the gate of the seventh transistor is connected to a fifth control voltage, and the source of the seventh transistor is grounded.
Preferably, the attenuation circuit further comprises a path inductor and an eighth transistor; a first end of the path inductor is connected with the signal input end, a drain of the eighth transistor is connected with a second end of the path inductor, a gate of the eighth transistor is connected to a sixth control voltage, and a source of the eighth transistor is grounded; the gate of the first transistor is connected to the drain of the eighth transistor.
Preferably, the attenuation circuit further comprises a third capacitor, a first end of the third capacitor is connected with the drain of the sixth transistor, and a second end of the third capacitor is used as a second end of the attenuation circuit and connected with the signal output end.
Preferably, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all NMOS transistors.
Preferably, the passive circuit further includes a fourth capacitor, a first end of the fourth capacitor is connected to the drain of the second transistor and the second end of the power supply inductor, respectively, and a second end of the fourth capacitor is connected to the signal output terminal.
Preferably, the passive circuit further comprises a feedback inductor, a first end of the feedback inductor is connected with the source electrode of the first transistor, and a second end of the feedback inductor is grounded.
In a second aspect, the present invention provides a radio frequency receiving module, which includes the passive circuit in the bypass mode of the radio frequency receiving module.
Compared with the prior art, the utility model discloses a passive circuit under radio frequency receiving module bypass mode is used for attenuating the decay circuit of back output through addding between first electric capacity and signal output part to the signal of signal input part input, thereby realized carrying out the function of decay to high-power signal, and then can make high-power signal decay become required power signal in order to export to next stage circuit, solved the contradiction that exists between current low noise amplifier's next stage circuit low power demand and radio frequency receiving circuit received the too big power signal promptly.
[ description of the drawings ]
In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
fig. 1 is a circuit diagram of a passive circuit in a bypass mode of a radio frequency receiving module according to an embodiment of the present invention.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
The embodiment of the utility model provides a passive circuit 100 under radio frequency receiving module bypass mode combines fig. 1 to show, and it includes signal input part VIN, first electric capacity C1, decay circuit 10, power supply inductance Ld, first transistor M1, second transistor M2 and signal output part VOUT.
The passive circuit 100 in the rf receiving module bypass mode is hereinafter referred to as a passive circuit.
A first end of the first capacitor C1 is connected to the signal input terminal VIN, a first end of the attenuator circuit 10 is connected to a second end of the first capacitor C1, and a second end of the attenuator circuit 10 is connected to the signal output terminal VOUT.
The first end of the power supply inductor Ld is connected to the power supply voltage VDD, and the second end of the power supply inductor Ld is connected to the signal output terminal VOUT.
The gate of the first transistor M1 is connected to the signal input terminal VIN, and the source of the first transistor M1 is grounded.
The source of the second transistor M2 is connected to the drain of the first transistor M1, the gate of the second transistor M2 is connected to the supply voltage Vb, and the drain of the second transistor M2 is connected to the second end of the supply inductor Ld and the signal output terminal VOUT, respectively.
When the passive circuit 100 is in the rf receiving module bypass mode, the signal received by the signal input terminal VIN passes through the attenuation circuit 10, and is attenuated by the attenuation circuit 10 and then output to the signal output terminal VOUT.
Specifically, the attenuation circuit 10 includes a third transistor S3, a first resistor R1, a fourth transistor S4, a second resistor R2, a fifth transistor S5, a third resistor R3, a sixth transistor S6, a fourth resistor R4, and a fifth resistor R5.
The gate of the third transistor S3 is connected to the first control voltage VG3, the source of the third transistor S3 is used as the first end of the attenuation circuit 10 and is connected to the second end of the first capacitor C1, and two ends of the first resistor R1 are respectively connected to the source of the third transistor S3 and the drain of the third transistor S3.
The gate of the fourth transistor S4 is connected to the second controller voltage VG4, the source of the fourth transistor S4 is connected to the drain of the third transistor S3, and two ends of the second resistor R2 are respectively connected to the source of the fourth transistor S4 and the drain of the fourth transistor S4.
A first terminal of the fifth resistor R5 is connected to the drain of the fourth transistor S4, and a second terminal of the fifth resistor R5 is grounded.
The gate of the fifth transistor S5 is connected to the third control voltage VG5, the source of the fifth transistor S5 is connected to the first end of the fifth resistor R5, and two ends of the third resistor R3 are respectively connected to the source of the fifth transistor S5 and the drain of the fifth transistor S5.
The gate of the sixth transistor S6 is connected to the fourth controller voltage VG6, the source of the sixth transistor S6 is connected to the drain of the fifth transistor S5, two ends of the fourth resistor R4 are respectively connected to the source of the sixth transistor S6 and the drain of the sixth transistor S6, and the drain of the sixth transistor S6 is connected to the signal output terminal VOUT as the second end of the attenuator circuit 10.
Specifically, the attenuation circuit 10 further includes a second capacitor C2 and a seventh transistor S2.
A first end of the second capacitor C2 is connected to a first end of the fifth resistor R5, a drain of the seventh transistor S2 is connected to a second end of the second capacitor C2, a gate of the seventh transistor S2 is connected to the fifth controller voltage VG2, and a source of the seventh transistor S2 is grounded.
The source of the fifth transistor S5 is connected to the first end of the second capacitor C2, i.e. the source of the fifth transistor S5 is indirectly connected to the first end of the fifth resistor R5 through the first end of the second capacitor C2.
Specifically, the attenuation circuit 10 further includes a pass inductor L1 and an eighth transistor S1.
A first end of the path inductor L1 is connected to the signal input terminal VIN, a drain of the eighth transistor S1 is connected to a second end of the path inductor L1, a gate of the eighth transistor S1 is connected to the sixth control voltage VG1, and a source of the eighth transistor S1 is grounded.
The gate of the first transistor M1 is connected to the drain of the eighth transistor S1, that is, the gate of the first transistor M1 is indirectly connected to the signal input end VIN through the drain of the eighth transistor S1 and the pass inductor L1 in sequence.
Specifically, the attenuation circuit 10 further includes a third capacitor C3, and a first end of the third capacitor C3 is connected to the drain of the sixth transistor S6; a second terminal of the third capacitor C3 is connected to the signal output terminal VOUT as a second terminal of the attenuator circuit 10, i.e., the drain of the sixth transistor S6 is indirectly connected to the signal output terminal VOUT through the third capacitor C3.
Specifically, the passive circuit 100 further includes a fourth capacitor C4, a first end of the fourth capacitor C4 is respectively connected to the drain of the second transistor M2 and the second end of the power supply inductor Ld, and a second end of the fourth capacitor C4 is connected to the signal output terminal VOUT, that is, the drain of the second transistor M2 and the second end of the power supply inductor Ld are indirectly connected to the signal output terminal VOUT through the fourth capacitor C4.
Specifically, the passive circuit 100 further includes a feedback inductor Ls, a first end of the feedback inductor Ls is connected to the source of the first transistor M1, and a second end of the feedback inductor Ls is grounded, that is, the source of the first transistor M1 is indirectly grounded through the feedback inductor Ls. The feedback inductor Ls is a source degeneration inductor of the first transistor M1, and the feedback inductor Ls is used for increasing the real part of the input impedance, so that matching can be performed more conveniently, matching loss can be reduced, the optimal noise source impedance and the conjugate matching impedance can be closer, and a better noise coefficient and input matching can be obtained.
In this embodiment, the first transistor M1, the second transistor M2, the third transistor S3, the fourth transistor S4, the fifth transistor S5, the sixth transistor S6, the seventh transistor S2, and the eighth transistor S1 are all NMOS transistors.
In this embodiment, the first capacitor C1 and the power supply inductor Ld form an output matching circuit of the low noise amplifier, and the power supply inductor Ld also functions as a power supply inductor, that is, a drain inductor of the low noise amplifier; the first transistor M1 and the second transistor M2 form a low noise amplifier of a cascode structure, that is, a transistor for amplifying a signal in an amplification mode; the feedback inductor Ls is a source electrode feedback inductor of the low noise amplifier; the fourth capacitor C4 is a blocking capacitor at the output end in the amplification mode; the first capacitor C1, the second capacitor C2 and the third capacitor C3 are all blocking capacitors, wherein the third capacitor C3 also has a matching function; the third transistor S3 to the eighth transistor S1 are MOS switch transistors, and the first resistor R1 to the fifth resistor R5 are parallel resistors of the drain and the source of the third transistor S3 to the sixth transistor S6; the first to sixth control voltages VG3 to VG1 are control voltages of the MOS switches.
In this embodiment, when the power needs to operate in the bypass mode, the sixth control electrode voltage VG1 controls the eighth transistor S1 to be turned on, the fifth control electrode voltage VG2 controls the seventh transistor S2 to be turned off, and the first to fourth control electrode voltages VG3 to VG6 respectively control the third to sixth transistors S3 to S6 to be turned on, so as to ensure that the power signal is attenuated and then output from the bypass circuit (bypass path).
In this embodiment, in the bypass mode of the passive circuit 100 of the radio frequency receiving module, the first transistor M1 and the second transistor M2 do not have an amplification effect, and a signal input by the signal input end VIN does not pass through the first transistor M1 and the second transistor M2 any more; in the bypass mode, the third transistor S3 to the sixth transistor S6 in the attenuator circuit 10 are turned on, the power signal passes through the bypass circuit, that is, when the third transistor S3 to the sixth transistor S6 are turned on, the T-type attenuator circuit 10 (attenuator network) can be formed by the turned-on channel resistors R1 to R4 and the parallel fifth resistor R5, and the sixth control voltage VG1 controls the turn-on of the eighth transistor S1 to form a path from the signal input terminal VIN of the bypass circuit to the ground through the path inductor L1, so as to improve the input matching in the bypass mode, reduce the input reflection, and obtain the better eighth transistor S1.
In this embodiment, when the third transistor S3 to the sixth transistor S6 are turned on, the fifth control voltage VG2 controls the seventh transistor S2 to be turned off, and the power signal is attenuated by the attenuation circuit 10 and then output to the signal output terminal VOUT; when the circuit does not work in a bypass mode, the first control electrode voltage VG3 to the fourth control electrode voltage VG6 respectively control the turn-off of the third transistor S3 to the sixth transistor S6, and the first resistor R1 to the fourth resistor R4 can keep the voltages of the drain and the source of the third transistor S3 to the sixth transistor S6 consistent, so as to ensure the turn-off of the switch; however, at this time, the third transistor S3 to the sixth transistor S6 have parasitic capacitances, and the power signal leaks to the output terminal from this path, which deteriorates the isolation of the circuit, so the fifth control voltage VG2 is needed to control the seventh transistor S2 to be turned on, so that the power signal leaking to the bypass path is pulled down to the ground through the second capacitor C2, thereby improving the isolation of the circuit.
The term "connected" as used in this embodiment is electrically connected or connected, i.e., two or more devices are electrically connected or connected.
Compared with the prior art, the passive circuit 100 in the bypass mode of the radio frequency receiving module according to the embodiment is additionally provided with the attenuation circuit 10 for attenuating the signal input by the signal input terminal VIN and outputting the attenuated signal between the first capacitor C1 and the signal output terminal VOUT, so that the function of attenuating a high-power signal is realized, the high-power signal can be attenuated into a required power signal to be output to a next-stage circuit, and the contradiction between the low-power requirement of the next-stage circuit of the existing low-noise amplifier and the fact that the radio frequency receiving circuit receives an excessively large power signal is solved.
The utility model also provides another embodiment, a radio frequency receiving module, the radio frequency receiving module includes passive circuit 100 under the radio frequency receiving module bypass mode as in the above-mentioned embodiment.
Since the rf receiving module in this embodiment includes the passive circuit 100 in the rf receiving module bypass mode in the above embodiment, the rf receiving module can also achieve the technical effect achieved by the passive circuit 100 in the rf receiving module bypass mode in the above embodiment, which is not described herein again.
The above embodiments of the present invention are only described, and it should be noted that, for those skilled in the art, modifications can be made without departing from the inventive concept, but these all fall into the protection scope of the present invention.
Claims (9)
1. A passive circuit in a bypass mode of a radio frequency receiving module is characterized by comprising a signal input end, a first capacitor, an attenuation circuit, a power supply inductor, a first transistor, a second transistor and a signal output end;
the first end of the first capacitor is connected with the signal input end, the first end of the attenuation circuit is connected with the second end of the first capacitor, and the second end of the attenuation circuit is connected with the signal output end;
the first end of the power supply inductor is connected to a power supply voltage, and the second end of the power supply inductor is connected with the signal output end;
the grid electrode of the first transistor is connected with the signal input end, and the source electrode of the first transistor is grounded;
the source of the second transistor is connected with the drain of the first transistor, the gate of the second transistor is connected to a supply voltage, and the drains of the second transistor are respectively connected to the second end of the supply inductor and the signal output end;
when the passive circuit is in the bypass mode of the radio frequency receiving module, the signal received by the signal input end passes through the attenuation circuit, and is output to the signal output end after the signal input by the signal input end is attenuated by the attenuation circuit.
2. The passive circuit in the bypass mode of the rf receiving module of claim 1, wherein the attenuation circuit comprises a third transistor, a first resistor, a fourth transistor, a second resistor, a fifth transistor, a third resistor, a sixth transistor, a fourth resistor, and a fifth resistor;
the grid electrode of the third transistor is connected to a first control electrode voltage, the source electrode of the third transistor is used as a first end of the attenuation circuit and is connected with a second end of the first capacitor, and two ends of the first resistor are respectively connected to the source electrode of the third transistor and the drain electrode of the third transistor;
the grid electrode of the fourth transistor is connected to a second control electrode voltage, the source electrode of the fourth transistor is connected with the drain electrode of the third transistor, and two ends of the second resistor are respectively connected with the source electrode of the fourth transistor and the drain electrode of the fourth transistor;
a first end of the fifth resistor is connected with a drain electrode of the fourth transistor, and a second end of the fifth resistor is grounded;
a gate of the fifth transistor is connected to a third control electrode voltage, a source of the fifth transistor is connected with a first end of the fifth resistor, and two ends of the third resistor are respectively connected with the source of the fifth transistor and a drain of the fifth transistor;
the grid electrode of the sixth transistor is connected to a fourth control electrode voltage, the source electrode of the sixth transistor is connected with the drain electrode of the fifth transistor, two ends of the fourth resistor are respectively connected with the source electrode of the sixth transistor and the drain electrode of the sixth transistor, and the drain electrode of the sixth transistor is used as the second end of the attenuation circuit and is connected with the signal output end.
3. The passive circuit in a bypass mode of a radio frequency receive module of claim 2 wherein the attenuation circuit further comprises a second capacitor and a seventh transistor; the first end of the second capacitor is connected with the first end of the fifth resistor, the drain of the seventh transistor is connected with the second end of the second capacitor, the gate of the seventh transistor is connected to a fifth control voltage, and the source of the seventh transistor is grounded.
4. The passive circuit of claim 3, wherein the attenuation circuit further comprises a path inductor and an eighth transistor; a first end of the path inductor is connected with the signal input end, a drain of the eighth transistor is connected with a second end of the path inductor, a gate of the eighth transistor is connected to a sixth control voltage, and a source of the eighth transistor is grounded; the gate of the first transistor is connected to the drain of the eighth transistor.
5. The passive circuit in a bypass mode of a radio frequency receive module of claim 4, wherein the attenuation circuit further comprises a third capacitor, a first terminal of the third capacitor is connected to the drain of the sixth transistor, and a second terminal of the third capacitor is connected to the signal output terminal as a second terminal of the attenuation circuit.
6. The passive circuit in the RF receive module bypass mode of claim 4, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all NMOS transistors.
7. The passive circuit in the bypass mode of the rf receiving module of claim 1, further comprising a fourth capacitor, a first terminal of the fourth capacitor is connected to the drain of the second transistor and the second terminal of the supply inductor, respectively, and a second terminal of the fourth capacitor is connected to the signal output terminal.
8. The passive circuit in the bypass mode of the rf receive module of claim 1, further comprising a feedback inductor, a first terminal of the feedback inductor being connected to the source of the first transistor, a second terminal of the feedback inductor being connected to ground.
9. A radio frequency receive module, characterized in that the radio frequency receive module comprises a passive circuit in the bypass mode of the radio frequency receive module according to any one of claims 1 to 8.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222963335.6U CN218633923U (en) | 2022-11-07 | 2022-11-07 | Passive circuit under radio frequency receiving module bypass mode and radio frequency receiving module |
| PCT/CN2023/125978 WO2024099059A1 (en) | 2022-11-07 | 2023-10-23 | Passive circuit in bypass mode of radio frequency receiving module, and radio frequency receiving module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222963335.6U CN218633923U (en) | 2022-11-07 | 2022-11-07 | Passive circuit under radio frequency receiving module bypass mode and radio frequency receiving module |
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| Publication Number | Publication Date |
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| CN218633923U true CN218633923U (en) | 2023-03-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202222963335.6U Active CN218633923U (en) | 2022-11-07 | 2022-11-07 | Passive circuit under radio frequency receiving module bypass mode and radio frequency receiving module |
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| Country | Link |
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| CN (1) | CN218633923U (en) |
| WO (1) | WO2024099059A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024099059A1 (en) * | 2022-11-07 | 2024-05-16 | 深圳飞骧科技股份有限公司 | Passive circuit in bypass mode of radio frequency receiving module, and radio frequency receiving module |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7898325B2 (en) * | 2009-05-28 | 2011-03-01 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Amplifier with bypass switch |
| US9748993B2 (en) * | 2015-09-08 | 2017-08-29 | Mediatek Inc. | Radio frequency receiver front-end with gain control capability as well as improved impedance matching control capability |
| US11757419B2 (en) * | 2020-02-25 | 2023-09-12 | Smarter Microelectronics (Guang Zhou) Co., Ltd. | Radio frequency power amplifier circuit and gain control method |
| US11817829B2 (en) * | 2021-01-29 | 2023-11-14 | Skyworks Solutions, Inc. | Multi-mode broadband low noise amplifier |
| CN218633923U (en) * | 2022-11-07 | 2023-03-14 | 深圳飞骧科技股份有限公司 | Passive circuit under radio frequency receiving module bypass mode and radio frequency receiving module |
-
2022
- 2022-11-07 CN CN202222963335.6U patent/CN218633923U/en active Active
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2023
- 2023-10-23 WO PCT/CN2023/125978 patent/WO2024099059A1/en unknown
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024099059A1 (en) * | 2022-11-07 | 2024-05-16 | 深圳飞骧科技股份有限公司 | Passive circuit in bypass mode of radio frequency receiving module, and radio frequency receiving module |
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| WO2024099059A1 (en) | 2024-05-16 |
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