CN116131770B - High-integration-level high-linearity low-noise amplifier - Google Patents
High-integration-level high-linearity low-noise amplifier Download PDFInfo
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- CN116131770B CN116131770B CN202310411509.4A CN202310411509A CN116131770B CN 116131770 B CN116131770 B CN 116131770B CN 202310411509 A CN202310411509 A CN 202310411509A CN 116131770 B CN116131770 B CN 116131770B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention discloses a high-integration-level high-linearity low-noise amplifier, which comprises a high-isolation compensation network unit and a signal input end IN which are arranged IN parallel 1c And signal output terminal OUT 1c A radio frequency amplifying unit and a bypass unit between the two; the output end of the radio frequency amplifying unit passes through a radio frequency switch SW 4c And the high isolation compensation network unit is connected with the high isolation compensation network unit. The invention introduces a high isolation compensation network unit based on the low noise amplifier with bypass function. In the chip process, the resistor, the capacitor and the transistor which form the high-isolation compensation network unit can be realized through small-size devices, so that the compatibility of the low-noise characteristic and the high-linearity characteristic of the low-noise amplifier with the bypass function is realized on the basis of paying a small extra area cost, and the low-noise amplifier with the bypass function has better practicability.
Description
Technical Field
The invention belongs to the technical field of radio frequency front ends, and particularly relates to a high-integration-level high-linearity low-noise amplifier.
Background
Because the signal is transmitted for a long time, the signal is weak and doped with a large amount of noise, the useful signal acquired by the antenna end of the wireless receiver system has lower quality, small strength and various interference signals, which are caused by multipath effect and transmission loss. The key function of the receiving front end is to amplify a specific useful signal, perform down-conversion processing on the amplified signal, and demodulate the signal into a baseband signal for processing by a circuit of the back end.
The low noise amplifier is the most critical component at the front end of the radio frequency receiver, and is responsible for amplifying the signal received by the antenna end, and reducing the introduction of self noise as much as possible while amplifying the signal, so that the low noise amplifier is required to have the characteristics of small noise, proper gain and high linearity. If the gain of the low noise amplifier is too low, the effect of the post-stage circuit module on the noise performance of the whole system cannot be suppressed, which can cause interference to the transmission of the useful signal. If the noise figure of the low noise amplifier is too large, the noise characteristic of the system is directly deteriorated, which deteriorates the sensitivity of the receiver system, and the low noise amplifier is required to have high linearity in order to secure a wide dynamic range of the whole system. The low noise amplifier plays a decisive role in the performance of the receiving end.
When the output signal power of the low noise amplifier is larger than the output 1dB compression point, the output signal will generate serious distortion; increasing the input signal power, wherein the output power of the low noise amplifier will not increase with the increase of the input power after the output power reaches the saturated output power; the input signal power continues to be increased with the risk of damaging the device. In practical use, the bypass function is usually integrated on the low noise amplifier side to obtain a good quality radio frequency signal: when the input signal is a small signal, the low noise amplifier branch is turned on, the bypass branch is turned off, and the radio frequency signal enters the subsequent signal processing unit after being amplified by the low noise amplifier. When the input signal is a large signal, the low noise amplifier branch is turned off, the bypass branch is turned on, and the radio frequency signal enters the subsequent signal processing unit after passing through the bypass.
Due to the high integration and miniaturization requirements of radio frequency systems, it is generally desirable to integrate the low noise amplifier with the bypass circuit. The conventional low noise amplifier with bypass function generally adopts the structure shown in fig. 1 or fig. 2. As shown in fig. 1, in the bypass state, since the low noise amplifier still introduces a parasitic capacitance when turned off, the impedance of the low noise amplifier branch is not a high value, and the radio frequency signal leaks from the low noise amplifier branch in the off state, resulting in a poor linearity index in the bypass state. As shown in FIG. 2, the conventional bypass function with low noise as shown in FIG. 1On the basis of the acoustic amplifier, a radio frequency switch SW is added 4b In the bypass state, the RF switch SW 4b The low noise amplifier branch impedance is high, so that the linearity index of the bypass state is not influenced by the low noise amplifier branch in the off state. But radio frequency switch SW 4b Will introduce an additional RF switch SW in the low noise amplifier branch 4b On-resistance, which causes deterioration of noise figure of low noise amplifier, and at the same time, for reducing RF switch SW 4b On-resistance value, RF switch SW 4b A large size must be selected, which occupies a large chip area, and this tends to reduce the device area with high integration, resulting in a smaller package size, which is unacceptable for users in terms of miniaturization.
Disclosure of Invention
The invention aims to provide a high-integration high-linearity low-noise amplifier and aims to solve the problems.
The invention is realized mainly by the following technical scheme:
a high-linearity low-noise amplifier with high integration level comprises a high-isolation compensation network unit and a signal input end IN arranged IN parallel 1c And signal output terminal OUT 1c A radio frequency amplifying unit and a bypass unit between the two; the output end of the radio frequency amplifying unit passes through a radio frequency switch SW 4c The high isolation compensation network unit is connected with the high isolation compensation network unit; the high isolation compensation network unit comprises a PMOS transistor M 1d NMOS transistor M 2d NMOS transistor M 3d PMOS transistor M 4d PMOS transistor M 5d Resistance R 1d Resistance R 2d Resistance R 3d Resistance R 4d Resistance R 5d And capacitor C 1d The method comprises the steps of carrying out a first treatment on the surface of the The PMOS transistor M 1d Source of (d) and NMOS transistor M 2d Is connected with the drain of the NMOS transistor M 2d Source of (d) and NMOS transistor M 3d Is connected with the drain of the NMOS transistor M 3d The source electrode of the transistor is grounded; the PMOS transistor M 5d Source of (d) and PMOS transistor M 4d Is connected with the drain electrode of the transistor; the NMOS transistor M 2d PMOS transistorM 4d Cascaded and adopts common gate configuration as positive guide, the PMOS transistor M 5d Adopting a common source configuration as a negative transconductance; the resistor R 5d As a feedback resistor and arranged in the PMOS transistor M 5d Gate of (d) and NMOS transistor M 2d Is between the drains of (a); the capacitor C 1d Is arranged at the first end of the PMOS transistor M 4d Source of (d) and NMOS transistor M 2d The second end of the second electrode is grounded; the PMOS transistor M 1d PMOS transistor M 5d The drains of the two electrodes are respectively connected with a power supply; the PMOS transistor M 1d NMOS transistor M 2d NMOS transistor M 3d PMOS transistor M 4d The grid electrode of (C) is respectively connected with the resistor R 1d Resistance R 2d Resistance R 3d Resistance R 4d Is connected with a corresponding bias voltage; the radio frequency switch SW 4c Is connected with the output end of the amplifying unit, and the second end is connected with the input end IN 1d Connection, input IN 1d And PMOS transistor M 5d Source, PMOS transistor M 4d The drain electrode is connected.
In order to better realize the invention, the radio frequency amplifying unit further comprises an NMOS transistor M 1c NMOS transistor M 2c Radio frequency switch SW 2c Capacitance C 1c Capacitance C 3c The method comprises the steps of carrying out a first treatment on the surface of the The capacitor C 1c Is connected with the first end of the signal input end IN 1c Connection, the capacitor C 3c A second terminal of (2) and a signal output terminal OUT 1c Connecting; the NMOS transistor M 1c Source of (d) and NMOS transistor M 2c Drain connection of NMOS transistor M 2c The source electrode of the NMOS transistor M is grounded 2c Gate and capacitor C of (2) 1c The second end is connected; the radio frequency switch SW 2c Respectively with NMOS transistor M 1c Drain of (d) and rf switch SW 4c A first terminal connected to the capacitor C and a second terminal connected to the capacitor C 3c Is connected to the first end of the housing.
In order to better realize the invention, the radio frequency amplifying unit further comprises a resistor R 5c Resistance R 6c Capacitance C 2c Inductance L 1c The method comprises the steps of carrying out a first treatment on the surface of the The resistor R 5c Resistance R 6c For dividing the power supply into NMOS transistors M 1c Providing a static working point, the capacitor C 2c For compensating gain loss of the low noise amplifier at high frequencies; the NMOS transistor M 1c The grid electrode of (C) is respectively connected with the capacitor C 2c A first end of (1), a resistor R 5c A first end of (1), a resistor R 6c Is connected to the first end of the capacitor C 2c Resistance R 5c The second ends of the resistors R are respectively connected with the ground 6c Second terminal of (2) and inductance L 1c The first ends of the two terminals are respectively connected with a power supply; the NMOS transistor M 1c Drain electrode of (d) and inductance L 1c Is connected to the second end of the RF switch SW 2c Respectively with NMOS transistor M 1c Drain electrode of (d) and inductance L 1c Second terminal of (d) and radio frequency switch SW 4c A first terminal connected to the capacitor C and a second terminal connected to the capacitor C 3c Is connected to the first end of the housing.
In order to better implement the invention, further, the bypass unit comprises a radio frequency switch SW 1c The radio frequency switch SW 1c Respectively with the capacitor C 1c Second terminal of NMOS transistor M 2c Is connected with the grid of the radio frequency switch SW at the second end 2c Second terminal of (C) and capacitor C 3c Is connected to the first end of the housing.
In order to better realize the invention, the invention further comprises a direct current bias unit for NMOS transistor M in the full temperature range 2c Providing a stable static operating point.
In order to better realize the invention, the direct current bias unit further comprises a resistor R 1c Resistance R 2c Resistance R 3c Resistance R 4c NMOS transistor M 3c And a radio frequency switch SW 3c The method comprises the steps of carrying out a first treatment on the surface of the Resistor R 1c Is connected to a power supply, NMOS transistor M 3c The drain electrode of (a) is respectively connected with the resistor R 1c Second terminal of (a) radio frequency switch SW 3c A first end of (1), a resistor R 2c Is connected to the first end of the radio frequency switch SW 3c Second terminal of (d) and NMOS transistor M 3c The sources of (2) are respectively connected to groundNMOS transistor M 3c Gate and resistor R of (2) 3c Is connected with the first end of the resistor R 4c Respectively with resistor R 3c Resistance R 2c Is connected to the second end of the resistor R 4c Respectively with the capacitor C 1c Second terminal of (a) radio frequency switch SW 1c Is a first end of NMOS transistor M 2c Is connected to the gate of the transistor.
The parasitic resistance introduced by adding a switch at the input end of the low noise amplifier can deteriorate the noise coefficient of the low noise amplifier, and the noise coefficient of the low noise amplifier is not basically influenced by adding a switch at the output end.
The invention has the beneficial effects that:
(1) The invention introduces a high isolation compensation network unit based on the low noise amplifier with bypass function. In the chip process, the resistor, the capacitor and the transistor which form the high-isolation compensation network unit can be realized through small-size devices, so that the compatibility of the low-noise characteristic and the high-linearity characteristic of the low-noise amplifier with the bypass function is realized on the basis of paying a small extra area cost, and the low-noise amplifier with the bypass function has better practicability;
(2) When the input signal is a large signal, the low noise amplifier branch is turned off and the bypass branch is turned on. Performing inverse transformation on the capacitive impedance of the capacitor in the high-isolation compensation network unit to enable the capacitive impedance to present inductive impedance to the outside; at the moment, the high isolation compensation network unit resonates with parasitic capacitance introduced by the low noise amplifier in the off state, so that the low noise amplifier branch in the off state presents high resistance at the working frequency, and high linearity in the bypass state is realized.
Drawings
FIG. 1 is a conventional low noise amplifier with bypass function;
FIG. 2 is a schematic diagram of a conventional improved low noise amplifier with bypass function;
FIG. 3 is a schematic circuit diagram of the present invention;
FIG. 4 is a schematic circuit diagram of a high isolation compensation network element;
FIG. 5 is a graph showing the third-order intermodulation point contrast between the output of the present invention and the output of a conventional low noise amplifier with bypass function;
fig. 6 is a graph showing the noise figure versus the conventional improved low noise amplifier with bypass function according to the present invention.
Detailed Description
Example 1:
a high-linearity low-noise amplifier with high integration level, as shown IN FIG. 4, comprises a high-isolation compensation network unit and a signal input terminal IN arranged IN parallel 1c And signal output terminal OUT 1c A radio frequency amplifying unit and a bypass unit between the two; the output end of the radio frequency amplifying unit passes through a radio frequency switch SW 4c The high isolation compensation network unit is connected with the high isolation compensation network unit; the high isolation compensation network unit comprises a PMOS transistor M 1d NMOS transistor M 2d NMOS transistor M 3d PMOS transistor M 4d PMOS transistor M 5d Resistance R 1d Resistance R 2d Resistance R 3d Resistance R 4d Resistance R 5d And capacitor C 1d The method comprises the steps of carrying out a first treatment on the surface of the The PMOS transistor M 1d Source of (d) and NMOS transistor M 2d Is connected with the drain of the NMOS transistor M 2d Source of (d) and NMOS transistor M 3d Is connected with the drain of the NMOS transistor M 3d The source electrode of the transistor is grounded; the PMOS transistor M 5d Source of (d) and PMOS transistor M 4d Is connected with the drain electrode of the transistor; the NMOS transistor M 2d PMOS transistor M 4d Cascaded and adopts common gate configuration as positive guide, the PMOS transistor M 5d Adopting a common source configuration as a negative transconductance; the resistor R 5d As a feedback resistor and arranged in the PMOS transistor M 5d Gate of (d) and NMOS transistor M 2d Is between the drains of (a); the capacitor C 1d Is arranged at the first end of the PMOS transistor M 4d Source of (d) and NMOS transistor M 2d The second end of the second electrode is grounded; the PMOS transistor M 1d PMOS transistor M 5d The drains of the two electrodes are respectively connected with a power supply; the PMOS transistor M 1d NMOS transistor M 2d NMOS transistor M 3d PMOS transistor M 4d Gate of (2) is respectively communicated withOver-resistance R 1d Resistance R 2d Resistance R 3d Resistance R 4d Is connected with a corresponding bias voltage; the radio frequency switch SW 4c Is connected with the output end of the amplifying unit, and the second end is connected with the input end IN 1d Connection, input IN 1d And PMOS transistor M 5d Source, PMOS transistor M 4d The drain electrode is connected.
When the input signal is a large signal, the low noise amplifier branch is turned off and the bypass branch is turned on. Performing inverse transformation on the capacitive impedance of the capacitor in the high-isolation compensation network unit to enable the capacitive impedance to present inductive impedance to the outside; at the moment, the high isolation compensation network unit resonates with parasitic capacitance introduced by the low noise amplifier in the off state, so that the low noise amplifier branch in the off state presents high resistance at the working frequency, and high linearity in the bypass state is realized.
Preferably, as shown in fig. 3, the radio frequency amplifying unit includes an NMOS transistor M 1c NMOS transistor M 2c Radio frequency switch SW 2c Capacitance C 1c Capacitance C 3c The method comprises the steps of carrying out a first treatment on the surface of the The capacitor C 1c Is connected with the first end of the signal input end IN 1c Connection, the capacitor C 3c A second terminal of (2) and a signal output terminal OUT 1c Connecting; the NMOS transistor M 1c Source of (d) and NMOS transistor M 2c Drain connection of NMOS transistor M 2c The source electrode of the NMOS transistor M is grounded 2c Gate and capacitor C of (2) 1c The second end is connected; the radio frequency switch SW 2c Respectively with NMOS transistor M 1c Drain of (d) and rf switch SW 4c A first terminal connected to the capacitor C and a second terminal connected to the capacitor C 3c Is connected to the first end of the housing.
Preferably, as shown in fig. 3, the radio frequency amplifying unit further comprises a resistor R 5c Resistance R 6c Capacitance C 2c Inductance L 1c The method comprises the steps of carrying out a first treatment on the surface of the The resistor R 5c Resistance R 6c For dividing the power supply into NMOS transistors M 1c Providing a static working point, the capacitor C 2c For compensating gain loss of the low noise amplifier at high frequencies; the NMOS crystalTube M 1c The grid electrode of (C) is respectively connected with the capacitor C 2c A first end of (1), a resistor R 5c A first end of (1), a resistor R 6c Is connected to the first end of the capacitor C 2c Resistance R 5c The second ends of the resistors R are respectively connected with the ground 6c Second terminal of (2) and inductance L 1c The first ends of the two terminals are respectively connected with a power supply; the NMOS transistor M 1c Drain electrode of (d) and inductance L 1c Is connected to the second end of the RF switch SW 2c Respectively with NMOS transistor M 1c Drain electrode of (d) and inductance L 1c Second terminal of (d) and radio frequency switch SW 4c A first terminal connected to the capacitor C and a second terminal connected to the capacitor C 3c Is connected to the first end of the housing.
Preferably, as shown in fig. 3, the bypass unit comprises a radio frequency switch SW 1c The radio frequency switch SW 1c Respectively with the capacitor C 1c Second terminal of NMOS transistor M 2c Is connected with the grid of the radio frequency switch SW at the second end 2c Second terminal of (C) and capacitor C 3c Is connected to the first end of the housing.
Preferably, the device also comprises a DC bias unit for NMOS transistor M in the full temperature range 2c Providing a stable static operating point. The DC bias unit can be NMOS transistor M in the full temperature range 2c Providing a stable static operating point. When the input signal is a large signal, the RF switch SW 3c Turn on the NMOS transistor M 2c The gate voltage is pulled down to 0V, so that the low noise amplifier loses amplification and is in an off state.
Preferably, as shown in FIG. 3, the DC bias unit includes a resistor R 1c Resistance R 2c Resistance R 3c Resistance R 4c NMOS transistor M 3c And a radio frequency switch SW 3c The method comprises the steps of carrying out a first treatment on the surface of the Resistor R 1c Is connected to a power supply, NMOS transistor M 3c The drain electrode of (a) is respectively connected with the resistor R 1c Second terminal of (a) radio frequency switch SW 3c A first end of (1), a resistor R 2c Is connected to the first end of the radio frequency switch SW 3c Second terminal of (d) and NMOS transistor M 3c The source electrodes of the NMOS transistors are respectively connected with the groundM 3c Gate and resistor R of (2) 3c Is connected with the first end of the resistor R 4c Respectively with resistor R 3c Resistance R 2c Is connected to the second end of the resistor R 4c Respectively with the capacitor C 1c Second terminal of (a) radio frequency switch SW 1c Is a first end of NMOS transistor M 2c Is connected to the gate of the transistor.
The invention introduces a high isolation compensation network unit based on the low noise amplifier with bypass function. In the chip process, the resistor, the capacitor and the transistor which form the high-isolation compensation network unit can be realized through small-size devices, so that the compatibility of the low-noise characteristic and the high-linearity characteristic of the low-noise amplifier with the bypass function is realized on the basis of paying a small extra area cost, and the low-noise amplifier with the bypass function has better practicability.
Example 2:
a high-integration high-linearity low-noise amplifier is provided, which is based on a low-noise amplifier with bypass function and introduces a high-isolation compensation network unit. In the chip process, the resistor, the capacitor and the transistor which form the high-isolation compensation network unit can be realized through small-size devices, so that the compatibility of the low-noise characteristic and the high-linearity characteristic of the low-noise amplifier with the bypass function is realized on the basis of paying a small extra area cost.
As shown in fig. 4, the high isolation compensation network unit includes a radio frequency switch SW 4c PMOS transistor M 1d NMOS transistor M 2d NMOS transistor M 3d PMOS transistor M 4d PMOS transistor M 5d Resistance R 1d Resistance R 2d Resistance R 3d Resistance R 4d Resistance R 5d And capacitor C 1d . PMOS transistor M 4d And NMOS transistor M 2d The cascade adopts common gate configuration as positive guide, PMOS transistor M 5d A common source configuration is employed as the negative transconductance. Resistor R 5d Added as feedback resistor to PMOS transistor M 5d Gate of (d) and NMOS transistor M 2d An additional inductance is formed in the loop between the drains of the active inductor to increase the inductance of the active inductor.Auxiliary capacitor C 1d Is added to one end of the PMOS transistor M 4d Drain of (d) and NMOS transistor M 2d The other end is grounded. PMOS transistor M 1d And NMOS transistor M 3d As a current source to bias the circuit, V d1 、V d2 、V d3 And V d4 Respectively PMOS transistors M 1d NMOS transistor M 2d NMOS transistor M 3d And PMOS transistor M 4d Is provided.
Radio frequency switch SW 4c When the input signal is a large signal, the high isolation compensation network unit is in an on state, and the parasitic capacitance introduced by the low noise amplifier in an off state resonates, so that the low noise amplifier branch in the off state presents high resistance at the working frequency, and high linearity in a bypass state is realized.
The linearity of the low noise amplifier with the bypass function in the bypass state is generally measured by adopting the size of an output third-order intermodulation point, and the higher the output third-order intermodulation point is, the better the linearity is.
When the input signal is a small signal, the low noise amplifier branch is turned on, and the bypass branch is turned off, and because other parasitic devices are not introduced on the radio frequency channel, the low noise amplifier can obtain the optimal noise coefficient characteristic and the minimum chip area.
When the input signal is a large signal, the low noise amplifier branch is turned off and the bypass branch is turned on. The high-isolation compensation network unit is composed of an NMOS transistor, a PMOS transistor, a capacitor and a resistor, and the capacitive impedance of the capacitor in the high-isolation compensation network unit is inversely transformed to enable the capacitor to present inductive impedance to the outside. At the moment, the high isolation compensation network unit resonates with parasitic capacitance introduced by the low noise amplifier in the off state, so that the low noise amplifier branch in the off state presents high resistance at the working frequency, and high linearity in the bypass state is realized.
Example 3:
a high-integration high-linearity low-noise amplifier, as shown in figures 3 and 4, comprises a radio frequency amplifying and bypass unit, a direct current bias unit and a high-isolation compensation network unit.
As shown in fig. 3, the rf amplifying and bypassing unit includes an NMOS transistor M 1c NMOS transistor M 2c Resistance R 5c Resistance R 6c Capacitance C 1c Capacitance C 2c Capacitance C 3c Inductance L 1c Radio frequency switch SW 1c And a radio frequency switch SW 2c . Capacitor C 1c First end and signal input end IN 1c Connected to NMOS transistor M 2c Source is connected to ground, NMOS transistor M 2c Drain and NMOS transistor M 1c Source-side connection, NMOS transistor M 1c Grid and capacitor C 2c First end, resistor R 5c First end, resistor R 6c The first ends are connected together, the capacitor C 2c The second end is connected with the ground, and the resistor R 5c The second end is connected with the ground, and the resistor R 6c Second end and inductance L 1c First end, power supply VCC 1c Connected to the radio frequency switch SW 2c Second end and RF switch SW 1c Second end, capacitor C 3c The first ends are connected together, the capacitor C 3c A second terminal and a signal output terminal OUT 1c And (5) connection.
The DC bias unit comprises a resistor R 1c Resistance R 2c Resistance R 3c Resistance R 4c NMOS transistor M 3c And a radio frequency switch SW 3c . Resistor R 1c First end and power VCC 2c Connection, resistance R 1c Second end, RF switch SW 3c First end, resistor R 2c First end and NMOS transistor M 3c Drain electrodes are connected together, and a radio frequency switch SW 3c The second end is connected with the ground, the NMOS transistor M 3c Source is connected to ground, NMOS transistor M 3c Grid and resistor R 3c The first end is connected with the resistor R 3c Second end, resistor R 2c Second end and resistor R 4c The first ends being connected together, resistor R 4c Second end and capacitor C 1c Second end, RF switch SW 1c First end, NMOS transistor M 2c The gates are connected together.
As shown in fig. 4, the high isolation compensating network elementComprising a radio frequency switch SW 4c PMOS transistor M 1d NMOS transistor M 2d NMOS transistor M 3d PMOS transistor M 4d PMOS transistor M 5d Resistance R 1d Resistance R 2d Resistance R 3d Resistance R 4d Resistance R 5d And capacitor C 1d . Radio frequency switch SW 4c First end and NMOS transistor M 1c Drain electrode, inductance L 1c Second end, RF switch SW 2c The first ends are connected together. Radio frequency switch SW 4c Second and input terminals IN 1d Connection, input IN 1d And PMOS transistor M 5d Source, PMOS transistor M 4d Drain electrodes are connected together, PMOS transistor M 4d Source and capacitor C 1d First end, NMOS transistor M 2d Source, NMOS transistor M 3d Drain electrodes are connected together, capacitor C 1d The second end is connected with the ground, the NMOS transistor M 2d Drain and PMOS transistor M 1d Source, resistor R 5d The first ends being connected together, resistor R 5d Second end and PMOS transistor M 5d Gate connection, PMOS transistor M 1d Drain, PMOS transistor M 5d Drain and power VCC 1d Connected together, resistance R 1d First end and PMOS transistor M 1d Gate connection, resistance R 1d Second end and bias voltage V d1 Connection, resistance R 2d First end and NMOS transistor M 2d Gate connection, resistance R 2d Second end and bias voltage V d2 Connection, resistance R 3d First end and NMOS transistor M 3d Gate connection, resistance R 3d Second end and bias voltage V d3 Connection, resistance R 4d First end and PMOS transistor M 4d Gate connection, resistance R 4d Second end and bias voltage V d4 And (5) connection.
The invention introduces a high isolation compensation network unit based on the low noise amplifier with bypass function: in the chip process, the resistor, the capacitor and the transistor which form the high-isolation compensation network unit can be realized through small-size devices, so that the compatibility of the low-noise characteristic and the high-linearity characteristic of the low-noise amplifier with the bypass function is realized on the basis of paying a small extra area cost.
When the input signal is a small signal, the low noise amplifier branch is turned on, and the bypass branch is turned off, and because other parasitic devices are not introduced on the radio frequency channel, the low noise amplifier can obtain the optimal noise coefficient characteristic and the minimum chip area.
When the input signal is a large signal, the low noise amplifier branch is turned off and the bypass branch is turned on. The high-isolation compensation network unit is composed of an NMOS transistor, a PMOS transistor, a capacitor and a resistor, and the capacitive impedance of the capacitor in the high-isolation compensation network unit is inversely transformed to enable the capacitor to present inductive impedance to the outside. At the moment, the high isolation compensation network unit resonates with parasitic capacitance introduced by the low noise amplifier in the off state, so that the low noise amplifier branch in the off state presents high resistance at the working frequency, and high linearity in the bypass state is realized.
The working principle of the invention is as follows:
radio frequency signal passing through signal input IN 1c High-linearity low-noise amplifier with bypass function entering high integration level and passing through capacitor C at first 1b 。
When the input signal is a small signal, the external signal controls the RF switch SW 1c Switch-off, radio frequency switch SW 3c Switch-off, radio frequency switch SW 4c Switch-off, radio frequency switch SW 2c Conducting. The radio frequency signal sequentially passes through the NMOS transistor M 2c NMOS transistor M 1c Amplifying the signal, and passing the amplified radio frequency signal through a radio frequency switch SW 2c After that, pass through a capacitor C 3c From the signal output terminal OUT 1c And outputting.
When the input signal is a large signal, the external signal controls the RF switch SW 1c On, radio frequency switch SW 3c On, radio frequency switch SW 4c On, radio frequency switch SW 2c And (5) switching off. The radio frequency signal sequentially passes through the radio frequency switch SW 1c Capacitance C 3c Then, by the signal output terminal OUT 1c And outputting.
Inductance L 1c Supplying power to the low noise amplifier for the choke inductance;
resistor R 5c Resistance R 6c To power supply voltage VCC 1c To divide voltage into transistor M 1c Providing a static working point, a capacitor C 2c The gain loss of the low noise amplifier at high frequencies can be compensated.
Resistor R 1c Resistance R 2c Resistance R 3c Resistance R 4c NMOS transistor M 3c And a radio frequency switch SW 3c . The DC bias unit can be NMOS transistor M in the whole temperature range 2c Providing a stable static operating point. When the input signal is a large signal, the RF switch SW 3c Turn on the NMOS transistor M 2c The gate voltage is pulled down to 0V, so that the low noise amplifier loses amplification and is in an off state.
Radio frequency switch SW 4c When the input signal is a small signal, the high-isolation compensation network unit is in an off state, and the high-isolation compensation network unit is in a high configuration, so that the output characteristic of the resistor is hardly influenced.
PMOS transistor M 4d And NMOS transistor M 2d The cascade adopts common gate configuration as positive guide, PMOS transistor M 5d A common source configuration is employed as the negative transconductance. Resistor R 5d Added as feedback resistor to PMOS transistor M 5d Gate of (d) and NMOS transistor M 2d An additional inductance is formed in the loop between the drains of the active inductor to increase the inductance of the active inductor. Auxiliary capacitor C 1d Is added to one end of the PMOS transistor M 4d Drain of (d) and NMOS transistor M 2d The other end is grounded. PMOS transistor M 1d And NMOS transistor M 3d As a current source to bias the circuit, V d1 、V d2 、V d3 And V d4 Respectively PMOS transistors M 1d NMOS transistor M 2d NMOS transistor M 3d And PMOS transistor M 4d Is provided.
Radio frequency switch SW 4c When the input signal is a large signal, the input signal is in an on state, and the high-isolation compensation network unit and the low-noise amplifier are in an off stateParasitic capacitance introduced by the amplifier generates resonance, so that the low noise amplifier branch in the off state presents high resistance at the working frequency, thereby realizing high linearity in the bypass state.
The linearity of the low noise amplifier with the bypass function in the bypass state is generally measured by adopting the size of an output third-order intermodulation point, and the higher the output third-order intermodulation point is, the better the linearity is.
The noise performance of the low-noise amplifier with the bypass function in the amplifying state is generally measured by adopting the noise coefficient, and the smaller the noise coefficient is, the better the noise performance is.
As shown in FIG. 5, compared with the traditional low noise amplifier with bypass function, the invention can obtain better output third-order intermodulation point, namely better linearity performance, under the same output power in the bypass state.
As shown in fig. 6, the present invention has a lower noise figure performance in a wide band range as compared with the conventional improved low noise amplifier with bypass function.
The foregoing description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and any simple modification, equivalent variation, etc. of the above embodiment according to the technical matter of the present invention fall within the scope of the present invention.
Claims (6)
1. The high-linearity low-noise amplifier with high integration level is characterized by comprising a high-isolation compensation network unit and a signal input end IN which are arranged IN parallel 1c And signal output terminal OUT 1c A radio frequency amplifying unit and a bypass unit between the two; the output end of the radio frequency amplifying unit passes through a radio frequency switch SW 4c The high isolation compensation network unit is connected with the high isolation compensation network unit; the high isolation compensation network unit comprises a PMOS transistor M 1d NMOS transistor M 2d NMOS transistor M 3d PMOS transistor M 4d PMOS transistor M 5d Resistance R 1d Resistance R 2d Resistance R 3d Resistance R 4d Resistance R 5d And capacitor C 1d The method comprises the steps of carrying out a first treatment on the surface of the The PMOS transistor M 1d Source of (d) and NMOS transistor M 2d Is connected with the drain of the NMOS transistor M 2d Source of (d) and NMOS transistor M 3d Is connected with the drain of the NMOS transistor M 3d The source electrode of the transistor is grounded; the PMOS transistor M 5d Source of (d) and PMOS transistor M 4d Is connected with the drain electrode of the transistor; the NMOS transistor M 2d PMOS transistor M 4d Cascaded and adopts common gate configuration as positive guide, the PMOS transistor M 5d Adopting a common source configuration as a negative transconductance; the resistor R 5d As a feedback resistor and arranged in the PMOS transistor M 5d Gate of (d) and NMOS transistor M 2d Is between the drains of (a); the capacitor C 1d Is arranged at the first end of the PMOS transistor M 4d Source of (d) and NMOS transistor M 2d The second end of the second electrode is grounded; the PMOS transistor M 1d PMOS transistor M 5d The drains of the two electrodes are respectively connected with a power supply; the PMOS transistor M 1d NMOS transistor M 2d NMOS transistor M 3d PMOS transistor M 4d The grid electrode of (C) is respectively connected with the resistor R 1d Resistance R 2d Resistance R 3d Resistance R 4d Is connected with a corresponding bias voltage; the radio frequency switch SW 4c Is connected with the output end of the amplifying unit, and the second end is connected with the input end IN 1d Connection, input IN 1d And PMOS transistor M 5d Source, PMOS transistor M 4d The drain electrode is connected.
2. The high-integration high-linearity low-noise amplifier of claim 1, wherein said radio frequency amplifying unit comprises an NMOS transistor M 1c NMOS transistor M 2c Radio frequency switch SW 2c Capacitance C 1c Capacitance C 3c The method comprises the steps of carrying out a first treatment on the surface of the The capacitor C 1c Is connected with the first end of the signal input end IN 1c Connection, the capacitor C 3c A second terminal of (2) and a signal output terminal OUT 1c Connecting; the NMOS transistor M 1c Source of (d) and NMOS transistor M 2c Drain connection of NMOS transistor M 2c The source electrode of the NMOS transistor M is grounded 2c Is a gate of (2)Electrode and capacitor C 1c The second end is connected; the radio frequency switch SW 2c Respectively with NMOS transistor M 1c Drain of (d) and rf switch SW 4c A first terminal connected to the capacitor C and a second terminal connected to the capacitor C 3c Is connected to the first end of the housing.
3. The high-integration high-linearity low-noise amplifier of claim 2, wherein said radio frequency amplifying unit further comprises a resistor R 5c Resistance R 6c Capacitance C 2c Inductance L 1c The method comprises the steps of carrying out a first treatment on the surface of the The resistor R 5c Resistance R 6c For dividing the power supply into NMOS transistors M 1c Providing a static working point, the capacitor C 2c For compensating gain loss of the low noise amplifier at high frequencies; the NMOS transistor M 1c The grid electrode of (C) is respectively connected with the capacitor C 2c A first end of (1), a resistor R 5c A first end of (1), a resistor R 6c Is connected to the first end of the capacitor C 2c Resistance R 5c The second ends of the resistors R are respectively connected with the ground 6c Second terminal of (2) and inductance L 1c The first ends of the two terminals are respectively connected with a power supply; the NMOS transistor M 1c Drain electrode of (d) and inductance L 1c Is connected to the second end of the RF switch SW 2c Respectively with NMOS transistor M 1c Drain electrode of (d) and inductance L 1c Second terminal of (d) and radio frequency switch SW 4c A first terminal connected to the capacitor C and a second terminal connected to the capacitor C 3c Is connected to the first end of the housing.
4. The high-integration high-linearity low-noise amplifier of claim 2, wherein said bypass unit comprises a radio frequency switch SW 1c The radio frequency switch SW 1c Respectively with the capacitor C 1c Second terminal of NMOS transistor M 2c Is connected with the grid of the radio frequency switch SW at the second end 2c Second terminal of (C) and capacitor C 3c Is connected to the first end of the housing.
5. A high integration, high linearity, low noise, as defined in claim 2The acoustic amplifier is characterized by further comprising a DC bias unit, wherein the DC bias unit is used for NMOS transistor M in the full temperature range 2c Providing a stable static operating point.
6. The high-integration high-linearity low-noise amplifier of claim 5, wherein said DC bias unit comprises a resistor R 1c Resistance R 2c Resistance R 3c Resistance R 4c NMOS transistor M 3c And a radio frequency switch SW 3c The method comprises the steps of carrying out a first treatment on the surface of the Resistor R 1c Is connected to a power supply, NMOS transistor M 3c The drain electrode of (a) is respectively connected with the resistor R 1c Second terminal of (a) radio frequency switch SW 3c A first end of (1), a resistor R 2c Is connected to the first end of the radio frequency switch SW 3c Second terminal of (d) and NMOS transistor M 3c The source electrodes of the NMOS transistors M are respectively connected with the ground 3c Gate and resistor R of (2) 3c Is connected with the first end of the resistor R 4c Respectively with resistor R 3c Resistance R 2c Is connected to the second end of the resistor R 4c Is a second end of (2) respectively with the capacitor C 1c Second terminal of (a) radio frequency switch SW 1c Is a first end of NMOS transistor M 2c Is connected to the gate of the transistor.
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| CN117294264B (en) * | 2023-11-22 | 2024-03-12 | 成都明夷电子科技有限公司 | Low-noise transimpedance amplifier for optical receiver |
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