CN111934627A - CMOS low-distortion low-noise amplifier circuit - Google Patents
CMOS low-distortion low-noise amplifier circuit Download PDFInfo
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Abstract
The invention discloses a CMOS low-distortion low-noise amplifier circuit, which is applied to the field of radio frequency integrated circuits and aims at solving the problems that the third-order intermodulation linearity of the amplifier circuit in the prior art is below 0dBm and the amplifier circuit is difficult to deal with the large-signal interference environment; the transconductance input stage of the invention adopts a complementary common source stage structure, so that the current efficiency is doubled; the linearity improving stage adopts a complementary common-emitter stage to improve the small-signal linearity of the complementary common-source stage; the feedback stage adopts a source follower to solve the problem of second-order interaction of nonlinear active feedback; the off-chip element and the input parasitic capacitor form a pi-type matching network to enhance the input matching bandwidth, so that the use of on-chip high-capacity inductor is avoided; the common mode feedback circuit detects the common mode voltage of the output port of the low noise discharge circuit and compares the common mode voltage with the reference voltage to obtain an error signal which is connected to the M through the feedback of the bias resistorp1、Mp2The grid electrode of the grid electrode is dynamically adjusted, so that the circuit works in stable direct current workAnd (4) point.
Description
Technical Field
The invention belongs to the field of radio frequency integrated circuits, and particularly relates to a low-noise amplifier circuit.
Background
At present, software wireless end technology is increasingly popularized, only a baseband software protocol layer needs to be configured, and various standards meeting the requirements of different communication protocols can be flexibly compatible with each other and coexist on a set of hardware equipment platform. Therefore, the research on broadband rf transceiving technology is becoming more and more important. Compared with the traditional bulky transceiver structure, the new saw (surface acoustic wave) -free filter transceiver structure proposed in recent years quickly becomes the focus of attention in the industry. In order to obtain good anti-blocking interference capability, the SAW-less receiver design abandons the traditional voltage mode and adopts a novel current mode design concept instead.
With the increasing working frequency of rf integrated circuits, in the application environment of low voltage and low power consumption, the traditional voltage mode circuit can not deal with the processing of circuit signals well, and the disadvantages of nonlinearity, etc. are gradually revealed. And the current mode circuit which takes the current as a signal variable to represent the carrier can solve the bottleneck of the voltage mode circuit in the aspects of speed, bandwidth, low voltage and low power consumption. In recent years, the potential advantages of current mode circuits in analog/mixed signal processing are gradually being exploited and gradually penetrating into the field of rf integrated circuit design technology.
The core circuit unit structure of the SAW-less receiver is shown in fig. 1, and comprises a low noise (transconductance) amplifier, a current commutation type passive mixer and a baseband filter as constituent units. In principle, the blocking interference is converted into a current signal by a low-noise amplifier, and the blocking current signal is eliminated at a baseband filter after the mixer. The noise of the low noise amplifier located at the first stage of the receiving chain is very important, so the noise optimization problem in the broadband constitutes another difficulty of the SAW-free receiver. Furthermore, the low noise gain cannot be exchanged with large power consumption, since low power consumption has always been the basic starting point for chip design.
In prior art 1(e.a. keehr and a.hajimiri, "a Wide-Swing Low-Noise transmission Amplifier and the amplification of Large-Signal Handling Direct-Conversion Receivers," IEEE trans.circuits system.Regul.Pap., vol.59, No.1, pp.30-43, Jan.2012), based on push-pull operation, a Large Signal input 1dB compression point of 22dBm was achieved. However, because of the matching requirements, the transconductance tends to be small; note that the receiver is band limited. In prior art 2(m.mehrpoo and r.b.staszewski, "ahigh selective LNTA capable of large-signal handling for RF receiver front-ends," in 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC),2013, pp.185-188), a push-pull cascode structure with gm enhancement and N-way filtering is proposed, which achieves large transconductance and high linearity. However, the noise figure is large (6.5 dB) and the single-ended structure is less robust against interference. Note that both of these structures require bulky on-chip inductors. In addition, the document (Guo Benqing, A8.1 mW 0.1-2 GHz induced loss CMOS LNTA for software-defined radio applications, IEEE ASICON,1-4,2015) proposes an innovative scheme, the power consumption and the noise are low, but the linearity of a third-order intermodulation point is below 0dBm, and the large signal interference environment is difficult to deal with.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a CMOS low-distortion low-noise amplifier circuit, which has low noise, low distortion (high linearity), low power consumption, and anti-blocking capability.
The technical scheme adopted by the invention is as follows: a CMOS low noise wideband low distortion amplifier comprising: a transconductance amplifier stage, a linearity booster stage, a feedback stage, an output load stage, a common mode feedback circuit, and off-chip components.
The transconductance amplifier stage comprises a PMOS transistor Mp1PMOS transistor Mp2NMOS transistor Mn1NMOS transistor Mn2Capacitor CL1Capacitor CL2Capacitor CR1Capacitor CR2；
PMOS transistor Mp1Grid passing capacitor CL1Connected to terminal X, a PMOS transistor Mp1Source connected to VDD, PMOS transistor Mp1Drain connected NMOS transistor Mn1A drain electrode; NMOS transistor Mn1Grid passing capacitor CL2Connected to terminal X, NMOS transistor Mn1Source grounded, NMOS transistor Mn1The drain is connected with the positive output end Vout+(ii) a PMOS transistor MP2Grid passing capacitor CR1Connected to terminal Y, a PMOS transistor MP2Source connected to VDD, PMOS transistor MP2Drain connected NMOS transistor Mn2A drain electrode; NMOS transistor Mn2Grid passing capacitor CR2Inductor LRIs connected with a negative input end V of a radio frequency signalrfin-NMOS transistor Mn2Source grounded, NMOS transistor Mn2Drain electrode connected with negative output end Vout-；
PMOS transistor Mp1、Mp2The grid is connected with the output end V of the common mode feedback circuit through a bias resistor respectivelyfbNMOS transistor Mn1、Mn2The grid is respectively connected with a bias voltage V through a bias resistorbn1(typically 0.69V) for dc biasing the two NMOS transistors, which is about +100mV of the threshold voltage of the NMOS transistor.
The linear boost stage comprises a PNP type BJT transistor Qp1PNP type BJT transistor Qp2NPN BJT transistor Qn1NPN BJT transistor Qn2Capacitor CL3Capacitor CL4Capacitor CR3Capacitor CR4；
PNP type BJT transistor Qp1Base passing capacitor CL3PNP BJT transistor Q connected to terminal Xp1Emitter pass resistor Rdgp1PNP BJT transistor Q connected to VDDp1Collector connected with positive output end Vout+(ii) a NPN BJT transistor Qn1Base passing capacitor CL4An NPN BJT transistor Q connected to the terminal Xn1Emitter pass resistor Rdgn1Grounded, NPN BJT transistor Qn1Collector connected with positive output end Vout+；
PNP type BJT transistor Qp2Base passing capacitor CR3PNP BJT transistor Q connected to terminal Yp2Emitter pass resistor Rdgp2PNP BJT transistor Q connected to VDDp2The collector is connected with the negative output end Vout-(ii) a NPN BJT transistor Qn2Base passing capacitor CR4An NPN BJT transistor Q connected to terminal Yn2Emitter pass resistor Rdgn2Grounded, NPN BJT transistor Qn2The collector is connected with the negative output end Vout-；
PNP type BJT transistor Qp1、Qp2Respectively connected with a bias voltage V through bias resistorsbp2(typical value is 1.0V) for carrying out direct current bias on two PNP transistors and NPN type BJT transistor Qn1、Qn2Respectively connected with a bias voltage V through bias resistorsbn2(typically 0.76V) for dc biasing the two NPN transistors.
The feedback stage comprises an NMOS transistor M5NMOS transistor M6NMOS transistor M7NMOS transistor M8Capacitor CL5Capacitor CL6Capacitor CR5Capacitor CR6Resistance RFLResistance RFR；
NMOS transistor M5Grid passing capacitor CL5Is connected with a positive output end Vout+Source pass resistor R of NMOS transistorFLThe NMOS transistor drain electrode is connected with VDD; NMOS transistor M6Grid passing capacitor CL6Is connected with a negative output end Vout-NMOS transistor M6Source grounded, NMOS transistor M6Drain connected to NOMS transistor M5A source stage of (a); NMOS transistor M7Grid passing capacitor CR5Is connected with a negative output end Vout-NMOS transistor M7Source pass resistor RFRConnected to terminal Y, NMOS transistor M7The drain electrode is connected with VDD; NMOS transistor M8Grid passing capacitor CR6Is connected with a positive output end Vout+NMOS transistor M8Source grounded, NMOS transistor M8Drain connected NMOS transistor M7A source stage of (a);
NMOS transistor M5、M7The grid is respectively connected with a bias voltage V through a bias resistorbn3(typically 1.8V), NMOS transistor M6、M8The grid is respectively connected with a bias voltage V through a bias resistorbn4(typically 0.9V); capacitor Cntr1One end is connected with the negative output end Vout-One end is connected with a terminal X; capacitor Cntr2One end is connected with the positive output end Vout+And one end is connected to endpoint Y.
The output load stage comprises a capacitor CLL、CLRAnd a resistance RLL、RLR. Capacitor with a capacitor elementCLLOne end and a positive output end Vout+Connected with the other end through a resistor RLLGrounding; capacitor CLROne end and a negative output end Vout-Connected with the other end through a resistor RLRAnd (4) grounding.
The bond wire inductor and off-chip capacitor include: bond wire inductance LLAnd a bonding wire inductance LRAnd off-chip capacitor CbLAnd off-chip capacitor CbR(ii) a Off-chip capacitor CbLOne end of the capacitor is grounded and an off-chip capacitor CbLThe other end is connected with a radio frequency positive input end Vrfin+(ii) a Off-chip capacitor CbROne end of the capacitor is grounded and an off-chip capacitor CbRThe other end is connected with a radio frequency negative input end Vrfin-(ii) a Bond wire inductance LLOne end is connected with a radio frequency positive input end Vrfin+Inductance of bonding wire LLThe other end is connected with a terminal point X; bond wire inductance LROne end is connected with a radio frequency negative input end Vrfin-Inductance of bonding wire LRThe other end terminates at a terminal point Y.
The common mode feedback Circuit (CMFB) comprises a PMOS transistor M9PMOS transistor M10NMOS transistor M11NMOS transistor M12NMOS transistor M13NMOS transistor M14NMOS transistor M15NMOS transistor M16(ii) a PMOS transistor M9Grid and PMOS transistor M10Gate connected, PMOS transistor M9Source connected to VDD, PMOS transistor M9The drain electrode is connected with the grid electrode of the drain electrode; PMOS transistor M10Source connected to VDD, PMOS transistor M10Drain electrode connected to output end V of common mode feedback circuitfb(ii) a NMOS transistor M11Grid connected with positive output end Vout+NMOS transistor M11Drain connected PMOS transistor M9Drain, NMOS transistor M11Source and NMOS transistor M13The source stage is connected; NMOS transistor M12Grid connected with negative output end Vout-NMOS transistor M12Source and NMOS transistor M14Source, NMOS transistor M12Drain connected NMOS transistor M9A drain electrode; NMOS transistor M13The grid is connected with a reference voltage VrefNMOS transistor M13Source connected NMOS transistor M15Drain, NMOS transistor M13Drain and PMOS transistor M10The drain electrodes are connected; NMOS transistor M14The grid is connected with a reference voltage VrefNMOS transistor M14Source connected NMOS transistor M16Drain, NMOS transistor M14Drain and PMOS transistor M10The drain electrodes are connected; NMOS transistor M15Grid electrode is connected with bias voltage VBNMOS transistor M15The source level is grounded; NMOS transistor M16Grid electrode is connected with bias voltage VBNMOS transistor M16The source is grounded.
The invention has the beneficial effects that: the low-noise low-distortion amplifier (LNTA) adopts a differential structure, a radio frequency signal passes through a pi-type matching network, a voltage signal is amplified and converted into a current signal by a transconductance amplification stage, and the current signal flows to an output load stage; the linear boost stage is connected with the transconductance stage in parallel, so that the linearity of the low-noise amplifier circuit is improved; the feedback circuit realizes broadband matching; the common mode feedback circuit provides a stable direct current working point for the circuit. The invention can realize wider frequency band and good performances of noise, linearity and the like; the amplifier circuit of the present invention includes the following advantages:
1. based on the cross-coupling structure, the active feedback stage realizes broadband matching and improves the noise performance in the circuit;
2. cross coupling capacitance CntrBy adopting the method, the Miller equivalent capacitance of the input end can be eliminated;
3. based on a derivative cancellation principle, improving the linearity of the small signal by adopting an auxiliary path linearity improvement level;
4. the current is multiplexed by adopting a complementary symmetrical structure of the transistor, so that the power consumption of the circuit is reduced;
5. using bond wire inductance, off-chip capacitance, and LNTA input parasitic capacitance (specifically approximated by C)gs,Mn1+Cgs,Mp1+Cbe,Qn1+Cbe,Qp1+(Cgd,Mn1+Cgd,Mp1+Cbc,Qn1+Cbc,Qp1) Av, where Av represents the voltage gain, about 3 times. ) The formed pi-type matching network enhances the circuit bandwidth.
Drawings
FIG. 1 is a SAW-less receiver core circuit element;
FIG. 2 is a schematic diagram of a prior art low noise discharge circuit;
FIG. 3 is a schematic diagram of a prior art low noise discharge circuit;
FIG. 4 is a schematic diagram of a CMOS low distortion low noise amplifier of the present invention;
FIG. 5 is a schematic diagram of a CMOS low distortion low noise amplifier common mode feedback circuit of the present invention;
FIG. 6 shows the input port matching results of a CMOS low distortion low noise amplifier of the present invention;
FIG. 7 is a graph of the noise results of a CMOS low distortion low noise amplifier of the present invention;
FIG. 8 is a graph of the in-band IIP3 simulation results for a CMOS low distortion low noise amplifier of the present invention;
FIG. 9 is a graph of the noise results under blocking interference for a CMOS low distortion low noise amplifier of the present invention;
fig. 10 is a graph of S21 and transconductance gain for a CMOS low distortion low noise amplifier of the present invention.
Detailed Description
In order to facilitate the understanding of the technical contents of the present invention by those skilled in the art, the present invention will be further explained with reference to the accompanying drawings.
The invention is a CMOS low noise broadband low distortion amplifier, the structure of which is shown in figure 4, comprising: a transconductance amplifier stage, a linearity booster stage, a feedback stage, an output load stage, a common mode feedback circuit, and off-chip components.
The transconductance input stage is a main path and is used for signal amplification in a current mode, and a complementary common source stage structure (M) is adoptedn1And Mp1、Mn2And Mp2) The current efficiency can be doubled. The auxiliary path is a linear boosting stage, and adopts a complementary common emitter stage (Q) based on a derivative cancellation principlen1And Qp1、Qn2And Qp2) To improve the small signal linearity of the main path common source stage. Wherein, the resistance RdgnAnd RdgpFor adjusting the distortion amplitude of the BJT tube. In addition, the BJT transistor in the weak inversion region is only consumableA negligible direct current. The feedback stage adopts a source follower to solve the problem of second-order interaction of nonlinear active feedback. The off-chip element and the input parasitic capacitor form a pi-type matching network to enhance the input matching bandwidth, so that the use of on-chip high-capacity inductor can be avoided. The common mode feedback circuit detects the output port I of the low noise discharge circuitO+、IO-Is compared with a reference voltage VDD/2, and the obtained error signal is connected to M through a bias resistor in a feedback wayp1、Mp2The gate of the circuit is dynamically adjusted so that the circuit operates at a stable DC operating point.
Single-ended input impedance Z of the inventioninCan be expressed as
Wherein, gm1Is a single-ended equivalent common source transistor Mn1、Mp1Total transconductance, here parameter gm3Equivalent stands for BJT transistor Qn1、Qp1Total transconductance (g)m3＝gmQn1+gmQp1)，RFIs a single-ended equivalent feedback resistor, RLIs a single-ended equivalent load resistance. gm5、gm6Is M5And M6Transconductance of (1); rinIs the input resistance of the circuit (set to 50 Ω).
Regarding the linearity of low noise amplification, the third-order distortion current expression is as follows
Where a1 is the intermediate derivative variable, which is 0.5 under the input match condition. Transistor Q of the auxiliary pathn1、Qp1And a MOS transistor M of a main pathn1、Mp1Carrying out nonlinear superposition cancellation to enable the total transconductance first-order derivative g of the common-source transistorm1' and second derivative gm1"close to zero. Thus, only M remains5And M6Transconductance derivative of gm5′,gm6′gm5″,gm6"associated terms, although when f1＝-2gm1a1RLThis residual term can also be eliminated, however, in practical simulations, this conflicts with the impedance matching condition. Therefore, the present invention employs gm6，gm5The method of applying a large drive voltage (-400 mV) makes the effect of this residual term negligible. Finally, the circuit is ensured to obtain high linearity.
Examples
The low-noise discharge circuit provided by the embodiment is realized by adopting a 180nm radio frequency CMOS (complementary metal oxide semiconductor) process, adopts 1.8V voltage for power supply, and has the power consumption of 18 mW. FIG. 6 is a graph of simulation results of S11 with low noise, which shows when S11 shows<At-10 dB, the upper frequency limit is 2.7 GHz; FIG. 7 shows the noise figure results with a minimum noise figure NF of about 2.84 dB; figure 8 shows the in-band IIP3 simulation results: a maximum of 22.5dBm, where a 10MHz two tone test frequency interval is used. Its power compression point P1dB can also be seen>2.5 dB; FIG. 9 is a graph of the simulation results of Blocker NF in the presence of jamming, at PblockerUnder the frequency offset condition of 0dBm and 100MHZ, the noise performance at the 1GHz point frequency is NF 3.3 dB; fig. 10 shows a gain curve of a low noise amplifier, and it is noted that the voltage gain is 4dB, the transconductance gain reaches a peak value of 100mS within a 3dB bandwidth, and the passive inductive resonance effect of the input matching network is benefited; in contrast, at low frequencies, its transconductance is about 80 mS.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (10)
1. A CMOS low distortion, low noise amplifier circuit, comprising: the circuit comprises a transconductance amplification stage, a linear boosting stage, a feedback stage, an output load stage, a common-mode feedback circuit and an off-chip element;
the first end of the transconductance amplification stage passes through an inductor LLIs connected with a positive input port V of an alternating current signalrfin+The second end of the transconductance amplifier stage is connected with the output end V of the common mode feedback circuitfbThe third end of the transconductance amplifying stage passes through an inductor LRIs connected with a negative input port V of an alternating current signalrfin-The transconductance amplifier stage is used for receiving a radio frequency negative input alternating current small signal with a phase difference of 180 degrees with a radio frequency positive input signal, and the fourth end of the transconductance amplifier stage is connected with a positive-polarity radio frequency signal output port V of the amplifier circuitout+The fifth end of the transconductance amplifier stage is connected with a negative radio frequency signal output port V of the amplifier circuitout-The low-noise amplifier is used for amplifying the alternating current small signal;
the first end of the linear boost stage passes through an inductor LLIs connected with a positive input port V of a radio frequency signalrfin+Second end of linear boost stage is connected with positive output port Vout+The third end of the linear boost stage is connected with a negative output port Vout-The fourth end of the linear boost stage passes through an inductor LRIs connected with a negative input port V of a radio frequency signalrfin-；
The first end of the feedback stage passes through an inductor LLIs connected with a positive input port V of a radio frequency signalrfin+The second end of the feedback stage passes through an inductor LLIs connected with a negative input port V of a radio frequency signalrfin-The third end of the feedback stage is connected with a positive output port Vout+The fourth end of the feedback stage is connected with a negative output port Vout-The fifth end of the feedback stage is connected with the positive output port Vout+The sixth end of the feedback stage is connected with the negative output port Vout-；
The first end of the output load stage is connected with a positive output port Vout+The second end of the output load stage is grounded, and the third end of the output load stage is connected with a negative output port Vout-The fourth end of the output load stage is grounded;
the first end of the common mode feedback circuit is connected with a positive output port Vout+The second end of the common mode feedback circuit is connected with a negative output port Vout-Common mode feedback circuitThe third end is a common mode feedback circuit output port Vfb(ii) a The common mode feedback circuit is used for receiving the output voltage of the common mode feedback circuit so as to provide direct current bias for the two PMOS tubes;
the off-chip component at least comprises an inductor LLInductor LR。
2. A CMOS low noise low distortion amplifier according to claim 1, wherein said transconductance amplifier stage comprises a PMOS transistor Mp1PMOS transistor Mp2NMOS transistor Mn1NMOS transistor Mn2Capacitor CL1Capacitor CL2Capacitor CR1Capacitor CR2；
PMOS transistor Mp1Grid and capacitor CL1A first terminal connected to a capacitor CL1The second terminal is used as the first terminal of the transconductance amplifier stage, and the PMOS transistor Mp1Source connected to VDD, PMOS transistor Mp1Drain connected NMOS transistor Mn1A drain electrode; NMOS transistor Mn1Grid and capacitor CL2A first terminal connected to a capacitor CL2Second terminal and capacitor CL1A second terminal connected to the NMOS transistor Mn1Source grounded, NMOS transistor Mn1The drain electrode is used as the fourth end of the transconductance amplification stage; PMOS transistor MP2Grid and capacitor CR1A first terminal connected to a capacitor CR1The second terminal is used as the third terminal of the transconductance amplifier stage, and the PMOS transistor MP2Source connected to VDD, PMOS transistor MP2Drain connected NMOS transistor Mn2A drain electrode; NMOS transistor Mn2Grid electrode connected capacitor CR2First terminal, capacitor CR2The second terminal is connected with a capacitor CR1Second terminal, NMOS transistor Mn2Source grounded, NMOS transistor Mn2The drain electrode is used as the fifth end of the transconductance amplifying stage.
3. A CMOS low distortion low noise amplifier circuit as defined in claim 2, wherein the PMOS transistor Mp1Grid, PMOS transistor Mp2The grid is connected with the output end V of the common mode feedback circuit through a bias resistor respectivelyfbNMOS transistor Mn1、NMOSTransistor Mn2The grid is respectively connected with a bias voltage V through a bias resistorbn1。
4. The CMOS low distortion low noise amplifier circuit of claim 1, wherein said linearity enhancement stage comprises a PNP BJT transistor Qp1PNP type BJT transistor Qp2NPN BJT transistor Qn1NPN BJT transistor Qn2Capacitor CL3Capacitor CL4Capacitor CR3Capacitor CR4Resistance Rdgp1Resistance Rdgn1Resistance Rdgp2Resistance Rdgn2；
PNP type BJT transistor Qp1Base and capacitor CL3A first terminal connected to a capacitor CL3The second terminal is used as the first terminal of the linear boost stage, and the PNP type BJT transistor Qp1Emitter pass resistor Rdgp1PNP BJT transistor Q connected to VDDp1Collector as second end of linear boost, NPN type BJT transistor Qn1Base and capacitor CL4A first terminal connected to a capacitor CL4The second terminal is connected with a capacitor CL3Second terminal, NPN BJT transistor Qn1Emitter pass resistor Rdgn1Grounded, NPN BJT transistor Qn1Collector and PNP BJT transistor Qp1The collector electrodes are connected;
PNP type BJT transistor Qp2Base and capacitor CR3A first terminal connected to a capacitor CR3The second terminal is used as the fourth terminal of the linear boosting stage, and the PNP type BJT transistor Qp2Emitter pass resistor Rdgp2PNP BJT transistor Q connected to VDDp2The collector is used as a third end of the linear boost stage; NPN BJT transistor Qn2Base and capacitor CR4A first terminal connected to a capacitor CR4Second terminal and capacitor CR3A second terminal connected to an NPN BJT transistor Qn2Emitter pass resistor Rdgn2Grounded, NPN BJT transistor Qn2Collector and PNP BJT transistor Qp2The collector electrodes are connected.
5. A CMOS low distortion device according to claim 4Low noise amplifier circuit, characterized in that PNP type BJT transistor Qp1Base, PNP type BJT transistor Qp2The base electrodes are respectively connected with a bias voltage V through bias resistorsbp2(ii) a NPN BJT transistor Qn1Base, NPN type BJT transistor Qn2The base electrodes are respectively connected with a bias voltage V through bias resistorsbn2。
6. A CMOS low distortion low noise amplifier circuit according to claim 1, wherein said feedback stage comprises an NMOS transistor M5NMOS transistor M6NMOS transistor M7NMOS transistor M8Capacitor CL5Capacitor CL6Capacitor CR5Capacitor CR6Resistance RFLResistance RFR；
NMOS transistor M5Grid and capacitor CL5A first terminal connected to a capacitor CL5The second terminal is used as the third terminal of the feedback stage, and the NMOS transistor M5Source and resistor RFLA first terminal connected to a resistor RFLThe second terminal is used as the first terminal of the feedback stage, and the NMOS transistor M5The drain electrode is connected with VDD; NMOS transistor M6Grid and capacitor CL6A first terminal connected to a capacitor CL6The second end is used as the fourth end of the feedback stage, and the NMOS transistor M6Source grounded, NMOS transistor M6Drain connected to NOMS transistor M5A source stage of (a); NMOS transistor M7Grid passing capacitor CR5A capacitor CL6Second terminal, NMOS transistor M7Source and resistor RFRA first terminal connected to a resistor RFRThe second terminal is used as the second terminal of the feedback stage, and the NMOS transistor M7The drain electrode is connected with VDD; NMOS transistor M8Grid passing capacitor CR6A capacitor CL5Second terminal, NMOS transistor M8Source grounded, NMOS transistor M8Drain connected NMOS transistor M7The source stage of (1).
7. A CMOS low distortion low noise amplifier circuit as claimed in claim 6, wherein NMOS transistor M5Grid and NMOS transistor M7The grid is respectively connected with a bias voltage V through a bias resistorbn3NMOS transistor M6Grid and NMOS transistor M8The grid is respectively connected with a bias voltage V through a bias resistorbn4。
8. A CMOS low distortion low noise amplifier circuit according to claim 1, wherein said off-chip components further comprise: off-chip capacitor CbLAnd off-chip capacitor CbR(ii) a Off-chip capacitor CbLOne end of the capacitor is grounded and an off-chip capacitor CbLThe other end is connected with a radio frequency positive input end Vrfin+(ii) a Off-chip capacitor CbROne end of the capacitor is grounded and an off-chip capacitor CbRThe other end is connected with a radio frequency negative input end Vrfin-。
9. The CMOS low distortion and low noise amplifier circuit of claim 8, further comprising cross-coupling capacitor Cntr1And a cross coupling capacitor Cntr2Cross coupling capacitance Cntr1The first end is connected with the negative output end Vout-Cross coupling capacitance Cntr1The second terminal passes through an inductor LLIs connected with a positive input end V of a radio frequency signalrfin+(ii) a Cross coupling capacitance Cntr2The first end is connected with the positive output end Vout+Cross coupling capacitance Cntr2The second terminal passes through an inductor LRIs connected with a negative input end V of a radio frequency signalrfin-。
10. A CMOS low distortion low noise amplifier circuit according to claim 1, wherein said common mode feedback circuit comprises: PMOS transistor M9PMOS transistor M10NMOS transistor M11NMOS transistor M12NMOS transistor M13NMOS transistor M14NMOS transistor M15NMOS transistor M16；
PMOS transistor M9Grid and PMOS transistor M10Gate connected, PMOS transistor M9Source connected to VDD, PMOS transistor M9The drain electrode is connected with the grid electrode of the drain electrode; PMOS transistor M10The source is connected with the VDD in a connecting mode,PMOS transistor M10Drain electrode connected to output end V of common mode feedback circuitfb(ii) a NMOS transistor M11A gate as a first end of the common mode feedback circuit, an NMOS transistor M11Drain connected PMOS transistor M9Drain, NMOS transistor M11Source and NMOS transistor M13The source stage is connected; NMOS transistor M12A gate as a second terminal of the common mode feedback circuit, an NMOS transistor M12Source and NMOS transistor M14Source, NMOS transistor M12Drain connected NMOS transistor M9A drain electrode; NMOS transistor M13The grid is connected with a reference voltage VrefNMOS transistor M13Source connected NMOS transistor M15Drain, NMOS transistor M13Drain and PMOS transistor M10The drain electrodes are connected; NMOS transistor M14The grid is connected with a reference voltage VrefNMOS transistor M14Source connected NMOS transistor M16Drain, NMOS transistor M14Drain and PMOS transistor M10The drain electrodes are connected; NMOS transistor M15Grid electrode is connected with bias voltage VBNMOS transistor M15The source level is grounded;
NMOS transistor M16Grid electrode is connected with bias voltage VBNMOS transistor M16The source is grounded.
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| CN113904635A (en) * | 2021-10-12 | 2022-01-07 | 中国电子科技集团公司第二十四研究所 | High-third-order intermodulation point field effect transistor radio frequency amplifier |
| CN113904635B (en) * | 2021-10-12 | 2023-08-11 | 中国电子科技集团公司第二十四研究所 | High third-order intermodulation point field effect transistor radio frequency amplifier |
| CN114650073A (en) * | 2022-04-15 | 2022-06-21 | 成都信息工程大学 | Linearization correction method and device for radio frequency receiver |
| CN116131770A (en) * | 2023-04-18 | 2023-05-16 | 成都明夷电子科技有限公司 | High-integration-level high-linearity low-noise amplifier |
| CN116131770B (en) * | 2023-04-18 | 2023-07-18 | 成都明夷电子科技有限公司 | High-integration-level high-linearity low-noise amplifier |
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