CN107196611B - Broadband single-ended-to-differential low-noise amplifier - Google Patents
Broadband single-ended-to-differential low-noise amplifier Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45183—Long tailed pairs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/372—Noise reduction and elimination in amplifier
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Abstract
The invention relates to a 0.1-1.2 GHz broadband single-ended-to-differential low-noise amplifier, which comprises: the input end of the input matching stage circuit receives a signal (IN) at the signal input end, generates two paths of signals with opposite phases and outputs the two paths of signals to a noise cancellation stage circuit at the rear stage through a high-pass filter respectively; the noise cancellation stage circuit is provided with three input ends and two output ends, wherein two input ends are connected with two output ends of the input matching stage, the other input end receives a signal (IN) of the signal input end and outputs two differential signals (OUT +/OUT-).
Description
Technical Field
The invention belongs to the technical field of radio frequency integrated circuits, and particularly relates to a 0.1-1.2 GHz broadband single-ended-to-differential low-noise amplifier.
Background
With the development of wireless communication, the role of radio frequency receiving technology in the military and civil fields is becoming more important. The broadband communication system is the development trend of the current wireless communication technology and is also the hot spot of the research at home and abroad[1][2]. Various broadband low noise amplifier design methods exist. The common-gate amplifier utilizes transconductance of an input tube to realize broadband matching, the relation between the noise coefficient and the working frequency and the bandwidth is not large and relatively flat, and the circuit has excellent reverse isolation performance and higher linearity but higher noise coefficient[3]. The global negative feedback structure can alleviate the severe trade-off between impedance matching and noise figure, but the gain is low and multi-stage cascade is needed, which leads to the unstable problem[4]. The resistor parallel feedback common-source amplifier reduces the quality factor of the input end so as to realize bandwidth expansion and gain flattening, but the resistor itself introduces noise, which deteriorates the noise characteristic of the input end[5]. Distributed amplifiers require multiple transistor cascades and large amounts of inductors, or require high quality transmission lines, increase area and power consumption, and increase cost[6]。
In the design of a radio frequency receiver, a kirschner mixer is often used to suppress common mode noise and improve port isolation. However, the signal received from the antenna is a single-ended signal, and the bandpass filter and the low noise amplifier are both single-port structures, so that the balun is required to convert the single-ended signal into a differential signal. The passive balun generally utilizes coaxial lines, microstrip lines and the like for coupling and phase shifting, and has the defect of serious signalLoss, large area and deterioration of system noise. The active balun realizes the function of converting single end into differential by using the operating characteristics of the transistor. There are several common active balun structures. The simplest of these is a single transistor whose source and drain loading is carefully designed to achieve single-turn dual functionality, but this configuration is not suitable for broadband applications due to output parasitics[7]. The structure of the feedback differential pair has the disadvantages that the mismatch of the gain phase depends on the frequency due to the existence of the R/L/C compensation loop, and the power consumption is higher[8]. CS-CG pair, which has low power consumption and good isolation, but large phase error[9]。
The existing broadband low-noise amplifier is difficult to realize good input matching and very low noise at the same time, most of the existing broadband low-noise amplifiers are limited to single-ended input and single-ended output and can only work in cascade connection with a balun structure, the complexity of interstage matching is increased, extra noise is introduced, and the chip area is large.
Reference documents:
【1】 Zika. CMOS wideband low noise amplifier design based on noise cancellation technology [ J ] microelectronics, 2012,42(5): 622-.
【2】Li C F,Chou S C,Lai C M,et al.A feedforward noise and distortioncancellation technique for CMOS broadband LNA-mixer[C]//Solid-State CircuitsConference.IEEE,2014:337-340.
【3】Arshad S,Ramzan R,Muhammad K,et al.A sub-10mW,noise cancelling,wideband LNA for UWB applications[J].AEU-International Journal of Electronicsand Communications,2014,69(1):109-118.
【4】Nejdel A.Flexible Receivers in CMOS for Wireless Communication[J].2015.
【5】Perumana B G,Zhan J H C,Taylor S S,et al.Resistive-Feedback CMOSLow-Noise Amplifiers for Multiband Applications[J].2008,56(5):1218-1225.
【6】Parvizi M,Allidina K,El-Gamal M N.A Sub-mW,Ultra-Low-Voltage,Wideband Low-Noise Amplifier Design Technique[J].IEEE Transactions on VeryLarge Scale Integration Systems,2015,23(6):1111-1122.
【7】Azevedo F,Mendes L,Fialho V,et al.A 5GHz/1.8V CMOS active balunintegrated with LNA[J].2008.
【8】Joo S,Choi T Y,Kim J Y,et al.A 3-to-5GHz UWB LNA with a low-powerbalanced active balun[C]//Radio Frequency Integrated Circuits Symposium,2009.Rfic.IEEE Xplore,2009:303-306.
【9】Yuan S,Zhao J,Li Y.Design and simulation of an improved widebandlow noise amplifier with an active balun[C]//International Conference onAutomatic Control and Artificial Intelligence.2012:786-789.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a broadband single-conversion double-low-noise amplifier capable of working in a frequency band of 0.1-1.2 GHz, apply a noise cancellation technology and an active balun technology to the same circuit, realize good input matching and low noise performance in a broadband at the same time, have a single-ended input differential output function, have a simple structure, can manufacture a small chip, can be realized by a CMOS 0.18um process, and have reproducibility in design. The technical scheme is as follows:
a wideband single-ended to differential low noise amplifier comprising: the input end of the input matching stage circuit receives a signal (IN) at the signal input end, generates two paths of signals with opposite phases and outputs the two paths of signals to a noise cancellation stage circuit at the rear stage through a high-pass filter respectively;
the noise cancellation stage circuit is provided with three input ends and two output ends, wherein two input ends are connected with two output ends of the input matching stage, the other input end receives a signal (IN) of the signal input end and outputs two differential signals (OUT +/OUT-);
the input matching stage circuit comprises: a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4), a fifth transistor (M5); wherein the gate of the first transistor (M1) is connected to the gate of the second transistor (M2), the second terminal of the first capacitor (C1), the first terminal of the first resistor (R1) and the first terminal of the sixth capacitor (C6), respectively;
the drain electrode of the first transistor (M1) is respectively connected with the drain electrode of the second transistor (M2), the second end of the first resistor (R1), the first end of the third capacitor (C3) and the first end of the fourth capacitor (C4);
the source electrode of the second transistor (M2) is respectively connected with the drain electrode of the third transistor (M3) and the second end of the second capacitor (C2);
the gate of the fourth transistor (M4) is respectively connected with the first end of the second resistor (R2) and the second end of the third capacitor (C3);
the drain of the fourth transistor (M4) is connected to the drain of the fifth transistor (M5) and the first terminal of the fifth capacitor (C5), respectively.
The noise cancellation stage circuit comprises: a sixth transistor (M6), a seventh transistor (M7), an eighth transistor (M8), a ninth transistor (M9), a tenth transistor (M10), an eleventh transistor (M11);
wherein the gates of the sixth transistor (M6) are connected to the first terminal of the fifth resistor and the second terminal of the sixth capacitor (C6), respectively;
the drain of the sixth transistor (M6) is connected with the source of the seventh transistor (M7);
the drain electrode of the seventh transistor (M7) is respectively connected with the source electrode of the eighth transistor (M8), the first end of the seventh capacitor (C7) and the first end of the eighth capacitor (C8);
a gate of the eighth transistor (M8) is connected to a second terminal of the third resistor (R3) and a second terminal of the fourth capacitor (C4);
the gate of the ninth transistor (M9) is connected to the first terminal of the sixth resistor (R6) and the second terminal of the seventh capacitor (C7), respectively;
a drain of the ninth transistor (M9) is connected to a source of a tenth transistor (M10);
a drain of the tenth transistor (M10) is connected to a source of the eleventh transistor (M11) and a first end of the ninth capacitor (C9), respectively;
the gate of the eleventh transistor (M11) is connected to the second terminal of the fourth resistor (R4) and the second terminal of the fifth capacitor (C5), respectively.
The gate of the third transistor (M3) and the gate of the fifth transistor (M5) are both connected with a first voltage source (V1);
the second end of the second resistor (R2), the second end of the fifth resistor (R5) and the second end of the sixth resistor (R6) are all connected with a second voltage source (V2);
the source of the third transistor (M3), the source of the fifth transistor (M5), the drain of the eighth transistor (M8), the drain of the eleventh transistor (M11), the first end of the second capacitor (C2), the first end of the third resistor (R3) and the first end of the fourth resistor (R4) are all connected with a third voltage source (V3);
the source of the first transistor (M1), the source of the fourth transistor (M4), the source of the sixth transistor (M6), and the source of the ninth transistor (M9) are all connected to ground.
The signal input end (IN) is connected with a first end of a first capacitor (C1);
a second terminal of the eighth capacitor (C8) is connected to the first signal output terminal (OUT +);
and the second end of the ninth capacitor (C9) is connected with the second signal output end (OUT-).
Compared with the prior art, the technical scheme of the embodiment of the invention has the beneficial effects that:
(1) the invention adopts the noise cancellation technology to realize good input matching and lower noise in the broadband.
(2) The invention combines the active balun technology with the noise cancellation technology, rather than adding a first-stage active balun after a low-noise amplifier, reduces the complexity of interstage matching and avoids the noise caused by the balun and the gain loss caused by poor matching.
(3) The device used in the invention mainly comprises an MOS tube, a resistor and a capacitor, and the whole circuit does not contain an inductor, thereby saving the area of a chip and reducing the cost.
(4) The invention is realized by adopting a deep submicron 0.18umCMOS process, is powered by 1.8V low power supply voltage and has lower power consumption.
(5) The invention adopts mainstream CMOS process, can be integrated with digital baseband circuit of CMOS process on the same chip, and is easy to realize system-on-chip integration.
Drawings
FIG. 1 is a circuit configuration diagram of a low noise amplifier of the present invention;
FIG. 2 is a graph of simulation results of the noise figure of the low noise amplifier of the present invention;
FIG. 3 is a graph of simulation results of the S parameter of the low noise amplifier of the present invention;
FIG. 4 is a graph of simulation results of two port output signal phases for the low noise amplifier of the present invention;
FIG. 5 is a graph of simulation results of two port output signal gains for the low noise amplifier of the present invention;
fig. 6 is a graph of simulation results of the linearity of the low noise amplifier of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, the input matching stage circuit includes: a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4), a fifth transistor (M5);
wherein the gate of the first transistor (M1) is connected to the gate of the second transistor (M2), the second terminal of the first capacitor (C1), the first terminal of the first resistor (R1) and the first terminal of the sixth capacitor (C6), respectively;
the drain electrode of the first transistor (M1) is respectively connected with the drain electrode of the second transistor (M2), the second end of the first resistor (R1), the first end of the third capacitor (C3) and the first end of the fourth capacitor (C4);
the source electrode of the second transistor (M2) is respectively connected with the drain electrode of the third transistor (M3) and the second end of the second capacitor (C2);
the gate of the fourth transistor (M4) is respectively connected with the first end of the second resistor (R2) and the second end of the third capacitor (C3);
the drain of the fourth transistor (M4) is connected to the drain of the fifth transistor (M5) and the first terminal of the fifth capacitor (C5), respectively.
In the embodiment of the invention, the first transistor (M1), the second transistor (M2) and the first resistor (R1) form a current multiplexing structure with parallel feedback of resistors, input impedance is provided by using transconductance of a complementary common-gate transistor, good input matching characteristics in a wider frequency band are ensured, and the transconductance of a single transistor is increased to the sum of the transconductance of the two transistors by the stacked NMOS transistor and PMOS transistor under the same bias current, so that the circuit gain is improved without increasing power consumption. The structure can also improve the robustness of the circuit, and can reduce the influence of parasitic effect, temperature and process change on power gain and input impedance matching. The noise current of the input stage transistors M1 and M2 flows through the first resistor (R1) and the internal resistance of the power supply to form in-phase noise voltages at the X and Y points, and the X and Y points have inverted useful signal voltages due to the inverting amplification characteristics of the common source amplifier, and this difference is the key to noise cancellation. The common source amplifier formed by M4 and M5 is used as one of the inputs of the noise cancellation stage after inverting and amplifying the output of the complementary common gate, and is the basis for forming the single-ended input differential output.
As shown in fig. 1, the noise cancellation stage circuit includes: a sixth transistor (M6), a seventh transistor (M7), an eighth transistor (M8), a ninth transistor (M9), a tenth transistor (M10), an eleventh transistor (M11);
wherein the gates of the sixth transistor (M6) are connected to the first terminal of the fifth resistor and the second terminal of the sixth capacitor (C6), respectively;
the drain of the sixth transistor (M6) is connected with the source of the seventh transistor (M7);
the drain electrode of the seventh transistor (M7) is respectively connected with the source electrode of the eighth transistor (M8), the first end of the seventh capacitor (C7) and the first end of the eighth capacitor (C8);
a gate of the eighth transistor (M8) is connected to a second terminal of the third resistor (R3) and a second terminal of the fourth capacitor (C4);
the gate of the ninth transistor (M9) is connected to the first terminal of the sixth resistor (R6) and the second terminal of the seventh capacitor (C7), respectively;
a drain of the ninth transistor (M9) is connected to a source of a tenth transistor (M10);
a drain of the tenth transistor (M10) is connected to a source of the eleventh transistor (M11) and a first end of the ninth capacitor (C9), respectively;
the gate of the eleventh transistor (M11) is connected to the second terminal of the fourth resistor (R4) and the second terminal of the fifth capacitor (C5), respectively.
In the embodiment of the invention, the source follower M8 amplifies the Y-point noise voltage in phase, the M6 and M7 cascode amplifiers amplify the X-point noise voltage signal in opposite phase, the M8 source electrodes are superposed, and the noise can be offset at the output end OUT +; similarly, the source follower M11 amplifies the Z point noise voltage in phase, the M9 and M10 cascode amplifiers amplify the noise voltage at the drain of M7 in opposite phase, and the noise is superposed at the source of M8 and can be cancelled at the output end OUT-. Meanwhile, for a useful signal, the Y-point signal is amplified in phase by the M8 and is opposite to the phase of the X point, and the X point is amplified in phase by the M6 and the M7 cascode amplifier, so that the amplification is enhanced at the output end OUT +; m11 amplifies the Z-point signal in phase and thus in phase with point X, and M9 and M10 cascode amplifiers amplify the output signals of M6 and M7 cascode amplifiers in phase and thus in phase with point X, are boosted at output OUT-, and in phase opposition to the signal at output OUT +. M7 and M10 can restrain the Miller effect, improve reverse isolation, increase circuit stability, and make the input/output impedance matching network not influence each other. The input stage noise can be respectively counteracted at the two ports and a differential output signal can be formed by only carefully designing the transconductance values of the MOS tubes. Meanwhile, because the transconductance of M8 and M11 provides output impedance, output matching can be realized in a wider frequency band range, and the gain flatness of the circuit system is increased.
In an embodiment of the invention, the gate of the third transistor (M3) and the gate of the fifth transistor (M5) are both connected to a first voltage source (V1); the second end of the second resistor (R2), the second end of the fifth resistor (R5) and the second end of the sixth resistor (R6) are all connected with a second voltage source (V2); the source of the third transistor (M3), the source of the fifth transistor (M5), the drain of the eighth transistor (M8), the drain of the eleventh transistor (M11), the first end of the second capacitor (C2), the first end of the third resistor (R3) and the first end of the fourth resistor (R4) are all connected with a third voltage source (V3); the source of the first transistor (M1), the source of the fourth transistor (M4), the source of the sixth transistor (M6), and the source of the ninth transistor (M9) are all connected to ground. The signal input end (IN) is connected with a first end of a first capacitor (C1); a second terminal of the eighth capacitor (C8) is connected to the first signal output terminal (OUT +); and the second end of the ninth capacitor (C9) is connected with the second signal output end (OUT-).
The circuit is subjected to simulation verification by using a Cadence RF spectrum by adopting a TSMC CMOS 0.18um process.
FIG. 2 is a simulation result of the noise factor of the 0.1-1.2 GHz broadband low noise amplifier. Therefore, the noise coefficient is 3.2-4.1 dB in the frequency band range of 0.1-1.2 GHz, which shows that the low noise amplifier has good noise coefficient in the whole frequency band.
FIG. 3 shows the simulation result of the S parameter of the 0.1-1.2 GHz broadband low noise amplifier. Therefore, S is within the frequency band range of 0.1-1.2 GHz11<-15，S22<19, showing that the low noise amplifier of the invention realizes good input and output matching in the whole frequency band; s12<44, showing that the low noise amplifier of the invention has good reverse isolation performance; s21The maximum value is 13.5dB, which shows that the low noise amplifier of the invention has higher gain.
FIG. 4 is a simulation result of the phase and gain of two output ports of the 0.1-1.2 GHz broadband low noise amplifier. Therefore, in the frequency band range of 0.1-1.2 GHz, the phase error is 2.5 degrees, the output signal is proved to have good differential characteristics, and the LNA can realize the function of a balun.
FIG. 5 is a simulation result of the linearity of the 0.1-1.2 GHz broadband low noise amplifier port. It can be seen that the input 1dB compression point is-8 dBm at a frequency of 700M, indicating that the low noise amplifier of the present invention has good linearity.
FIG. 6 shows the stability factor of the 0.1-1.2 GHz broadband low noise amplifier. It can be seen that Kf> 23, indicating unconditional stability of the low noise amplifier of the present invention.
The invention adopts a current multiplexing structure with parallel feedback of resistors, utilizes the transconductance of the transistor to provide input impedance, ensures that the transistor has good input matching characteristic in a wider frequency band, and increases the transconductance of a single transistor to the sum of the transconductances of two transistors by the stacked NMOS transistor and the PMOS transistor under the same bias current, thereby improving the circuit gain without increasing the power consumption. The structure can also improve the robustness of the circuit, and can reduce the influence of parasitic effect, temperature and process change on power gain and input impedance matching. A primary common source amplifier is added behind an input matching stage to increase one path of inverted signal output, which is the basis for realizing single-end input and double-end output. The noise cancellation stage is based on the combination of the source follower and the cascode, cancels the noise of the input matching stage at the output and reinforces the useful signal, forming differential signals with opposite phases and equal amplitudes, and the transconductance of the source follower provides output impedance to have good output matching in a wide frequency band range.
The above embodiments are merely illustrative of the circuit structure of the present invention and are not intended to be limiting. Moreover, exemplary embodiments in accordance with the above-described configurations may be understood and implemented by those skilled in the art; the circuit structures described in the foregoing embodiments may be modified, or some of them may be replaced with equivalents; and these modifications or substitutions do not make the essence of the corresponding circuit configuration depart from the essential features of the technical solutions of the embodiments of the present invention. The scope of the invention should be construed in accordance with the attached claims.
Claims (3)
1. A wideband single-ended to differential low noise amplifier comprising: the input end of the input matching stage circuit receives a signal (IN) at the signal input end, generates two paths of signals with opposite phases and outputs the two paths of signals to a noise cancellation stage circuit at the rear stage through a high-pass filter respectively;
the noise cancellation stage circuit is provided with three input ends and two output ends, wherein two input ends are connected with two output ends of the input matching stage, the other input end receives a signal (IN) of the signal input end and outputs two differential signals (OUT +/OUT-);
the input matching stage circuit comprises: a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4), a fifth transistor (M5); wherein the gate of the first transistor (M1) is connected to the gate of the second transistor (M2), the second terminal of the first capacitor (C1), the first terminal of the first resistor (R1) and the first terminal of the sixth capacitor (C6), respectively;
the drain electrode of the first transistor (M1) is respectively connected with the drain electrode of the second transistor (M2), the second end of the first resistor (R1), the first end of the third capacitor (C3) and the first end of the fourth capacitor (C4);
the source electrode of the second transistor (M2) is respectively connected with the drain electrode of the third transistor (M3) and the second end of the second capacitor (C2);
the gate of the fourth transistor (M4) is respectively connected with the first end of the second resistor (R2) and the second end of the third capacitor (C3);
the drain electrode of the fourth transistor (M4) is respectively connected with the drain electrode of the fifth transistor (M5) and the first end of the fifth capacitor (C5);
the noise cancellation stage circuit comprises: a sixth transistor (M6), a seventh transistor (M7), an eighth transistor (M8), a ninth transistor (M9), a tenth transistor (M10), an eleventh transistor (M11);
wherein the gates of the sixth transistor (M6) are connected to the first terminal of the fifth resistor and the second terminal of the sixth capacitor (C6), respectively;
the drain of the sixth transistor (M6) is connected with the source of the seventh transistor (M7);
the drain electrode of the seventh transistor (M7) is respectively connected with the source electrode of the eighth transistor (M8), the first end of the seventh capacitor (C7) and the first end of the eighth capacitor (C8); a gate of the seventh transistor (M7) is connected to a gate of the tenth transistor (M10);
a gate of the eighth transistor (M8) is connected to a second terminal of the third resistor (R3) and a second terminal of the fourth capacitor (C4);
the gate of the ninth transistor (M9) is connected to the first terminal of the sixth resistor (R6) and the second terminal of the seventh capacitor (C7), respectively;
a drain of the ninth transistor (M9) is connected to a source of a tenth transistor (M10);
a drain of the tenth transistor (M10) is connected to a source of the eleventh transistor (M11) and a first end of the ninth capacitor (C9), respectively;
the gate of the eleventh transistor (M11) is respectively connected with the second end of the fourth resistor (R4) and the second end of the fifth capacitor (C5);
the gate of the third transistor (M3) and the gate of the fifth transistor (M5) are both connected with a first voltage source (V1);
the second end of the second resistor (R2), the second end of the fifth resistor (R5) and the second end of the sixth resistor (R6) are all connected with a second voltage source (V2);
the source of the third transistor (M3), the source of the fifth transistor (M5), the drain of the eighth transistor (M8), the drain of the eleventh transistor (M11), the first end of the second capacitor (C2), the first end of the third resistor (R3) and the first end of the fourth resistor (R4) are all connected with a third voltage source (V3);
the source of the first transistor (M1), the source of the fourth transistor (M4), the source of the sixth transistor (M6) and the source of the ninth transistor (M9) are all connected with the ground terminal;
the signal input end (IN) is connected with a first end of a first capacitor (C1);
a second terminal of the eighth capacitor (C8) is connected to the first signal output terminal (OUT +);
and the second end of the ninth capacitor (C9) is connected with the second signal output end (OUT-).
2. The amplifier of claim 1, wherein the second transistor (M2), the third transistor (M3), and the fifth transistor (M5) are all PMOS transistors, and the rest are all NMOS transistors.
3. Amplifier according to claim 1, characterized in that the third voltage source (V3) provides a dc bias voltage.
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| CN109361363A (en) * | 2018-09-11 | 2019-02-19 | 天津大学 | A kind of broadband fully differential low-noise amplifier |
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| CN113131883B (en) * | 2019-12-30 | 2022-10-28 | 澜至电子科技（成都）有限公司 | Low noise amplifier |
| CN112803899B (en) * | 2020-12-28 | 2023-10-03 | 东南大学 | Noise-cancellation-based on-chip inductance-free single-to-double low-noise amplifier |
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