CN107196611A - Broadband single-ended transfer difference low-noise amplifier - Google Patents

Abstract

The present invention relates to one kind 0.1~1.2GHz broadbands single-ended transfer difference low-noise amplifier, including：Matching stage circuit and noise cancellation level circuit are inputted, the input matching stage circuit, its input receives the signal (IN) of signal input part, produces the two paths of signals of opposite in phase, be output to the noise cancellation level circuit of rear class by high-pass filter respectively；The noise cancellation level circuit, noise cancellation level circuit has three inputs, the two-way output of two output ends, wherein two-way input connection input matching stage, another road input receives the signal (IN) of signal input part, output two paths of differential signals (OUT+/OUT).

Description

Wideband Single-Ended-to-Differential Low Noise Amplifier

technical field

The invention belongs to the technical field of radio frequency integrated circuits, and in particular relates to a 0.1-1.2 GHz broadband single-end-to-differential low-noise amplifier.

Background technique

With the development of wireless communication, the role of radio frequency receiving technology in military and civilian fields is becoming more and more important. Broadband communication system is the development trend of today's wireless communication technology, and it is also a hot research topic at home and abroad ^[1][2] . There are several approaches to wideband LNA design. The common-gate amplifier uses the transconductance of the input tube to achieve broadband matching. The noise figure has little relationship with the operating frequency and bandwidth and is relatively flat. The circuit has excellent reverse isolation performance and high linearity, but the noise figure is high ^{[3 ]} . The global negative feedback structure can ease the severe trade-off relationship between impedance matching and noise figure, but the gain is low and requires multi-stage cascading, which will lead to unstable problems ^[4] . Resistor parallel feedback common source amplifier reduces the quality factor of the input to achieve bandwidth expansion and gain flattening, but the resistor itself will introduce noise, which will deteriorate the noise characteristics of the input ^[5] . Distributed amplifiers require multi-transistor cascading and a large amount of inductance, or high-quality transmission lines, which increase the area and power consumption, and increase the cost ^[6] .

In the design of radio frequency receivers, in order to suppress common mode noise and improve port isolation, Gilbert mixers are often used. However, the signal received from the antenna is a single-ended signal, and the general band-pass filter and low-noise amplifier are single-port structures, so a balun is required to convert the single-ended signal into a differential signal. Passive baluns generally use coaxial lines, microstrip lines, etc. for coupling and phase shifting. The disadvantages are serious signal loss, large area, and worsening system noise. The active balun is to use the working characteristics of the transistor to realize the function of single-ended conversion. There are several common active balun structures. The simplest of these is a single transistor, which can achieve single-turn dual-function by carefully designing its source and drain loads, but due to output parasitics, this structure is not suitable for broadband applications ^[7] . The disadvantage of the structure of the feedback differential pair is that the mismatch of the gain phase depends on the frequency due to the existence of the R/L/C compensation loop, and the power consumption is high ^[8] . CS-CG pair, it has lower power consumption and good isolation, but the phase error is larger ^[9] .

Existing broadband low noise amplifiers are difficult to achieve good input matching and low noise at the same time, and most of them are limited to single-ended input and single-ended output and can only work in cascade with the balun structure, which will increase the complexity of inter-stage matching , introduce additional noise, and the chip area is larger.

references:

【1】Qi Kai. Design of CMOS Broadband Low Noise Amplifier Based on Noise Cancellation Technology[J]. Microelectronics, 2012,42(5):622-626.

【2】Li C F, Chou S C, Lai C M, et al. A feedforward noise and distortion cancellation technique for CMOS broadband LNA-mixer[C]//Solid-State Circuits Conference.IEEE,2014:337-340.

【3】Arshad S, Ramzan R, Muhammad K, et al.A sub-10mW, noise canceling, wideband LNA for UWB applications[J].AEU-International Journal of Electronics and Communications,2014, 69(1):109-118 .

【4】Nejdel A.Flexible Receivers in CMOS for Wireless Communication[J].2015.

【5】Perumana B G, Zhan J H C, Taylor S S, et al.Resistive-Feedback CMOSLow-Noise Amplifiers for Multiband Applications[J].2008,56(5):1218-1225.

【6】Parvizi M, Allidina K, El-Gamal M N.A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique [J]. IEEE Transactions on VeryLarge Scale Integration Systems, 2015, 23(6): 1111-1122.

【7】Azevedo F, Mendes L, Fialho V, et al. A 5GHz/1.8V CMOS active balun integrated with LNA[J].2008.

【8】Joo S, Choi T Y, Kim J Y, et al.A 3-to-5GHz UWB LNA with a low-powerbalanced active balun[C]//Radio Frequency Integrated Circuits Symposium,2009.Rfic.IEEE Xplore,2009: 303-306.

【9】Yuan S, Zhao J, Li Y. Design and simulation of an improved widebandlow noise amplifier with an active balun[C]//International Conference on Automatic Control and Artificial Intelligence.2012:786-789.

Contents of the invention

The technical problem to be solved by the present invention is to provide a broadband single-rotation dual low-noise amplifier that can work in the 0.1-1.2GHz frequency band, and apply noise cancellation technology and active balun technology to the same circuit to achieve good performance in broadband at the same time. It has excellent input matching and low noise performance, and has the function of single-ended input and differential output. It has a simple structure and can be made into a smaller chip. It can be realized in a CMOS 0.18um process, and the design is reproducible. The technical scheme is as follows:

A wideband single-ended to differential low-noise amplifier, comprising: an input matching stage circuit and a noise canceling stage circuit, the input matching stage circuit receives a signal (IN) from a signal input end at its input, and generates two signals with opposite phases, output to the noise cancellation stage circuit of the subsequent stage through the high-pass filter;

The noise canceling stage circuit, the noise canceling stage circuit has three input terminals and two output terminals, two of which are connected to the two outputs of the input matching stage, the other input receives the signal (IN) of the signal input terminal, and two outputs Differential signal (OUT+/OUT-);

The input matching stage circuit includes: a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4), and a fifth transistor (M5); wherein, the first transistor The gate of (M1) is respectively connected with the gate of the second transistor (M2), the second end of the first capacitor (C1), the first end of the first resistor (R1) and the first end of the sixth capacitor (C6). connect;

The drain of the first transistor (M1) is respectively connected to the drain of the second transistor (M2), the second end of the first resistor (R1), the first end of the third capacitor (C3) and the fourth capacitor ( The first end of C4) is connected;

The source of the second transistor (M2) is respectively connected to the drain of the third transistor (M3) and the second end of the second capacitor (C2);

The gate of the fourth transistor (M4) is respectively connected to the first end of the second resistor (R2) and the second end of the third capacitor (C3);

The drain of the fourth transistor (M4) is respectively connected to the drain of the fifth transistor (M5) and the first end of the fifth capacitor (C5).

The noise cancellation stage circuit includes: a sixth transistor (M6), a seventh transistor (M7), an eighth transistor (M8), a ninth transistor (M9), a tenth transistor (M10), and an eleventh transistor (M11) ;

Wherein the gate of the sixth transistor (M6) is respectively connected to the first end of the fifth resistor and the second end of the sixth capacitor (C6);

The drain of the sixth transistor (M6) is connected to the source of the seventh transistor (M7);

The drain of the seventh transistor (M7) is respectively connected to the source of the eighth transistor (M8), the first end of the seventh capacitor (C7) and the first end of the eighth capacitor (C8);

The gate of the eighth transistor (M8) is connected to the second end of the third resistor (R3) and the second end of the fourth capacitor (C4);

The gate of the ninth transistor (M9) is respectively connected to the first end of the sixth resistor (R6) and the second end of the seventh capacitor (C7);

The drain of the ninth transistor (M9) is connected to the source of the tenth transistor (M10);

The drain of the tenth transistor (M10) is respectively connected to the source of the eleventh transistor (M11) and the first end of the ninth capacitor (C9);

The gate of the eleventh transistor (M11) is respectively connected to the second end of the fourth resistor (R4) and the second end of the fifth capacitor (C5).

Both the gate of the third transistor (M3) and the gate of the fifth transistor (M5) are connected to the first voltage source (V1);

The second end of the second resistor (R2), the second end of the fifth resistor (R5) and the second end of the sixth resistor (R6) are all connected to the second voltage source (V2);

The source of the third transistor (M3), the source of the fifth transistor (M5), the drain of the eighth transistor (M8), the drain of the eleventh transistor (M11), the second capacitor (C2) The first end, the first end of the third resistor (R3) and the first end of the fourth resistor (R4) are all connected to the third voltage source (V3);

The sources of the first transistor (M1), the fourth transistor (M4), the sixth transistor (M6) and the ninth transistor (M9) are all connected to the ground terminal.

The signal input terminal (IN) is connected to the first terminal of the first capacitor (C1);

The second end of the eighth capacitor (C8) is connected to the first signal output end (OUT+);

The second end of the ninth capacitor (C9) is connected to the second signal output end (OUT-).

Compared with the prior art, the beneficial effects of the technical solutions of the embodiments of the present invention are:

(1) The present invention adopts noise canceling technology to realize good input matching and lower noise in broadband.

(2) The present invention combines the active balun technology with the noise canceling technology, instead of adding an active balun after the low-noise amplifier, reducing the complexity of inter-stage matching, and avoiding the noise caused by the balun Loss of gain due to noise and poor matching.

(3) The devices used in the present invention mainly include MOS transistors, resistors and capacitors, and the overall circuit does not contain inductors, thereby saving chip area and reducing costs.

(4) The present invention is realized by using a deep submicron 0.18um CMOS process, powered by a low power supply voltage of 1.8V, and its power consumption is relatively low.

(5) The implementation of the present invention adopts the mainstream CMOS technology, and can be integrated on the same chip with the common digital baseband circuit using the CMOS technology, so that system-on-chip integration can be easily realized.

Description of drawings

Fig. 1 is the circuit structure diagram of low noise amplifier of the present invention;

Fig. 2 is the simulation result figure of the noise figure of the low noise amplifier of the present invention;

Fig. 3 is the simulation result figure of the S parameter of low noise amplifier of the present invention;

Fig. 4 is the simulation result figure of the two-port output signal phase of the low noise amplifier of the present invention;

Fig. 5 is the simulation result figure of the two-port output signal gain of the low noise amplifier of the present invention;

Fig. 6 is a simulation result diagram of the linearity of the low noise amplifier of the present invention.

detailed description

In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

As shown in Figure 1, the input matching stage circuit includes: a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4), and a fifth transistor (M5);

Wherein, the gate of the first transistor (M1) is respectively connected with the gate of the second transistor (M2), the second terminal of the first capacitor (C1), the first terminal of the first resistor (R1) and the sixth capacitor The first end of (C6) is connected;

The drain of the first transistor (M1) is respectively connected to the drain of the second transistor (M2), the second end of the first resistor (R1), the first end of the third capacitor (C3) and the fourth capacitor ( The first end of C4) is connected;

The source of the second transistor (M2) is respectively connected to the drain of the third transistor (M3) and the second end of the second capacitor (C2);

The gate of the fourth transistor (M4) is respectively connected to the first end of the second resistor (R2) and the second end of the third capacitor (C3);

The drain of the fourth transistor (M4) is respectively connected to the drain of the fifth transistor (M5) and the first end of the fifth capacitor (C5).

In the embodiment of the present invention, the first transistor (M1), the second transistor (M2) and the first resistor (R1) form a current multiplexing structure with parallel feedback of resistors, and the transconductance of complementary common-gate transistors is used to provide input impedance, ensuring It has good input matching characteristics in a wide frequency band. Under the same bias current, the stacked NMOS transistor and PMOS transistor increase the transconductance of a single transistor to the sum of the transconductance of the two transistors without increasing power consumption. increase the circuit gain. The structure can also improve the robustness of the circuit, which can reduce the influence of parasitic effects, temperature and process variations on power gain and input impedance matching. The noise current of the input-stage transistors M1 and M2 flows through the first resistor (R1) and the internal resistance of the power supply to form the same-phase noise voltage at the X and Y points, and at the same time, due to the inverting amplification characteristic of the common-source amplifier, the X and Y points have an inversion useful signal voltage, this difference is the key to noise cancellation. The common-source amplifier composed of M4 and M5 inverts and amplifies the output of the complementary common gate as one of the inputs of the noise canceling stage, which is the basis for forming a single-ended input and a differential output.

As shown in Figure 1, the noise cancellation stage circuit includes: a sixth transistor (M6), a seventh transistor (M7), an eighth transistor (M8), a ninth transistor (M9), a tenth transistor (M10), and a sixth transistor (M10). Eleven transistors (M11);

Wherein the gate of the sixth transistor (M6) is respectively connected to the first end of the fifth resistor and the second end of the sixth capacitor (C6);

The drain of the sixth transistor (M6) is connected to the source of the seventh transistor (M7);

The drain of the seventh transistor (M7) is respectively connected to the source of the eighth transistor (M8), the first end of the seventh capacitor (C7) and the first end of the eighth capacitor (C8);

The gate of the eighth transistor (M8) is connected to the second end of the third resistor (R3) and the second end of the fourth capacitor (C4);

The gate of the ninth transistor (M9) is respectively connected to the first end of the sixth resistor (R6) and the second end of the seventh capacitor (C7);

The drain of the ninth transistor (M9) is connected to the source of the tenth transistor (M10);

The drain of the tenth transistor (M10) is respectively connected to the source of the eleventh transistor (M11) and the first end of the ninth capacitor (C9);

The gate of the eleventh transistor (M11) is respectively connected to the second end of the fourth resistor (R4) and the second end of the fifth capacitor (C5).

In the embodiment of the present invention, the source follower M8 amplifies the noise voltage at point Y in phase, the cascode amplifiers M6 and M7 amplify the noise voltage signal at point X in reverse phase, and superimposes it at the source of M8, and the noise can be generated at the output terminal OUT+ Similarly, the source follower M11 amplifies the noise voltage at point Z in phase, and the M9 and M10 cascode amplifiers invert and amplify the noise voltage at the drain of M7 and superimpose it at the source of M8, and the noise can be output at the output offset at OUT-. At the same time, for the useful signal, M8 amplifies the signal at point Y in phase so that it is opposite to point X, M6 and M7 cascode amplifiers amplify point X in reverse, and strengthen it at the output terminal OUT+; M11 amplifies the signal at point Z in phase so that In the same phase as point X, the M9 and M10 cascode amplifiers invert and amplify the output signals of the M6 and M7 cascode amplifiers so that they are in the same phase as point X, and are strengthened at the output terminal OUT-, and are connected to the output terminal OUT+ The signal phase is reversed. M7 and M10 can suppress the Miller effect, improve reverse isolation, increase circuit stability, and make the input and output impedance matching networks independent of each other. As long as the transconductance value of the MOS tube is carefully designed, the noise of the input stage can be canceled at the two ports and a differential output signal can be formed. At the same time, since the transconductance of M8 and M11 provides output impedance, output matching can be realized in a wide frequency range, which increases the gain flatness of the circuit system.

In an embodiment of the present invention, both the gate of the third transistor (M3) and the gate of the fifth transistor (M5) are connected to the first voltage source (V1); the second of the second resistor (R2) end, the second end of the fifth resistor (R5) and the second end of the sixth resistor (R6) are all connected to the second voltage source (V2); the source of the third transistor (M3), the fifth transistor ( M5), the drain of the eighth transistor (M8), the drain of the eleventh transistor (M11), the first end of the second capacitor (C2), the first end of the third resistor (R3) and the first end of the third resistor (R3). The first ends of the four resistors (R4) are all connected to the third voltage source (V3); the source of the first transistor (M1), the source of the fourth transistor (M4), and the source of the sixth transistor (M6) Both the pole and the source of the ninth transistor (M9) are connected to the ground terminal. The signal input terminal (IN) is connected to the first terminal of the first capacitor (C1); the second terminal of the eighth capacitor (C8) is connected to the first signal output terminal (OUT+); the ninth capacitor (C9) The second terminal of is connected to the second signal output terminal (OUT-).

In this paper, TSMC CMOS 0.18um process is used, and Cadence RF Specter is used to simulate and verify the circuit.

Fig. 2 is the simulation result of the noise figure of the 0.1-1.2 GHz broadband low noise amplifier of the present invention. It can be seen that, in the range of 0.1-1.2 GHz frequency band, the noise figure is 3.2-4.1 dB, indicating that the low noise amplifier of the present invention has a good noise figure in the whole frequency band.

Fig. 3 is the simulation result of S parameters of the 0.1-1.2 GHz broadband low noise amplifier of the present invention. It can be seen that, within the frequency range of 0.1-1.2 GHz, S ₁₁ <-15, S ₂₂ <-19, indicating that the low noise amplifier of the present invention has achieved good input-output matching in the entire frequency band; S ₁₂ <- 44, indicating that the low noise amplifier of the present invention has good reverse isolation performance; the maximum value of S ₂₁ is 13.5dB, indicating that the low noise amplifier of the present invention has relatively high gain.

Fig. 4 is the simulation result of the phase and gain of the two output ports of the 0.1-1.2 GHz broadband low noise amplifier of the present invention. It can be seen that, in the 0.1-1.2GHz frequency band, the phase error is 2.5°, which proves that the output signal has good differential characteristics, and the LNA can realize the function of the balun.

Fig. 5 is the simulation result of the linearity of the 0.1-1.2 GHz broadband low noise amplifier port of the present invention. It can be seen that the input 1dB compression point is -8dBm when the frequency is 700M, indicating that the low noise amplifier of the present invention has good linearity.

Fig. 6 is the stability factor of the 0.1-1.2GHz broadband low noise amplifier of the present invention. It can be seen that K _f >23, indicating that the low noise amplifier of the present invention has unconditional stability.

The present invention adopts the current multiplexing structure of parallel feedback of resistors, uses the transconductance of transistors to provide input impedance, and ensures good input matching characteristics in a wide frequency band, and under the same bias current, the stacked NMOS tube and PMOS tube Increase the transconductance of a single transistor to the sum of the transconductance of two transistors, and increase the circuit gain without increasing power consumption. The structure can also improve the robustness of the circuit, which can reduce the influence of parasitic effects, temperature and process variations on power gain and input impedance matching. Adding a common-source amplifier after the input matching stage to increase an inverted signal output is the basis for realizing single-ended input and double-ended output. The noise cancellation stage is based on the combination of the source follower and the common source common gate, and cancels the noise of the input matching stage at the output end and strengthens the useful signal to form a differential signal with opposite phase and equal amplitude, and the transconductance of the source follower The output impedance is provided for good output matching over a wide frequency band.

The above embodiments are only used to illustrate the circuit structure of the present invention, not to limit it. In addition, the exemplary implementations according to the above configurations can be understood and implemented by those skilled in the art; the circuit structures described in the foregoing embodiments can be modified, or some of the circuit structures can be equivalently replaced; and these modifications or replacements, The essence of the corresponding circuit structure does not deviate from the basic features of the technical solutions of the various embodiments of the present invention. The scope of the present invention should be construed based on the claims.

Claims (3)

1. A wideband single-ended to differential low-noise amplifier, comprising: an input matching stage circuit and a noise canceling stage circuit, and the input matching stage circuit, whose input terminal receives the signal (IN) of the signal input terminal, produces two opposite phase circuits Signals are respectively output to the noise canceling stage circuit of the subsequent stage through the high-pass filter; The noise canceling stage circuit, the noise canceling stage circuit has three input terminals and two output terminals, two of which are connected to the two outputs of the input matching stage, the other input receives the signal (IN) of the signal input terminal, and two outputs Differential signal (OUT+/OUT-); The input matching stage circuit includes: a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4), and a fifth transistor (M5); wherein, the first transistor The gate of (M1) is respectively connected with the gate of the second transistor (M2), the second end of the first capacitor (C1), the first end of the first resistor (R1) and the first end of the sixth capacitor (C6). connect; The drain of the first transistor (M1) is respectively connected to the drain of the second transistor (M2), the second end of the first resistor (R1), the first end of the third capacitor (C3) and the fourth capacitor ( The first end of C4) is connected; The source of the second transistor (M2) is respectively connected to the drain of the third transistor (M3) and the second end of the second capacitor (C2); The gate of the fourth transistor (M4) is respectively connected to the first end of the second resistor (R2) and the second end of the third capacitor (C3); The drain of the fourth transistor (M4) is respectively connected to the drain of the fifth transistor (M5) and the first end of the fifth capacitor (C5). The noise cancellation stage circuit includes: a sixth transistor (M6), a seventh transistor (M7), an eighth transistor (M8), a ninth transistor (M9), a tenth transistor (M10), and an eleventh transistor (M11) ; Wherein the gate of the sixth transistor (M6) is respectively connected to the first end of the fifth resistor and the second end of the sixth capacitor (C6); The drain of the sixth transistor (M6) is connected to the source of the seventh transistor (M7); The drain of the seventh transistor (M7) is respectively connected to the source of the eighth transistor (M8), the first end of the seventh capacitor (C7) and the first end of the eighth capacitor (C8); The gate of the eighth transistor (M8) is connected to the second end of the third resistor (R3) and the second end of the fourth capacitor (C4); The gate of the ninth transistor (M9) is respectively connected to the first end of the sixth resistor (R6) and the second end of the seventh capacitor (C7); The drain of the ninth transistor (M9) is connected to the source of the tenth transistor (M10); The drain of the tenth transistor (M10) is respectively connected to the source of the eleventh transistor (M11) and the first end of the ninth capacitor (C9); The gate of the eleventh transistor (M11) is respectively connected to the second end of the fourth resistor (R4) and the second end of the fifth capacitor (C5). Both the gate of the third transistor (M3) and the gate of the fifth transistor (M5) are connected to the first voltage source (V1); The second end of the second resistor (R2), the second end of the fifth resistor (R5) and the second end of the sixth resistor (R6) are all connected to the second voltage source (V2); The source of the third transistor (M3), the source of the fifth transistor (M5), the drain of the eighth transistor (M8), the drain of the eleventh transistor (M11), the second capacitor (C2) The first end, the first end of the third resistor (R3) and the first end of the fourth resistor (R4) are all connected to the third voltage source (V3); The sources of the first transistor (M1), the fourth transistor (M4), the sixth transistor (M6) and the ninth transistor (M9) are all connected to the ground terminal. The signal input terminal (IN) is connected to the first terminal of the first capacitor (C1); The second terminal of the eighth capacitor (C8) is connected to the first signal output terminal (OUT+); The second end of the ninth capacitor (C9) is connected to the second signal output end (OUT-). 2. The amplifier according to claim 1, characterized in that, the second transistor (M2), the third transistor (M3) and the fifth transistor (M5) are all PMOS transistors, and the rest are all NMOS transistors. 3. The amplifier according to claim 1, characterized in that the third voltage source (V3) provides a DC bias voltage.