CN107733375B - Ultra-wideband low-noise amplifier - Google Patents
Ultra-wideband low-noise amplifier Download PDFInfo
- Publication number
- CN107733375B CN107733375B CN201711068702.3A CN201711068702A CN107733375B CN 107733375 B CN107733375 B CN 107733375B CN 201711068702 A CN201711068702 A CN 201711068702A CN 107733375 B CN107733375 B CN 107733375B
- Authority
- CN
- China
- Prior art keywords
- bias
- tube
- amplifying
- ultra
- feedback
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/372—Noise reduction and elimination in amplifier
Abstract
The invention discloses an ultra-wideband low-noise amplifier, which mainly solves the problem of poor noise and linearity performance in the prior art. The device adopts a two-stage cascade structure, and the two stages are coupled by a capacitor C3. The second-stage amplifying circuit adopts a basic common source circuit with a parallel peak structure; the input-output of the first-stage amplifying circuit is connected with a series circuit consisting of a feedback MOS tube M3 and a feedback coupling capacitor C2, and is used for providing broadband matching and improving linearity, and the source electrode of the feedback MOS tube M3 is connected with a bias MOS tube M4 which is used for providing bias current for the feedback MOS tube M3; an auxiliary transconductance amplifier G is connected between the input end of the first-stage amplifying circuit and the output end of the second-stage amplifying circuit. The invention can partially or completely eliminate the noise generated by partial components in the first-stage amplifying circuit, improves the overall noise performance of the ultra-wideband low-noise amplifier, and can be used for ultra-wideband wireless communication.
Description
Technical Field
The invention relates to the technical field of wireless communication, in particular to an ultra-wideband low-noise amplifier which is mainly used for ultra-wideband wireless communication.
Background
The ultra-wideband low-noise amplifier is generally used as a first module of an ultra-wideband radio frequency front end and is responsible for amplifying weak signal power received on an antenna for a post-stage circuit, and meanwhile, smaller noise power needs to be introduced, and the performance of the ultra-wideband low-noise amplifier has important influence on the performance of the whole system. The signal received on the antenna is generally a modulated signal, the frequency of the signal is in the range of radio frequency or microwave, and it can be known through the theory of high frequency circuit that the degree of reflection of the input signal has a close relationship with the degree of matching of the input impedance of the antenna and the low noise amplifier, that is:
where the reflection coefficient of the incident signal is represented, Rin represents the input impedance of the low noise amplifier, and Rs represents the characteristic impedance of the antenna.
Signal power loss due to reflections between the antenna and the low noise amplifier can in severe cases corrupt the signal and degrade communication quality. In order to solve this problem, a common method is to add a degeneration resistor between the gate and the drain of the amplifier tube, so that the impedance seen from the input end of the amplifier has a proper real component, and then convert the impedance to 50 ohms by means of impedance matching, or use a common-gate amplification mode. However, the use of the degeneration resistor complicates the matching network, and in order to obtain an input impedance of approximately 50 ohms in the entire communication band, passive elements such as inductors and capacitors need to be added, which sacrifices the chip area and cannot further improve the linearity, the use of common-gate input matching limits the gain and noise performance of the single-stage amplifier, and for a simple common-gate circuit, the noise factor of the amplifier is greater than or equal to 3dB when matching is implemented at the input terminal.
It is known from the cascaded noise theory that the noise figure of the final stage, i.e. the low noise amplifier, plays a decisive role in the noise of the whole system, because the noise is finally present at the output end through the amplification of the whole gain of the receiving chain, and the noise of other parts is only amplified through the gain of the partial block of the receiving chain. Therefore, the noise contribution of the low noise amplifier is further reduced by the technical means, and the method is very effective for improving the overall performance of the receiving chain. Meanwhile, the gain of the low noise amplifier is high enough to reduce the influence of the noise of the later stage equivalent to the input end as much as possible; the gain-frequency characteristic is sufficiently flat to minimize distortion of the time domain signal.
As wireless communication systems become more and more popular, resulting in the entire communication environment becoming extremely noisy, the antenna receives the useful signal and also receives other noise or communication signals in the passband, and if the interference is large enough, the normal operation of the low noise amplifier is affected, so that the amplification capability of the useful signal is lost. Another common situation is: considering the case that the transmitting path and the receiving path share the antenna through the duplexer, assuming that the power of the signal to be received is about-80 dBm, the output power of the transmitting terminal power amplifier is 30dBm, and the isolation characteristic between the transmitting port and the receiving port of the duplexer is 50dBm, this would mean that the transmitted power leaks to the input terminal by-20 dBm, which is input to the low noise amplifier together with the useful signal, and the useful signal cannot be effectively amplified because the leakage power of the transmitting signal is large, so that the low noise amplifier is in a gain compression state. Meanwhile, due to the wide bandwidth characteristic of the ultra-wideband communication system, the received total signal power is the integral of the signal power in the whole frequency band, so that the influence of the nonlinear phenomenon on the ultra-wideband communication system is stronger. In the design process of the low noise amplifier, negative feedback is an effective method for improving linearity, but this is at the expense of gain, and causes deterioration of the noise figure of the low noise amplifier and the system as a whole.
Disclosure of Invention
The invention aims to provide a circuit structure of an ultra-wideband low-noise amplifier, which weakens the strong compromise relation among matching performance, noise, gain and linearity and improves the noise characteristic and linearity under the condition of keeping the gain characteristic and the matching performance unchanged.
The technical idea of the invention is as follows: in view of the compromise relationship among matching, gain, noise and linearity, the circuit structure of the low-noise amplifier circuit is reasonably selected, the parameter values of circuit components are properly set, less noise is introduced while the matching performance is realized, and the noise and linearity of the circuit are improved through the circuit structure, so that the requirements of a communication system on various performance parameters of the low-noise amplifier are met, and the overall performance of a receiving chain is improved.
According to the above idea, the ultra-wideband low noise amplifier of the present invention includes an ultra-wideband low noise amplifier, which adopts a two-stage cascade structure, the first-stage amplification circuit includes a basic common source circuit using a resistor as a load, the second-stage basic common source circuit adopting a parallel peak structure includes a second amplification tube M2, a second bias resistor R3, a second load resistor R4 and a parallel peak inductor L1, signals between the two stages are coupled by a capacitor, and the ultra-wideband low noise amplifier is characterized in that:
the first-stage amplifying circuit comprises a first amplifying tube M1, a feedback MOS tube M3, a bias MOS tube M4, a first bias resistor R1, a first load resistor R2, a third bias resistor R5 and a feedback coupling capacitor C2, wherein the feedback MOS tube M3 and the feedback coupling capacitor C2 form a series circuit which is connected between the grid and the drain of the first amplifying tube M1 and used for providing broadband matching and improving linearity, the source of the feedback MOS tube M3 is connected with the drain of the bias MOS tube M4, and the source of the bias MOS tube M4 is connected to the ground and used for providing bias current for the feedback MOS tube M3;
an auxiliary transconductance amplifier G is connected between the grid electrode of the first amplifying tube M1 and the drain electrode of the second amplifying tube M2 and is used for partially or completely eliminating noise generated by the first amplifying tube M1, the bias MOS tube M4 and the first load resistor R2 and improving the overall noise performance of the ultra-wideband low noise amplifier.
Preferably, the feedback MOS transistor M3 is an NMOS transistor.
Preferably, the channel lengths of the feedback MOS transistor M3, the bias MOS transistor M4 and the first amplifying transistor M1 are the minimum dimensions specified in the CMOS manufacturing process, so as to reduce the parasitic capacitance and improve the frequency characteristic and matching performance.
Preferably, the gate of the bias MOS transistor M4 is connected to the bias voltage vb2 of the current source through the third bias resistor R5, so as to reduce the influence of the gate-drain parasitic capacitance of the bias MOS transistor M4 on the input matching.
Preferably, the gate of the first amplifying tube M1 is connected to one end of a first bias resistor R1, and the other end of R1 is connected to a bias voltage vb1 of the first-stage amplifying circuit; the drain of the first amplifying tube M1 is connected with one end of a first load resistor R2, and the other end of R2 is connected with a power supply vdd; the source of the first amplifying tube M1 is grounded.
Preferably, the gate of the second amplifying tube M2 is connected to one end of a second bias resistor R3, and the other end of R3 is connected to a second-stage amplifying circuit bias voltage vb 3; the drain of the second amplifying tube M2 is connected with one end of a second load resistor R4, the other end of R4 is connected with one end of a parallel peak inductor L1, and the other end of L1 is connected with a power vdd; the source of the second amplifier tube M2 is grounded.
Compared with the prior art, the invention has the following advantages:
1. on the premise of keeping good matching and gain characteristics, the invention further improves the whole linearity by using the nonlinear characteristic of the feedback MOS transistor M3;
2. in the invention, the auxiliary transconductance amplifier G is bridged between the grid electrode of the first amplifying tube M1 and the drain electrode of the second amplifying tube M2, so that the noise contributions of the first amplifying tube M1, the first load resistor R2 and the bias MOS tube M4 are reduced, and the noise performance is improved.
Drawings
FIG. 1 is a block circuit diagram of the present invention;
FIG. 2 is a circuit block diagram of an embodiment of the invention;
FIG. 3 is a graph of input matching performance obtained from simulations of an embodiment of the present invention;
FIG. 4 is a graph of simulated noise characteristics for an embodiment of the present invention;
FIG. 5 is a diagram of the third order intermodulation characteristics obtained from the simulation of the embodiment of the present invention;
fig. 6 is a graph of gain characteristics simulated for an embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to the following drawings, wherein the preferred embodiments are described in detail for the purpose of illustration, and are not to be construed as limiting the scope of the present invention.
Referring to fig. 1, a preferred embodiment of the ultra-wideband low noise amplifier of the present invention is mainly composed of a first stage amplifying circuit a1, a second stage amplifying circuit a2 and an auxiliary amplifier G, where Vs and Rs are respectively an excitation source and an internal resistance. The signal enters a first-stage amplifying circuit A1 through an input blocking capacitor C1 for first-stage amplification, the output signal of A1 is coupled to a second-stage amplifying circuit A2 through an interstage coupling capacitor C3 for second-stage amplification, and the signal amplified by the second stage is output through an output blocking capacitor C4. The whole gain of the ultra-wideband low-noise amplifier can more easily reach the required value through the two-stage amplification, and the feedback MOS tube M3 of the first-stage amplification circuit A1 can provide 50-ohm input resistance component, so that good input matching is realized; the noise of the first stage amplifying circuit a1 can be partially cancelled at the output end of the second stage by the auxiliary amplifier G, thereby improving the noise performance of the present invention.
Referring to fig. 2, the first-stage amplifier circuit a1 includes a basic common source circuit with a resistor as a load, and is composed of a first amplifier transistor M1, a diode-connected feedback MOS transistor M3, a bias MOS transistor M4, a first bias resistor R1, a first load resistor R2, a third bias resistor R5, and a feedback coupling capacitor C2. The source of the first amplifying tube M1 is grounded, the drain is connected to one end of the first load resistor R2, the other end of the first load resistor R2 is connected to the power vdd, the gate of the first amplifying tube M1 is connected to one end of the first bias resistor R1, the other end of the first bias resistor R1 is connected to the first-stage amplifying circuit bias voltage vb1, the gate and the drain of the feedback MOS tube M3 are shorted and connected to the drain of the first amplifying tube M1, the source of the feedback MOS tube M3 is connected to one end of the feedback coupling capacitor C2, the other end of the feedback MOS tube C2 is connected to the gate of the first amplifying tube M1 and used for providing broadband input matching and improving linearity, the source of the feedback MOS tube M3 is connected to the drain of the bias MOS tube M4, the source of the bias MOS tube M4 is grounded, the gate is connected to one end of the third bias resistor R5, and the other end of the third bias resistor R5 is connected to the bias voltage vb2 of the current source and used for reducing the influence of the parasitic gate matching of the input.
The second-stage amplifying circuit a2 adopts a basic common source circuit with a parallel peak structure, and comprises a second amplifying tube M2, a second bias resistor R3, a second load resistor R4 and a parallel peak inductor L1. The grid of the second amplifying tube M2 is connected with one end of a second bias resistor R3, the other end of the second bias resistor R3 is connected with the bias voltage vb3 of the second-stage amplifying circuit, the source of the second amplifying tube M2 is grounded, the drain is connected with one end of a second load resistor R4, the other end of R4 is connected with one end of a parallel peak inductor L1, and the other end of L1 is connected with a power supply vdd to improve the high-frequency gain.
An auxiliary transconductance amplifier G is connected between the grid electrode of the first amplifying tube M1 and the drain electrode of the second amplifying tube M2 and is used for partially or completely eliminating noise generated by the first amplifying tube M1, the bias MOS tube M4 and the first load resistor R2 and improving the overall noise performance of the ultra-wideband low noise amplifier.
Capacitive coupling is adopted among the input signal Si, the first-stage amplification circuit A1, the second-stage amplification circuit A2 and the output signal So. More specifically, the gate of the first amplifying tube M1 is connected to one end of the input dc blocking capacitor C1, and the input signal is input through the other end of the input dc blocking capacitor C1; the drain electrode of the first amplifying tube M1 is connected with one end of the coupling capacitor C3 in a cascade mode, and the other end of the C3 is connected with the grid electrode of the second amplifying tube M2; the drain of the second amplifying tube M2 is connected to one end of the output blocking capacitor C4, and the amplified signal is output from the other end of the output blocking capacitor C4 and flows to the next stage.
The principle and performance analysis of the invention are as follows:
1. theoretical analysis of input matching
In the first-stage amplification circuit A1, a first amplification tube M1 converts an input signal voltage into a signal current, the signal current flows through equivalent output impedance of A1 to generate voltage drop, a feedback MOS tube M3 realizes voltage-current feedback from the drain of M1 to the gate of M1, and M4 appears as a current source to provide proper bias current for M3.
In the case of a low-frequency small signal, neglecting the influence of parasitic factors can obtain that the real part of the input impedance is:
in the above formula RinFor low noise amplifier input resistance component, gM1、gM3The small signal transconductance of the first amplifying transistor M1 and the feedback MOS transistor M3 respectively.
As can be seen from the above formula, by adjusting gM1、gM3And R2 are sized to obtain the input resistance RinIs 50 ohms. By setting the channel lengths of M1, M3 and M4 to the minimum dimensions specified in the CMOS manufacturing process, the maximum limit can be reachedThe influence of input parasitic capacitance is reduced, the antenna is well matched, the frequency characteristic is optimized, and an NMOS tube is used for M3 because the same gM3NMOS has a smaller size than PMOS, and the minimum channel length is 0.18um in this embodiment.
Fig. 3 shows the input matching characteristic of the ultra-wideband low noise amplifier of the embodiment, and it can be seen from fig. 3 that the reflection coefficient S11 of the embodiment is less than-10 dB in the frequency band of 500MHz-5GHz, and good matching is achieved.
2. Analysis of noise performance improvement
The structure of the invention adopts a transconductance amplifier G, a noise cancellation channel is introduced, and the following can be known through noise analysis: the noise current generated by M1 flows through the equivalent output impedance of the first stage amplifier circuit, and generates noise voltages with the same polarity at points a and B in fig. 2, where the noise voltage at point a is amplified by the second stage amplifier circuit and converted into the drain current of M2, and the noise voltage at point B is amplified by the auxiliary transconductance amplifier G to generate the output current of G, and these two noise currents are superimposed at the drain of M2. Since the transconductance of the amplifier G and the transconductance of the second stage amplifier circuit have opposite signs, the gain of the auxiliary transconductance amplifier G is properly selected to cancel the two noise currents, i.e., the noise current generated by M1 is cancelled at the output terminal of the lna. Under the condition that the noise current of M1 is completely eliminated, the noise generated by the first load resistor R2 and the bias MOS transistor M4 is also cancelled to different degrees.
Contrary to the analysis result of the noise, the signal voltage input to the gate of M1 is amplified by the two-stage common source amplifier, and an output signal with the same polarity as the input signal is obtained; the input signal is amplified by the auxiliary transconductance amplifier, and the output signal with the same polarity is obtained, namely the signal voltage at the output end is strengthened.
By using the auxiliary transconductance amplifier, the noises of the first amplifying transistor M1, the first load resistor R2 and the bias MOS transistor M4 are weakened, and the output signal voltage is strengthened, so that the ultra-wideband low-noise amplifier obtains good noise characteristics.
Fig. 4 shows a curve of the noise characteristic of the present embodiment with frequency, and it can be seen that the noise figure NF is less than 3dB in the entire frequency band of 500MHz-5GHz, resulting in good noise performance.
3. Theoretical analysis of linearity improvement
The feedback MOS tube M3 is used as the feedback path of the first-stage amplifying circuit, and the matching factor is considered, and the pre-distortion processing can be carried out on the input large signal, so that the whole linearity of the two-stage circuit is improved.
According to fig. 1, the principle of using a feedback MOS transistor as a feedback path to improve linearity in case of large signals is further explained.
Under the condition that the gain of the amplifier a0 in fig. 1 is large enough and the feedback MOS transistor M3 has ideal square rate characteristics, it can be derived that the voltage gain from the input source Vs to the intermediate node C is:
in the formula VCThe output large signal voltage at point C in FIG. 1 is K ═ 0.5 μnCoxW/L, process and size parameter, V, of feedback MOS transistor M3THIs the threshold voltage of M3. A negative sign appears inside the root sign since the input voltage Vs itself is a negative value.
As can be seen from the above equation, the output voltage Vc at point C has a square root relation with the input voltage Vs, i.e., a1 performs predistortion processing on the input large signal. In the embodiment, the second-stage circuit a2 adopts a common source structure, so that the input-output voltage characteristic of the second-stage amplifying circuit is a square rate characteristic, the pre-distorted signal voltage is coupled to the gate of the second-stage amplifying circuit M2 through the inter-stage coupling capacitor C3, and the output signal voltage with good linearity is obtained through amplification of the square rate characteristic of a 2.
Fig. 5 shows the linearity simulation results of the embodiment. When the frequency is tested at 2GHz, the output third-order intermodulation point can reach 12.24dBm, and the linearity is improved.
4. Theoretical analysis of high frequency gain preservation
In the second-stage amplifying circuit a2, the series connection of the second load resistor R4 and the parallel peak inductor L1 is used as the overall load of a 2. It is assumed here that the load capacitance is denoted CLNeglecting the parasitic factors of the tube, the small signal gain from the gate of M2 to the drain of M2 of the second stage amplifier circuit is deduced by circuit theory as follows:
in the above formula AvFor the second stage of amplifying the circuit voltage gain, gM2Is the transconductance of the second amplifier tube M2.
As can be seen from the above formula, in the second-stage amplification circuit, because a resistor and an inductor are adopted to be connected in series, a zero-R4/L1 exists in the frequency characteristic, the positions of the zeros can be adjusted by adjusting the values of R4 and L1, and one pole of the amplifier is cancelled, so that the overall gain of the ultra-wideband low-noise amplifier is still kept at a high level at high frequency.
Fig. 6 shows the results of the gain simulation of the embodiment of the present invention, when the frequency is increased from 500MHz to 5GHz, the gain is gradually increased from less than 19dB to more than 20dB, and it can be seen that the existence of the zero point increases the gain with the increase of the frequency.
The foregoing is illustrative of the principles of the present invention, and as before it is to be understood that the invention is not limited to the disclosed forms, but is capable of modifications in various obvious respects, all without departing from the scope of the invention.
Claims (6)
1. The ultra-wideband low-noise amplifier adopts a two-stage cascade structure, a first-stage amplifying circuit A1 comprises a basic common source circuit taking a resistor as a load, a second-stage amplifying circuit A2 adopts the basic common source circuit of a parallel peak structure, and comprises a second amplifying tube M2, a second bias resistor R3, a second load resistor R4 and a parallel peak inductor L1, signals between two stages are coupled by capacitors, and the ultra-wideband low-noise amplifier is characterized in that:
the first-stage amplifying circuit A1 comprises a first amplifying tube M1, a diode-connected feedback MOS tube M3, a bias MOS tube M4, a first bias resistor R1, a first load resistor R2, a third bias resistor R5 and a feedback coupling capacitor C2, wherein the feedback MOS tube M3 and the feedback coupling capacitor C2 form a series circuit which is connected between the grid and the drain of the first amplifying tube M1 and used for providing broadband matching and improving linearity, the source of the feedback MOS tube M3 is connected with the drain of the bias MOS tube M4, and the source of the bias MOS tube M4 is connected with the ground and used for providing bias current for the feedback MOS tube M3;
an auxiliary transconductance amplifier G is connected between the grid electrode of the first amplifying tube M1 and the drain electrode of the second amplifying tube M2 and is used for partially or completely eliminating noise generated by the first amplifying tube M1, the bias MOS tube M4 and the first load resistor R2 and improving the overall noise performance of the ultra-wideband low noise amplifier.
2. The ultra-wideband low noise amplifier of claim 1, wherein the feedback MOS transistor M3 is an NMOS transistor.
3. The ultra-wideband low noise amplifier of claim 1, wherein the channel lengths of the feedback MOS transistor M3, the bias MOS transistor M4, and the first amplifying transistor M1 are all the minimum dimensions specified in the CMOS manufacturing process to reduce parasitic capacitance and improve frequency characteristics and matching performance.
4. The ultra-wideband low noise amplifier of claim 1, wherein the gate of the bias MOS transistor M4 is connected to the bias voltage vb2 of the current source through a third bias resistor R5 for reducing the influence of the gate-drain parasitic capacitance of the bias MOS transistor M4 on the input matching.
5. The ultra-wideband low noise amplifier of claim 1, wherein the gate of the first amplifying transistor M1 is connected to one end of a first bias resistor R1, and the other end of R1 is connected to the bias voltage vb1 of the first stage amplifying circuit; the drain of the first amplifying tube M1 is connected with one end of a first load resistor R2, and the other end of R2 is connected with a power supply vdd; the source of the first amplifying tube M1 is grounded.
6. The ultra-wideband low noise amplifier of claim 1, wherein the gate of the second amplifying transistor M2 is connected to one end of the second bias resistor R3, and the other end of R3 is connected to the bias voltage vb3 of the second stage amplifying circuit; the drain of the second amplifying tube M2 is connected with one end of a second load resistor R4, the other end of R4 is connected with one end of a parallel peak inductor L1, and the other end of L1 is connected with a power vdd; the source of the second amplifier tube M2 is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711068702.3A CN107733375B (en) | 2017-11-03 | 2017-11-03 | Ultra-wideband low-noise amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711068702.3A CN107733375B (en) | 2017-11-03 | 2017-11-03 | Ultra-wideband low-noise amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107733375A CN107733375A (en) | 2018-02-23 |
| CN107733375B true CN107733375B (en) | 2020-08-11 |
Family
ID=61222311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711068702.3A Active CN107733375B (en) | 2017-11-03 | 2017-11-03 | Ultra-wideband low-noise amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107733375B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108736967B (en) * | 2018-05-11 | 2021-04-06 | 厦门思力科电子科技有限公司 | Infrared receiving chip circuit and infrared receiving system |
| CN110690862A (en) * | 2018-07-06 | 2020-01-14 | 天工方案公司 | Amplifier linearity enhancement circuit and method for post-distortion feedback cancellation |
| CN110190816B (en) * | 2019-04-17 | 2021-05-14 | 西安电子科技大学 | Self-feedback low-noise amplifier applied to biopotential treatment |
| CN110708021B (en) * | 2019-09-30 | 2023-04-07 | 西安电子科技大学 | High-linearity differential double-feedback low-noise amplifier |
| CN111030694B (en) * | 2019-12-12 | 2023-03-21 | 西安电子科技大学 | Ultra-wideband source random hold amplifier based on inductive peaking |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103117711A (en) * | 2013-01-29 | 2013-05-22 | 天津大学 | Monolithic integrated radio frequency high-gain low-noise amplifier |
| CN103532497A (en) * | 2013-10-18 | 2014-01-22 | 中国科学技术大学 | Ultra-wide-band low-noise amplifier adopting inductance compensation technology |
| EP2624447B1 (en) * | 2012-02-01 | 2014-09-24 | Telefonaktiebolaget L M Ericsson AB (Publ) | Noise canceling low-noise amplifier |
| WO2015163971A3 (en) * | 2014-02-09 | 2015-12-17 | The Trustees Of Columbia University In The City Of New York | Circuits for low noise amplifiers with interferer reflecting loops |
| CN106505955A (en) * | 2016-10-26 | 2017-03-15 | 天津大学 | A kind of Ku band broadband low-noise amplifiers based on CMOS technology |
| CN106533367A (en) * | 2016-10-26 | 2017-03-22 | 天津大学 | High-gain CMOS low-noise amplifier for TD-LTE (Time Division Long Term Evolution) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100667303B1 (en) * | 2005-02-01 | 2007-01-12 | 삼성전자주식회사 | Low noise amplifier for ultra-wide band |
-
2017
- 2017-11-03 CN CN201711068702.3A patent/CN107733375B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2624447B1 (en) * | 2012-02-01 | 2014-09-24 | Telefonaktiebolaget L M Ericsson AB (Publ) | Noise canceling low-noise amplifier |
| CN103117711A (en) * | 2013-01-29 | 2013-05-22 | 天津大学 | Monolithic integrated radio frequency high-gain low-noise amplifier |
| CN103532497A (en) * | 2013-10-18 | 2014-01-22 | 中国科学技术大学 | Ultra-wide-band low-noise amplifier adopting inductance compensation technology |
| WO2015163971A3 (en) * | 2014-02-09 | 2015-12-17 | The Trustees Of Columbia University In The City Of New York | Circuits for low noise amplifiers with interferer reflecting loops |
| CN106505955A (en) * | 2016-10-26 | 2017-03-15 | 天津大学 | A kind of Ku band broadband low-noise amplifiers based on CMOS technology |
| CN106533367A (en) * | 2016-10-26 | 2017-03-22 | 天津大学 | High-gain CMOS low-noise amplifier for TD-LTE (Time Division Long Term Evolution) |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107733375A (en) | 2018-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107733375B (en) | Ultra-wideband low-noise amplifier | |
| US7834698B2 (en) | Amplifier with improved linearization | |
| CN107196611B (en) | Broadband single-ended-to-differential low-noise amplifier | |
| US10903798B2 (en) | Ultrawideband very low noise amplifier with noise reduction and current reuse | |
| AU2013214368B2 (en) | Low-noise amplifier | |
| Reja et al. | An area-efficient multistage 3.0-to 8.5-GHz CMOS UWB LNA using tunable active inductors | |
| CN107248850B (en) | Non-inductance low-power-consumption high-gain high-linearity broadband low-noise amplifier | |
| CN110729974A (en) | Ultra-wideband high-gain low-noise amplifier | |
| KR20220002907A (en) | Wideband Low Noise Amplifier with Noise Rejection | |
| CN111740705A (en) | Low-noise amplifier for eliminating nonlinearity | |
| CN110034738B (en) | Ultra-wideband low-noise amplifier based on improved impedance matching network | |
| CN116248052A (en) | Low noise amplifier and radio frequency chip | |
| CN111478671A (en) | Novel low-noise amplifier applied to Sub-GHz frequency band | |
| Yousef et al. | A 2–16 GHz CMOS current reuse cascaded ultra-wideband low noise amplifier | |
| CN116865691A (en) | Ultra-wideband low noise amplifier with bandwidth reconfigurable technology | |
| CN107579715B (en) | Broadband linear CMOS low-noise amplifier circuit | |
| CN113904635A (en) | High-third-order intermodulation point field effect transistor radio frequency amplifier | |
| Dorafshan et al. | High-gain CMOS low noise amplifier for ultra wide-band wireless receiver | |
| CN112468099A (en) | Radio frequency front end and low noise amplifier thereof | |
| CN112910420A (en) | High-linearity radio frequency power amplifier | |
| CN110661494A (en) | High-frequency amplifier circuit and semiconductor device | |
| CN113422580B (en) | Single-ended non-inductance low-noise amplifier suitable for broadband receiver | |
| CN218387444U (en) | Broadband high-gain low-noise amplifier | |
| CN215420203U (en) | Broadband high-linearity low-noise amplifier circuit based on CMOS structure | |
| KR101669507B1 (en) | Method and apparatus for tx leakage cancelling pre-processing in receiver of wireless communication system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |