CN107579715B - Broadband linear CMOS low-noise amplifier circuit - Google Patents

Broadband linear CMOS low-noise amplifier circuit Download PDF

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CN107579715B
CN107579715B CN201710858969.6A CN201710858969A CN107579715B CN 107579715 B CN107579715 B CN 107579715B CN 201710858969 A CN201710858969 A CN 201710858969A CN 107579715 B CN107579715 B CN 107579715B
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nmos
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郭本青
王雪冰
陈鸿鹏
张晓祥
陈俊
刘畅
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University of Electronic Science and Technology of China
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Abstract

The invention discloses a broadband linearization CMOS low noise amplifier circuit, aiming at the problem that the linearity is improved at a single frequency point in the prior linearization technology and the high linearity in the broadband range is not an effective solution; the LNA circuit is designed by adopting a CMOS complementary symmetrical structure, and linearity tuning optimization within a broadband range is carried out by using a bias circuit and a transistor size which are digitally controlled; an LNA circuit is obtained that can significantly improve the linearity of the LNA over a wide band while achieving high gain and low noise figure.

Description

Broadband linear CMOS low-noise amplifier circuit
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a design technology of a linear low-noise amplifier.
Background
The scaling down of CMOS processes enables the easy design of low noise, low power amplifiers. However, the linearity of the CMOS transistor is deteriorated due to the decrease in the power supply voltage and the degradation of the mobility. On the other hand, software radio technology based on the broadband transceiving principle puts high demands on linearity. All these have led to the study and development of linearization techniques.
Backtracking, the most effective linearization method is the multi-gate transistor (MGTR) technology (i.e., t.w.kim, b. -k.kim, and k. -r.lee, "high lly linear receiver front-end adapting MOSFET transduction coupled transistors," IEEE j.solid-State Circuits, vol.39, No.1, pp.223-229, jan.2004), which cancels the negative third-order nonlinearity of the main transistor by connecting an auxiliary transistor with positive third-order nonlinearity operating in the weak inversion region in parallel beside the main transistor, as shown in fig. 1. Thereby increasing the linearity of the circuit in a wider bias voltage range. However, at high frequencies, the interaction of the second order nonlinear coefficients with the input network often limits the practical effectiveness of this technique. Thus, improved derivative superposition methods are proposed to alleviate this conflict, but with the complexity of the input matching network structure. After that, post-distortion techniques (h.zhang, x.fan, and E.S a nchez-sine, "a low-power, linear, ultra-wideband LNA design technique," IEEE j.solid-State Circuits, vol.44, No.2, pp.320-330, feb.2009.) appeared, as shown in fig. 2, the control voltage of the third-order intermodulation component IM3 canceller can be sampled from the output node of the input transistor, resulting in a reduced influence on the input matching network. However, in general, the prior linearization techniques have achieved more linearity improvement at a single frequency. Achieving high linearity over a wide band remains a very challenging task.
Disclosure of Invention
In order to solve the technical problems, the application provides a broadband linear CMOS low-noise amplifier circuit, which adopts a CMOS complementary symmetric structure to improve the second-order linearity, and adopts a digital control technology to tune the nonlinear performance of the circuit to obtain the third-order distortion compensation effect of the broadband; the broadband linearity of the low-noise amplifier circuit is remarkably improved.
The technical scheme adopted by the invention is as follows: a wideband linearized CMOS low noise amplifier circuit comprising: the circuit comprises a common-gate input stage, a noise elimination stage, an amplification stage and a load stage; the input end of the common-gate input stage is connected with a radio-frequency signal, the first output end of the common-gate input stage is connected with the first input end of the amplification stage, and the second output end of the common-gate input stage is connected with the second input end of the amplification stage; the output end of the amplifying stage is connected with the input end of the load stage; the input end of the noise elimination stage is connected with a radio frequency input signal; the output end of the noise elimination stage is connected with the input end of the load stage, and the output end of the load stage outputs an amplified signal.
Further, the common-gate input stage comprises: the transistor comprises a first NMOS transistor, a first PMOS transistor, a resistor Rgp, a resistor Rgn, a capacitor C1 and a capacitor C3; the source electrode of the first NMOS tube and the source electrode of the first PMOS tube are connected together to be used asThe input end of the common-gate input stage is connected with a radio-frequency signal through a blocking capacitor C4; the drain electrode of the first NMOS tube is connected with a power supply V through a resistor RgnDD(ii) a The drain electrode of the first NMOS tube is also connected with the first end of a capacitor C1, and the second end of the capacitor C1 is used as the first output end of the common-gate input stage; the drain electrode of the first PMOS tube is grounded through a resistor Rgp; the drain electrode of the first PMOS tube is also connected with the first end of a capacitor C3, and the second end of the capacitor C3 is used as the second output end of the common-gate input stage; the grid electrode of the first NMOS tube is connected with a voltage Vbn 1; the gate of the first PMOS tube is connected with the voltage Vbp 1.
Further, the voltage Vbn1 and the voltage Vbp1 are controlled by 4-bit digits.
Further, the amplification stage comprises: the grid electrode of the second NMOS tube is used as a first input end of the amplification stage; the source electrode of the second NMOS tube is connected with a power supply VDD(ii) a The drain electrode of the second NMOS tube and the drain electrode of the second PMOS tube are connected together to be used as the output end of the amplifier stage; the grid electrode of the second PMOS tube is used as a second input end of the amplification stage; the source electrode of the second PMOS tube is grounded; the grid electrode of the second NMOS tube is also connected with a voltage Vbn3, and the grid electrode of the second PMOS tube is also connected with a voltage Vbp 3.
Further, the noise cancellation stage comprises: a third NMOS transistor, a third PMOS transistor, a resistor RF and a capacitor C2; the grid electrode of the third NMOS tube is connected with the grid electrode of the third PMOS tube, the grid electrode of the third NMOS tube is also connected with the first end of a capacitor C2, and the second end of the capacitor C2 is used as the input end of a noise elimination stage; the grid electrode of the third NMOS tube is also connected with the first end of the resistor RF, and the second end of the resistor RF is connected with the drain electrode of the third NMOS tube; the source electrode of the third NMOS tube is connected with external voltage, and the drain electrode of the third NMOS tube is also connected with the drain electrode of the third PMOS tube to be used as the output end of the noise elimination stage; and the source electrode of the third PMOS tube is grounded.
Further, the N well width W of the third NMOS tuben3P well width W of the third PMOS tubep3By 2-bit digital control.
The invention has the beneficial effects that: the invention discloses a broadband linear CMOS low-noise amplifier circuit, which comprises a common-gate input stage on a main path, an amplification stage, a noise elimination stage on an auxiliary path and a load stage, wherein the common-gate input stage is connected with the amplification stage; the radio frequency signal is output from the load resistor after being amplified by the main path and the auxiliary path; the method and the device adopt a digital control technology to tune the nonlinear performance of the circuit to obtain a third-order distortion compensation effect of the broadband; the low-noise amplifier circuit of the application has a complementary symmetrical structure of CMOS, so that the second-order linearity is improved; the low-noise amplifier circuit can obviously improve the broadband linearity of the LNA under the condition of maintaining a certain gain and noise index.
Drawings
FIG. 1 is a schematic diagram of a prior art multi-gate transistor (MGTR) amplifier circuit;
FIG. 2 is a schematic diagram of a prior art post-distortion amplifier circuit;
FIG. 3 is a schematic diagram of a wideband linearized CMOS low noise amplifier circuit of the present invention;
FIG. 4 is a graph of the gain results of a wideband linearized CMOS low noise amplifier circuit of the present invention;
FIG. 5 is a graph of the noise results of a wideband linearized CMOS low noise amplifier circuit of the present invention;
FIG. 6 is a graph of the wide-band linearity results of a wide-band linearized CMOS low noise amplifier of the present invention.
Detailed Description
In order to facilitate the understanding of the technical contents of the present invention by those skilled in the art, the present invention will be further explained with reference to the accompanying drawings.
Fig. 1 shows a schematic diagram of an amplifier circuit according to the present application, and the technical solution of the present application is: a wideband linearized CMOS low noise amplifier circuit, using a CMOS complementary symmetric structure, comprising: the circuit comprises a common-gate input stage, a noise elimination stage, an amplification stage and a load stage; the input end of the common-gate input stage is connected with a radio-frequency signal, the first output end of the common-gate input stage is connected with the first input end of the amplification stage, and the second output end of the common-gate input stage is connected with the second input end of the amplification stage; the output end of the amplifying stage is connected with the input end of the load stage; the input end of the noise elimination stage is connected with a radio frequency input signal; the output end of the noise elimination stage is connected with the input end of the load stage, and the output end of the load stage outputs an amplified signal.
The common-gate input stage includes: the transistor comprises a first NMOS transistor Mn1, a first PMOS transistor Mp1, a resistor Rgp, a resistor Rgn, a capacitor C1 and a capacitor C3; one end of a signal source Vs is grounded, the other end of the signal source Vs is used as a radio frequency input signal through a resistor Rs and a blocking capacitor C4, sources of Mp1 and Mn1 are connected with the X point with the radio frequency input signal, a gate of Mp1 is connected with a voltage Vbp1, and a gate of Mn1 is connected with a voltage Vbn 1; the drain of Mp1 is Grounded (GND) through a resistor Rgp, and the drain of Mp1 is also connected to the gate of Mn3 through a capacitor C3; the drain of Mn1 is connected to VDD through resistor Rgn, and the drain of Mn1 is also connected to the gate of Mp3 through capacitor C1.
The amplification stage comprises: the drains of the second NMOS transistor Mn3, the second PMOS transistor Mp3, both Mn3 and Mp3 are connected to point Y. The source of Mp3 is connected to VDD, and Vbp3 is connected to the gate of Mp3 through a resistor; the source of Mn3 is connected to Ground (GND), and Vbn3 is connected to the gate of Mn3 through a resistor.
The noise cancellation stage comprises: a third NMOS transistor Mn2, a third PMOS transistor Mp2, a resistor RF and a capacitor C2; the gates of both Mp2 and Mn2 are connected together, and the radio frequency input signal is connected through a capacitor C2; the source of Mp2 is connected with an external voltage, and the source of Mn2 is grounded; the drains of both Mp2 and Mn2 are connected together as the output of the noise cancellation stage; a resistor RF is connected in series between the gates and drains of both Mp2 and Mn 2.
The load stage is composed of a capacitor CL and a resistor RL. The stage is connected to a point Y, is connected to the ground through a capacitor CL and a low-noise amplifier load resistor RL in sequence, and signals are output from the load resistor after being amplified by the main path and the auxiliary path.
The low noise amplifier circuit provided by the invention adopts a CMOS complementary symmetric structure to compensate a second-order distortion coefficient and uses a digitally controlled bias voltage (V)bn1、Vbp1) And pipe size (W)n3&Wp3) And performing linearity tuning optimization in a broadband range. The performance of the circuit is analyzed simply by making the complementary transistor equivalent to the composite transistor. Specifically, the method comprises the following steps:
Figure BDA0001414627090000041
wherein, gmni、gmpi、gmiRespectively represent transistors Mni、MpiComposite transistor MiThe transconductance (i is 1 to 3); g'mni,g′mpi,g′mi,g″mni,g″mpi,g″miRepresents a transistor Mni、MpiComposite transistor MiFirst and second order transconductance derivatives.
According to circuit theory, the output signal current i of the circuit of the inventionoCan be expressed as a non-linear function of the input signal vs:
Figure BDA0001414627090000042
Figure BDA0001414627090000043
Figure BDA0001414627090000044
Figure BDA0001414627090000045
first, g 'inside the formula because second-order nonlinearity can be largely eliminated by complementary technology'miThe relevant terms are approximately ignored. Second, because the third-order non-linear polarity of the transistor in the weak inversion region is opposite to that of the strong inversion transistor, the second-order non-linear polarity is the same. Thus, the amplifier stage transistor M is adjustedn3/Mp3Transistor M of size to cancel noisen2/Mp2Third order non-linearity of (2). I.e., the second term in equation (5) is eliminated. Based on this principle, the amplifier can obtain high IIP3 and IIP2 linearity at a single frequency point. Again, as the frequency increases, the non-linearities of the second term in equation (5) cancel each other out and deteriorate. The reason is the nonlinearity caused by the parasitic effect of the main path and the auxiliary pathThe vector polarity is rotated. In this case, the frequency-dependent compensation variation due to the second term can be compensated by introducing the fourth third-order nonlinear term in equation (5). By controlling Vbn1&Vbp1The third order nonlinearity of the fourth term is tuned.
Simulation shows that M is changedn3and Mp3The size can further achieve optimized broadband linearity performance. Specifically, 4-bit controlled Vbn1: 1.5/1.525/1.55/1.57-V, 4 bit controlled Vbp1: 0.2/0.24/0.27/0.3-V. 2 bit controlled Wn3&Wp320/25 and 70/80-mum respectively, and the channel length is 0.18-mum. On the other hand, the third-order nonlinear terms introduced in the formula (5) enable the noise of the input transistor of the circuit not to be completely eliminated, but simulation shows that the added noise elimination level transconductance adopted by the circuit can still obtain the low noise of the whole circuit; the method specifically comprises the following steps:
the LNA (low noise amplifier) circuit is realized by adopting a 0.18 mu m rf CMOS (complementary metal oxide semiconductor) process. Under the power supply voltage of 1.8V, the chip bias current is 10.6 mA. The voltage gain curve for auxiliary path closed (aux.on) is S11, and the voltage gain curve for auxiliary path open (aux.off) is S12, as shown in fig. 4, the bandwidth of S11<10dB is 0.1 to 1.4GHz, and the voltage gain of LNA reaches 16.1 dB. Fig. 5 shows the noise figure results, the noise figure of the curve of the present application is 2.8-3.4 dB in the frequency range of 0.1 to 1.4ghz, and when the auxiliary path is disconnected, the noise degrades to about 8 dB.
In addition, the gain and noise degradation caused by the bias change brought by the digital control word are respectively less than 0.8 dB and less than 0.4 dB. And carrying out linearity simulation by adopting a test signal of constant amplitude diphone, wherein the diphone distances of the IIP2 and the IIP3 are 100 MHz and 10MHz respectively. As shown in FIG. 6, the IIP3 and the IIP2 are 13-18.9 dBm and 24-40 dBm in sequence within the designed bandwidth range. For the 500MHz dot frequency optimization result in the figure, the corresponding control variable of the corresponding digital control word is Vbn1&Vbp1:1.5、0.3V；Wn3&Wp325 and 80 um. It can be seen that the LNA circuit of the present application achieves good wideband IIP3 and IIP2 performance.
Frequency in fig. 4-6 represents Frequency.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims (3)

1. A wideband linearized CMOS low noise amplifier circuit, comprising: the circuit comprises a common-gate input stage, a noise elimination stage, an amplification stage and a load stage; the input end of the common-gate input stage is connected with a radio-frequency signal, the first output end of the common-gate input stage is connected with the first input end of the amplification stage, and the second output end of the common-gate input stage is connected with the second input end of the amplification stage; the output end of the amplifying stage is connected with the input end of the load stage; the input end of the noise elimination stage is connected with a radio frequency input signal; the output end of the noise elimination stage is connected with the input end of the load stage, and the output end of the load stage outputs an amplified signal;
the common-gate input stage comprises: the transistor comprises a first NMOS transistor, a first PMOS transistor, a resistor Rgp, a resistor Rgn, a capacitor C1 and a capacitor C3; the source electrode of the first NMOS tube and the source electrode of the first PMOS tube are connected together to be used as the input end of the common-gate input stage, and are connected with a radio-frequency signal through a blocking capacitor C4; the drain electrode of the first NMOS tube is connected with a power supply V through a resistor RgnDD(ii) a The drain electrode of the first NMOS tube is also connected with the first end of a capacitor C1, and the second end of the capacitor C1 is used as the first output end of the common-gate input stage; the drain electrode of the first PMOS tube is grounded through a resistor Rgp; the drain electrode of the first PMOS tube is also connected with the first end of a capacitor C3, and the second end of the capacitor C3 is used as the second output end of the common-gate input stage; the grid of the first NMOS tube is connected with a voltage Vbn1(ii) a The grid of the first PMOS tube is connected with a voltage Vbp1；
The amplification stage comprises: the grid electrode of the second NMOS tube is used as a first input end of the amplification stage; the source electrode of the second NMOS tube is connected with a power supply VDD(ii) a The drain electrode of the second NMOS tube and the drain electrode of the second PMOS tube are connected together to be used as the output end of the amplifier stage; the grid electrode of the second PMOS tube is used as a second input end of the amplification stage; the source electrode of the second PMOS tube is grounded; the grid electrode of the second NMOS tube is also connected with a voltage Vbn3, and the grid electrode of the second PMOS tube is also connected with a voltage Vbp 3;
the noise cancellation stage comprises: a third NMOS transistor, a third PMOS transistor, a resistor RF and a capacitor C2; the grid electrode of the third NMOS tube is connected with the grid electrode of the third PMOS tube, the grid electrode of the third NMOS tube is also connected with the first end of a capacitor C2, and the second end of the capacitor C2 is used as the input end of a noise elimination stage; the grid electrode of the third NMOS tube is also connected with the first end of the resistor RF, and the second end of the resistor RF is connected with the drain electrode of the third NMOS tube; the source electrode of the third NMOS tube is connected with external voltage, and the drain electrode of the third NMOS tube is also connected with the drain electrode of the third PMOS tube to be used as the output end of the noise elimination stage; the source electrode of the third PMOS tube is grounded;
by carrying out analytical equivalence on the complementary transistor equivalent to the composite transistor, the performance analysis of the circuit is simple and convenient, and specifically:
Figure FDA0003004111500000011
wherein, gmni、gmpi、gmiRespectively represent NMOS tubes (M)ni) PMOS tube (M)pi) Composite transistor MiTransconductance of (1); g'mni,g′mpi,g′mi,g″mni,g″mpi,g″miRepresents an NMOS transistor (M)ni) PMOS tube (M)pi) Composite transistor MiTaking 1-3 as the first-order transconductance derivative and the second-order transconductance derivative of (i);
according to circuit theory, the output signal current i of the circuitoCan be expressed as a non-linear function of the input signal vs:
Figure FDA0003004111500000021
Figure FDA0003004111500000022
Figure FDA0003004111500000023
Figure FDA0003004111500000024
first, g 'inside the formula because second-order nonlinearity can be largely eliminated by complementary technology'miThe relevant terms are approximately ignored; secondly, because the third-order nonlinear polarities of the transistor in the weak inversion region and the strong inversion transistor are opposite, and the second-order nonlinear polarities are the same; therefore, the N-well width W of the third NMOS transistor is adjustedn3P well width W of the third PMOS tubep3Transistor M of cancellation stage of noisen2/Mp2Third order non-linearity of (1); i.e. the second term in equation (5) is eliminated, and based on this principle, the amplifier can obtain high IIP3 and IIP2 linearity at a single frequency point; thirdly, as the frequency increases, the nonlinearity of the second term in the equation (5) is mutually cancelled and worsened because of the rotation of the polarity of the nonlinear vector caused by the parasitic effect of the main path and the auxiliary path, and at this time, the frequency-dependent compensation deviation generated by the second term can be compensated by the introduction of the fourth third-order nonlinear term in the equation (5); by controlling Vbn1And Vbp1The third order nonlinearity of the fourth term is tuned.
2. The wideband linearized CMOS low noise amplifier circuit as claimed in claim 1, wherein the voltages Vbn1 and Vbp1 are controlled by 4 bits.
3. The wideband linearized CMOS low noise amplifier circuit as claimed in claim 1, wherein said third NMOS transistor has an N-well width Wn3P of third PMOS tubeWell width Wp3By 2-bit digital control.
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