CN107579715A - A kind of broadband linear CMOS amplifier circuit in low noise - Google Patents
A kind of broadband linear CMOS amplifier circuit in low noise Download PDFInfo
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Abstract
The present invention discloses a kind of broadband linear CMOS amplifier circuit in low noise, and for being the lifting that the linearity is obtained in single frequency point mostly in current linearization technique, High Linear shortage effective workaround is obtained in broadband range；The application designs LNA circuits by using CMOS mutual symmetries structure, and the linearity tuning optimization in broadband range is carried out using numerically controlled biasing circuit and transistor size；Obtain to significantly improve the LNA linearity in broadband range, and obtain higher gain simultaneously, and the LNA circuits of relatively low noise figure.
Description
Technical field
The invention belongs to integrated circuit fields, more particularly to a kind of linearisation low-noise amplifier designing technique.
Background technology
The equal proportion reduction of CMOS technology makes it possible to easily design low noise, the amplifier of low-power consumption.However,
The linearity of CMOS transistor but deteriorates because supply voltage successively decreases the degeneration with mobility.On the other hand, received based on broadband
The software and radio technique of hair principle is even more that high requirement is proposed to the linearity.It is all these to have expedited the emergence of grinding for linearization technique
Study carefully and develop.
In the backtracking past, maximally effective linearization technique is multiple-gate transistor (MGTR) technology (that is, T.W.Kim, B.-
K.Kim,and K.-R.Lee,“Highly linear receiver front-end adopting MOSFET
transconductance linearization by multiple gated transistors,”IEEE J.Solid-
State Circuits, vol.39, no.1, pp.223-229, Jan.2004), as shown in figure 1, the technology passes through in host crystal
One in parallel is operated in weak inversion regime beside pipe, the auxiliary tube with positive third-order nonlinear optical coefficient, to offset the negative of supervisor
Third-order nonlinear optical coefficient.And then the linearity of circuit is added in a wider bias voltage ranges.Nevertheless, but
Under high frequency, the interaction of second order nonlinear coefficient and input network usually limit the actual effect of the technology.Then, improve
Derivative superposition method be suggested, to alleviate the contradiction, but with it be that input matching network structure becomes complicated.Afterwards, go out
Showed rear anti-aliasing techniques (H.Zhang, X.Fan, and E.S á nchez-Sinencio, " A low-power, linearized,
ultra-wideband LNA design technique,”IEEE J.Solid-State Circuits,vol.44,no.2,
Pp.320-330, Feb.2009.), as shown in Fig. 2 the control voltage of third order intermodulation component IM3 arresters can be from input crystal
The output node sampling of pipe, as a result reduces the influence to input matching network.However, former linearization technique on the whole
It is more the lifting that the linearity is obtained in single frequency point.It is still one extremely challenging that High Linear is obtained in broadband range
Task.
The content of the invention
In order to solve the above technical problems, present applicant proposes a kind of broadband linear CMOS amplifier circuit in low noise, adopt
Second-order linearity degree is improved with CMOS mutual symmetry structures, the non-linear behaviour of circuit is tuned using digital control technology
Obtain the three rank skew compensation effects in broadband；Significantly improve the wide-band linearity degree of amplifier circuit in low noise.
The technical solution adopted by the present invention is：A kind of broadband linear CMOS amplifier circuit in low noise, including：Grid are defeated altogether
Enter level, noise eliminates level, amplifying stage and load stage；The input termination radiofrequency signal of common-gate input stage, the of common-gate input stage
The first input end of one output termination amplifying stage, the second input of the second output termination amplifying stage of common-gate input stage；Amplification
The input of the output termination load stage of level；Noise eliminates the input termination radio-frequency input signals of level；Noise eliminates the output of level
The input of terminating load level, the output end output amplified signal of load stage.
Further, the common-gate input stage includes：First NMOS tube, the first PMOS, resistance Rgp, resistance Rgn, electricity
Hold C1, electric capacity C3；The source electrode of first NMOS tube is connected collectively as the defeated of common-gate input stage with the source electrode of the first PMOS
Enter end, and radiofrequency signal is connect by capacitance C4；The drain electrode of first NMOS tube meets power supply V by resistance RgnDD；First NMOS
The drain electrode of pipe is also connected with electric capacity C1 first ends, the first output end of electric capacity C1 the second end as common-gate input stage；First
The drain electrode of PMOS is grounded by resistance Rgp；First end of the drain electrode also with electric capacity C3 of first PMOS is connected, and the of electric capacity C3
Second output end of two ends as common-gate input stage；The grid of first NMOS tube meets voltage Vbn1；The grid of first PMOS connects
Voltage Vbp1.
Further, the voltage Vbn1 and voltage Vbp1 is controlled by 4 bit numerical digits.
Further, the amplifying stage includes：Second NMOS tube, the second PMOS, the grid of second NMOS tube are made
For the first input end of amplifying stage；The source electrode connection power supply V of second NMOS tubeDD；The drain electrode of second NMOS tube and the second PMOS
Drain electrode be connected collectively as amplifying stage output end；Second input of the grid of second PMOS as amplifying stage；Second
The source ground of PMOS；The grid of second NMOS tube also meets voltage Vbn3, and the grid of the second PMOS also connects voltage
Vbp3。
Further, the noise eliminates level and included：3rd NMOS tube, the 3rd PMOS, resistance RF, electric capacity C2；It is described
The grid of 3rd NMOS tube is connected with the grid of the 3rd PMOS, and the grid of the 3rd NMOS tube is also connected with electric capacity C2 first ends,
The ends of electric capacity C2 second eliminate the input of level as noise；First end of the grid of 3rd NMOS tube also with resistance RF is connected, electricity
The second end for hindering RF is connected with the drain electrode of the 3rd NMOS tube；3rd NMOS tube source electrode connects external voltage, the 3rd NMOS tube drain electrode
Also it is connected with the drain electrode of the 3rd PMOS and the output end of level is eliminated collectively as noise；3rd PMOS source ground.
Further, the N trap width W of the 3rd NMOS tuben3With the p-well width W of the 3rd PMOSp3Pass through 2 bit numbers
Position control.
Beneficial effects of the present invention：A kind of broadband linear CMOS amplifier circuit in low noise of the present invention, includes
Noise on common-gate input stage, amplifying stage and secondary path on main path eliminates level, and load stage；Radiofrequency signal is through master
Exported after the amplification of path and secondary path at load resistance；Non-linear property of the application using digital control technology to circuit
The three rank skew compensation effects for obtaining broadband can be tuned；And the amplifier circuit in low noise of the application is CMOS complementary pairs
Structure is claimed to improve second-order linearity degree；The amplifier circuit in low noise of the present invention in the case where maintaining certain gain and noise figure,
LNA wide-band linearity degree can be significantly improved.
Brief description of the drawings
Fig. 1 is existing multiple-gate transistor (MGTR) amplifier circuit diagram；
Fig. 2 is existing postdistortion amplifier circuit theory diagrams；
Fig. 3 is a kind of schematic diagram of broadband linear CMOS amplifier circuit in low noise of the present invention；
Fig. 4 is a kind of gain results curve of broadband linear CMOS amplifier circuit in low noise of the present invention；
Fig. 5 is a kind of broadband linear CMOS amplifier circuit in low noise noise result curve of the present invention；
Fig. 6 is a kind of wide-band linearity degree result figure of broadband linear CMOS low-noise amplifiers of the present invention.
Embodiment
For ease of skilled artisan understands that the technology contents of the present invention, enter one to present invention below in conjunction with the accompanying drawings
Step explaination.
It is the amplifier circuit diagram of the application as shown in Figure 1, the technical scheme of the application is：A kind of broadband linear
CMOS amplifier circuit in low noise, using CMOS mutual symmetry structures, including：Common-gate input stage, noise eliminate level, amplifying stage with
And load stage；The input termination radiofrequency signal of common-gate input stage, the first of the first output termination amplifying stage of common-gate input stage are defeated
Enter end, the second input of the second output termination amplifying stage of common-gate input stage；The input of the output termination load stage of amplifying stage
End；Noise eliminates the input termination radio-frequency input signals of level；Noise eliminates the input of the output termination load stage of level, load stage
Output end exports amplified signal.
Common-gate input stage includes：First NMOS tube Mn1, the first PMOS Mp1, resistance Rgp, resistance Rgn, electric capacity C1, electricity
Hold C3；Signal source Vs one end be grounded, the other end via a resistance Rs and capacitance C4 be used as radio-frequency input signals, Mp1 with
Both Mn1 source electrode is connected to X points with radio-frequency input signals, and Mp1 grid is connected to voltage Vbp1, Mn1 grid connection
In voltage Vbn1；Mp1 drain is grounded (GND) by resistance Rgp, and Mp1 drain is also connected to Mn3 grid by electric capacity C3
Pole；Mn1 drain is also connected to Mp3 grid by resistance Rgn connections VDD, Mn1 drain by electric capacity C1.
Amplifying stage includes：Both second NMOS tube Mn3, the second PMOS Mp3, Mn3 and Mp3 drain are connected to Y points.
Mp3 source electrode connects VDD, and Vbp3 is connected by a resistance with Mp3 grid；Mn3 source ground (GND), Vbn3 leads to
A resistance is crossed with Mn3 grid to be connected.
Noise, which eliminates level, to be included：3rd NMOS tube Mn2, the 3rd PMOS Mp2, resistance RF, electric capacity C2；Both Mp2 and Mn2
Grid link together, and pass through an electric capacity C2 connection radio-frequency input signals；Mp2 source electrode connects an applied voltage,
Mn2 source ground；Mp2 and both Mn2 drain is linked together, and the output end of level is eliminated as noise；In Mp2 and Mn2
A resistance RF is concatenated between both grid and drain.
Load stage is made up of an electric capacity CL, resistance RL.The level is connected to Y points, passes sequentially through an electric capacity CL, low noise
Put load resistance RL and be connected to ground, the amplified signal through main path and secondary path exports at load resistance.
Amplifier circuit in low noise proposed by the present invention, second order coefficient of torsion is compensated using CMOS mutual symmetries structure,
And use numerically controlled bias voltage (Vbn1、Vbp1) and pipe sizing (Wn3&Wp3) carry out broadband range in the linearity tuning
Optimization.By by complementary transistor be equivalent to Darlington analyzed it is equivalent, with the performance evaluation of simple and convenient circuit.Tool
Body：
Wherein, gmni、gmpi、gmiTransistor M is represented respectivelyni、Mpi, Darlington MiMutual conductance (i takes 1~3)；g′mni,
g′mpi,g′mi,g″mni,g″mpi,g″miRepresent transistor Mni、Mpi, Darlington MiSingle order, second order transconductance derivatives.
According to Circuit theory, the output signal electric current i of circuit of the present inventionoInput signal vs non-linear letter can be expressed as
Number：
Firstly, since complementary technology can eliminate second nonlinear significantly, so the g ' inside formulamiContinuous item approximation is neglected
Slightly.Secondly because the third-order non-linear opposite polarity of the transistor AND gate strong inversion transistor in weak inversion regime, and second nonlinear
Polarity is identical.Therefore, amplifying stage transistor M is adjustedn3/Mp3Size can offset noise and eliminate level transistor Mn2/Mp2Three ranks it is non-
Linearly.I.e. Section 2 is eliminated in formula (5).Based on this principle, amplifier can be obtained at single frequency point high IIP3,
The IIP2 linearities.Again, with the increase of frequency, non-linear cancel each other of Section 2 can deteriorate in formula (5).Reason exists
In the non-linear vector polarity rotation that main path, secondary path ghost effect are brought.Now, the rank of Section 4 three in formula (5) is passed through
The introducing of nonlinear terms, frequency dependence compensation deviation caused by Section 2 can be compensated.By controlling Vbn1&Vbp1,
The third-order non-linear of Section 4 is tuned.
Emulation shows, changes Mn3and Mp3Size can further obtain the wide-band linearity degree performance of optimization.Specifically, 4
The V of bit controlbn1：1.5/1.525/1.55/1.57-V the V of 4 bits controlbp1：0.2/0.24/0.27/0.3-V.2 bits
The W of controln3&Wp3Respectively 20/25,70/80- μm, channel length is 0.18- μm.On the other hand in the present invention, in formula (5)
The third-order non-linear item of introducing prevents the noise of the input transistors of circuit from being completely eliminated, but emulation shows, the present invention
The increased noise that circuit uses, which eliminates level mutual conductance, can still obtain the overall low noise of circuit；Specially：
The application LNA (low-noise amplifier) circuit is realized using 0.18 μm of rf CMOS technology.In 1.8V supply voltages
Under, chip bias current is 10.6mA.The voltage gain curve of secondary path closure (Aux.on) is S11, and secondary path disconnects
(Aux.off) voltage gain curve is S12, as shown in figure 4, S11<10dB band a width of 0.1 arrives 1.4GHz, LNA voltage
Gain has reached 16.1dB.Fig. 5 gives noise figure result, in 0.1 to 1.4GHz. frequency ranges, the application curve
Noise figure is 2.8~3.4dB, and after secondary path disconnects, noise degenerates to 8dB or so.
The offset change brought further for digital control word, caused gain, noise penalty be respectively smaller than 0.8,
0.4dB.Linearity emulation is carried out using the test signal of constant amplitude double-tone, and IIP2, IIP3 double-tone spacing be respectively 100,
10MHz.As shown in fig. 6, IIP3 and IIP2 is followed successively by 13~18.9,24~40dBm in the bandwidth range of design.For in figure
500MHz point frequency optimum results, it is V to control variable corresponding to respective digital control wordbn1&Vbp1:1.5、0.3V；Wn3&Wp3:
25、80um.It can be seen that the LNA circuits of the application achieve good broadband IIP3 and IIP2 performance.
Frequency in Fig. 4-6 represents frequency.
One of ordinary skill in the art will be appreciated that embodiment described here is to aid in reader and understands this hair
Bright principle, it should be understood that protection scope of the present invention is not limited to such especially statement and embodiment.For ability
For the technical staff in domain, the present invention can have various modifications and variations.Within the spirit and principles of the invention, made
Any modification, equivalent substitution and improvements etc., should be included within scope of the presently claimed invention.
Claims (6)
- A kind of 1. broadband linear CMOS amplifier circuit in low noise, it is characterised in that including：Common-gate input stage, noise eliminate Level, amplifying stage and load stage；The input termination radiofrequency signal of common-gate input stage, the first output termination amplification of common-gate input stage The first input end of level, the second input of the second output termination amplifying stage of common-gate input stage；The output termination of amplifying stage is negative Carry the input of level；Noise eliminates the input termination radio-frequency input signals of level；Noise eliminates the defeated of the output termination load stage of level Enter, the output end output amplified signal of load stage.
- 2. a kind of broadband linear CMOS amplifier circuit in low noise according to claim 1, it is characterised in that described common Grid input stage includes：First NMOS tube, the first PMOS, resistance Rgp, resistance Rgn, electric capacity C1, electric capacity C3；First NMOS The input that the source electrode of pipe is connected collectively as common-gate input stage with the source electrode of the first PMOS, and connect and penetrated by capacitance C4 Frequency signal；The drain electrode of first NMOS tube meets power supply V by resistance RgnDD；The drain electrode of first NMOS tube also with electric capacity C1 first end phases Even, first output end of electric capacity C1 the second end as common-gate input stage；The drain electrode of first PMOS is grounded by resistance Rgp； First end of the drain electrode of first PMOS also with electric capacity C3 is connected, and electric capacity C3 the second end exports as the second of common-gate input stage End；The grid of first NMOS tube meets voltage Vbn1；The grid of first PMOS meets voltage Vbp1.
- A kind of 3. broadband linear CMOS amplifier circuit in low noise according to claim 2, it is characterised in that the electricity Pressure Vbn1 and voltage Vbp1 is controlled by 4 bit numerical digits.
- 4. a kind of broadband linear CMOS amplifier circuit in low noise according to claim 1, it is characterised in that described to put Big level includes：Second NMOS tube, the second PMOS, the first input end of the grid of second NMOS tube as amplifying stage；The The source electrode connection power supply V of two NMOS tubesDD；The drain electrode of second NMOS tube is connected collectively as amplifying stage with the drain electrode of the second PMOS Output end；Second input of the grid of second PMOS as amplifying stage；The source ground of second PMOS；Described second The grid of NMOS tube also meets voltage Vbn3, and the grid of the second PMOS also meets voltage Vbp3.
- 5. a kind of broadband linear CMOS amplifier circuit in low noise according to claim 1, it is characterised in that described to make an uproar Sound, which eliminates level, to be included：3rd NMOS tube, the 3rd PMOS, resistance RF, electric capacity C2；The grid and the 3rd of 3rd NMOS tube The grid of PMOS is connected, and the grid of the 3rd NMOS tube is also connected with electric capacity C2 first ends, and the ends of electric capacity C2 second disappear as noise Except the input of level；First end of the grid of 3rd NMOS tube also with resistance RF is connected, resistance RF the second end and the 3rd NMOS Pipe drain electrode is connected；3rd NMOS tube source electrode connects external voltage, and the 3rd NMOS tube drain electrode is also connected with the drain electrode of the 3rd PMOS The output end of level is eliminated collectively as noise；3rd PMOS source ground.
- 6. a kind of broadband linear CMOS amplifier circuit in low noise according to claim 1, it is characterised in that described The N trap width W of three NMOS tubesn3With the p-well width W of the 3rd PMOSp3Controlled by 2 bit numerical digits.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110149096A (en) * | 2019-06-18 | 2019-08-20 | 杭州中科微电子有限公司 | A kind of low-noise amplifier of high linearity |
| CN112188125A (en) * | 2020-10-13 | 2021-01-05 | 成都微光集电科技有限公司 | Noise cancellation circuit and image sensor |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120013404A1 (en) * | 2010-07-13 | 2012-01-19 | Entropic Communications, Inc. | Method and Apparatus for Broadband Input Matching with Noise and Non-Linearity Cancellation in Power Amplifiers |
| CN103117712A (en) * | 2013-01-29 | 2013-05-22 | 天津大学 | Complementary metal-oxide-semiconductor (CMOS) high gain broad band low noise amplifier |
| CN103618503A (en) * | 2013-12-18 | 2014-03-05 | 上海艾为电子技术有限公司 | Amplifier circuit and control circuit and control method thereof |
| CN103780207A (en) * | 2012-10-22 | 2014-05-07 | 上海华虹宏力半导体制造有限公司 | Cmos radio frequency power amplifier |
| CN104539244A (en) * | 2014-12-23 | 2015-04-22 | 天津大学 | Distortion and noise cancellation based high-linearity CMOS broadband low noise amplifier |
| CN104935264A (en) * | 2015-06-02 | 2015-09-23 | 电子科技大学 | Inductor-free wideband low-noise transconductance amplifier |
| CN105262443A (en) * | 2015-11-12 | 2016-01-20 | 电子科技大学 | High-linearity low-noise transconductance amplifier |
| US9444410B1 (en) * | 2015-05-19 | 2016-09-13 | AltoBeam Inc. | Wide-band single-ended-to-differential low-noise amplifier using complementary push-pull structure |
| CN107070425A (en) * | 2017-05-27 | 2017-08-18 | 苏州大学 | Broadband low-power consumption low-noise amplifier applied to wireless sensor network |
-
2017
- 2017-09-21 CN CN201710858969.6A patent/CN107579715B/en not_active Expired - Fee Related
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120013404A1 (en) * | 2010-07-13 | 2012-01-19 | Entropic Communications, Inc. | Method and Apparatus for Broadband Input Matching with Noise and Non-Linearity Cancellation in Power Amplifiers |
| CN103780207A (en) * | 2012-10-22 | 2014-05-07 | 上海华虹宏力半导体制造有限公司 | Cmos radio frequency power amplifier |
| CN103117712A (en) * | 2013-01-29 | 2013-05-22 | 天津大学 | Complementary metal-oxide-semiconductor (CMOS) high gain broad band low noise amplifier |
| CN103618503A (en) * | 2013-12-18 | 2014-03-05 | 上海艾为电子技术有限公司 | Amplifier circuit and control circuit and control method thereof |
| CN104539244A (en) * | 2014-12-23 | 2015-04-22 | 天津大学 | Distortion and noise cancellation based high-linearity CMOS broadband low noise amplifier |
| US9444410B1 (en) * | 2015-05-19 | 2016-09-13 | AltoBeam Inc. | Wide-band single-ended-to-differential low-noise amplifier using complementary push-pull structure |
| CN104935264A (en) * | 2015-06-02 | 2015-09-23 | 电子科技大学 | Inductor-free wideband low-noise transconductance amplifier |
| CN105262443A (en) * | 2015-11-12 | 2016-01-20 | 电子科技大学 | High-linearity low-noise transconductance amplifier |
| CN107070425A (en) * | 2017-05-27 | 2017-08-18 | 苏州大学 | Broadband low-power consumption low-noise amplifier applied to wireless sensor network |
Non-Patent Citations (3)
| Title |
|---|
| HARUHIKO KUWATSUKA等: ""Enhancement of Third-Order Nonlinear Optical Susceptibilities in Compressively Strained Quantum Wells Under the Population Inversion Condition"", 《IEEE JOURNAL OF QUANTUM ELECTRONICS》 * |
| 安士全等: ""一种小型化超宽带功率放大器的设计"", 《中国电子科学研究院学报》 * |
| 曹克等: ""一个利用线性区MOS管补偿的射频放大器"", 《固体电子学研究与进展》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110149096A (en) * | 2019-06-18 | 2019-08-20 | 杭州中科微电子有限公司 | A kind of low-noise amplifier of high linearity |
| CN112188125A (en) * | 2020-10-13 | 2021-01-05 | 成都微光集电科技有限公司 | Noise cancellation circuit and image sensor |
| CN112188125B (en) * | 2020-10-13 | 2023-02-17 | 成都微光集电科技有限公司 | Noise cancellation circuit and image sensor |
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