CN104539244A - Distortion and noise cancellation based high-linearity CMOS broadband low noise amplifier - Google Patents

Abstract

The invention discloses a distortion and noise cancellation based high-linearity CMOS broadband low noise amplifier. The distortion and noise cancellation based high-linearity CMOS broadband low noise amplifier structurally comprises a distortion cancellation input stage and a noise cancellation output stage. The distortion cancellation input stage serves as a first stage of the low noise amplifier, input impedance matching and second-order cross modulation IMD2 cancellation are achieved by adopting CMOS complementary common-gate combination, meanwhile a complementary structure has the characteristic of current reuse, and accordingly power consumption is reduced. The noise cancellation output stage serves as a second stage and is mainly used for cancelling channel thermal noise current of two common-gate devices at the first stage and accordingly reducing the noise coefficient of a whole circuit. The distortion and noise cancellation based high-linearity CMOS broadband low noise amplifier can simultaneously achieve high linearity and low noise coefficient within a broadband range, and meanwhile gives consideration to other design parameters, such as input impedance matching, power gain and power consumption.

Description

Based on the high linearity CMOS wideband low noise amplifier of distortion and noise cancellation

Technical field

The present invention is technical field of radio frequency integrated circuits, is specifically related to a kind of CMOS wideband low noise amplifier (LNA) simultaneously adopting distortion and noise cancellation technique.

Background technology

Along with continuing to bring out of the mobile communication technologies such as 3G/4G, be that the wireless transmit-receive technology of representative is just obtaining unprecedented development with frequency microwave.Be different from ripe Generation Mobile Telecommunication System equipment, current mobile communication terminal is just trending towards integrated multiple communication standard and is realizing enjoying mutually in real time of information to meet network seamless link, and such as smart mobile phone can apply GSM, WCDMA, WIFI and RFTV etc.Traditional solution realizes many standard traffics based on by the path parallel connection of multiple arrowband, and this scheme often takies large chip area and has stability problem, lacks reconfigurability.Radio frequency transceiver based on Wideband module is attracting the attention of increasing researcher, and it uses single Wideband module to cover above-mentioned whole communication standard or part of standards.

As first radio frequency active module of wireless receiver, low noise amplifier plays very key effect in whole wireless system.The small-signal received from antenna, first through frequency band acceptance filter, is then carried out first time by low noise amplifier and is amplified, then delivers to rear class radio-frequency module and baseband circuit processes.In order to ensure the correct processing signals of post-module energy, low noise amplifier itself must introduce alap noise, meets input resistant matching, suitable gain and certain linearity simultaneously.The challenge of a design wideband low noise amplifier is to meet above-mentioned designing requirement in a very wide frequency band range.Owing to containing the different radiofrequency signal of multiple power in broad frequency range, between these signals, very easily there is intermodulation and intermodulation, thus destroy useful signal in a certain sub-band, affect signal transmission quality.So meet low noise and high linearity in broadband simultaneously, to become wideband low noise amplifier design successfully crucial.

Integrated circuit based on CMOS technology has high integration and low-power consumption consumption, selected by the mainstay having become current integrated circuit.Along with CMOS technology is constantly towards deep-submicron future development, MOS device just more and more meets the design requirement of radio frequency integrated circuit.Under current techniques, the cut-off frequency of 0.18 μm of technique MOS device can reach about 30GHz, and can meet the needs of below 10GHz radio circuit design, relevant report is as list of references [1] [2] [3].Such as, but the reduction of size is along with the appearance of device higher-order effect, and non-linear leakage output conductance, Velocity saturation effect, mobility decay and multiple-grid to exhaust etc. that constantly to make cmos circuit design more complicated.

As radio frequency integrated circuit common component, inductance is another key factor of limiting circuit performance always.On sheet, the Q value of integrated inductor limited (being generally less than 10) is not well positioned to meet arrowband coupling, frequency-selecting demand, and manufacturer generally do not provide inductor models or the model accuracy that provides very low; Oneself design one piece of on-chip inductor often needs the design software by specialty, as the HFSS software etc. of Ansoft company, these softwares often need to consume a large amount of computer resource and designer possesses certain use experience, and these factors above greatly limit the development of radio frequency integrated circuit.In addition, the supply voltage of integrated circuit is also continuous to decline along with process decline, and this makes circuit design more challenging.

List of references:

[1]Federico Bruccoleri,Eric A.M.Klumperink,,and Bram Nauta,“Wide-Band CMOSLow-Noise Amplifier Exploiting Thermal Noise Canceling,”IEEE J.Solid-State Circuits,vol.39,pp.275-282,Feb.2004。

[2]C.-F.Liao and S.I.Liu,“A broadband noise-canceling MOS LNA for 3.1–10.6-GHzUWB receiver,”IEEE J.Solid-State Circuits,vol.42,no.2,pp.329–339,Feb.2007。

[3]A.Bevilacqua and A.M.Niknejad,“An ultra-wideband CMOS LNA for 3.1to 10.6GHzwireless receiver,”in IEEE ISSCC Dig.Tech.Papers,pp.382–383,2004。

Summary of the invention

For prior art, a kind of high linearity CMOS wideband low noise amplifier based on distortion and noise cancellation that the present invention proposes is a kind of wideband low noise amplifier.Do not use inductance in the circuit of this amplifier, avoid the problem not being well positioned to meet arrowband coupling, frequency-selecting demand caused because Q value is limited.By two kinds of independently technology: distortion cancellation and noise cancellation technique are used in same circuit, thus high linearity and low noise under achieving broadband, take into account Input matching, power gain and power consumption parameter simultaneously.Amplifier of the present invention adopts CMOS 0.18 μm of technique to realize, and design has reproducibility.

In order to solve the problems of the technologies described above, a kind of technical scheme be achieved based on the high linearity CMOS wideband low noise amplifier of distortion and noise cancellation of the present invention is: this amplifier is divided into two-stage, comprise the distortion cancellation input stage of the first order and the noise cancellation output stage of the second level, wherein: described distortion cancellation input stage is made up of resistance R1, NMOS tube M1a, PMOS M1b, resistance R2 and coupling capacitance C1 and coupling capacitance C2, and wherein NMOS tube M1a and PMOS M1b constitutes complementary common gate structure; Described noise cancellation output stage is made up of resistance R3, electric capacity C3 and nmos pass transistor M2, nmos pass transistor M3 and nmos pass transistor M4, described nmos pass transistor M2 and nmos pass transistor M3 is used for realizing noise cancellation, the input that exports to that described nmos pass transistor M4 is used for this amplifier circuit is isolated, and resistance R3 is for realizing the output impedance coupling of this amplifier.

Annexation between above-mentioned each components and parts is: signal enters this amplifier circuit and is divided into two-way:

The source electrode access of one route NMOS tube M1a and PMOS M1b, above-mentioned NMOS tube M1a is connected with the source electrode of PMOS M1b; The grid of NMOS tube M1a is connected to direct voltage VB1, the grid of PMOS M1b is connected to direct voltage VB2; The drain electrode of NMOS tube M1a is connected to one end of resistance R1, and the other end of resistance R1 is connected to power vd D, the drain electrode connecting resistance R2 of PMOS M1b, and the other end of resistance R2 holds GND with being connected to; The drain electrode of NMOS tube M1a is connected to electric capacity C1, and the drain electrode of PMOS M1b is connected to electric capacity C2, and electric capacity C1 is connected with the other end of electric capacity C2 and is together connected to the grid of NMOS tube M2 in the second level.

Electric capacity C3 is connected to after the source electrode access of another route NMOS tube M1a and PMOS M1b, the other end of electric capacity C3 is connected to the grid of NMOS tube M3, the source electrode of NMOS tube M2 and NMOS tube M3 is held with being connected to, the drain terminal of NMOS tube M2 and NMOS tube M3 is connected to the source electrode of NMOS tube M4, the grid of NMOS tube M4 is connected to direct voltage VB3, the drain terminal of NMOS tube M4 is connected to resistance R3, and the other end of resistance R3 is connected to power vd D; The gate bias voltage of NMOS tube M2 and NMOS tube M3 is realized by two biasing circuits, the grid of consisting of of two biasing circuits: NMOS tube M5 is connected with drain electrode and is connected to resistance R4 and resistance R6, the other end of resistance R4 is connected to power vd D, and the other end of resistance R6 is connected to the grid of NMOS tube M2; The grid of NMOS tube M6 is connected with drain electrode and is connected to resistance R5 and resistance R7, and the other end of resistance R5 is connected to power vd D, and the other end of resistance R7 is connected to the grid of NMOS tube M3.

Compared with prior art, the beneficial effect of amplifier of the present invention is:

(1) noise cancellation technique, distortion cancellation technology and current multiplexing technology combine by the present invention, and can obtain high linearity and low-noise performance, current multiplexing technology is for saving power consumption simultaneously.

(2) use common gate structure to realize broadband Input matching in the present invention, many communication standards can be realized integrated simultaneously, facilitate the wireless multiplex roles of communication terminal to connect.

(3) the present invention adopts deep-submicron 0.18 μm of CMOS technology to realize, and 1.8V low supply voltage is powered, and its power consumption consumption is lower.

(4) device used in the present invention mainly comprises MOS transistor, resistance and electric capacity, and integrated circuit is not containing inductance, thus saving chip area, reduce cost.

(5) realization of the present invention adopts mainstream CMOS processes, can be integrated on same chip, easily realizing system on chip with generally adopting the digital baseband circuit of CMOS technology.

Accompanying drawing explanation

Fig. 1 is the circuit structure block diagram of low noise amplifier of the present invention;

Fig. 2 is noise cancellation technique schematic diagram in the present invention;

Fig. 3 is distortion cancellation technical schematic diagram in the present invention;

Fig. 4 is the complete circuit realization figure of low noise amplifier of the present invention;

Fig. 5 is the biasing circuit realization figure of M2 and M3 in the present invention;

Fig. 6 is the simulation result figure of the S parameter of low noise amplifier of the present invention;

Fig. 7 is power gain and the noise factor simulation result figure of low noise amplifier of the present invention;

Fig. 8 is IP1dB and the IIP3 simulation result figure of low noise amplifier of the present invention;

Embodiment

Below in conjunction with embodiment, the present invention is described in further detail.

As shown in Figure 1, a kind of high linearity CMOS wideband low noise amplifier based on distortion and noise cancellation that the present invention proposes, this amplifier is divided into two-stage, is followed successively by the distortion cancellation input stage of the first order and the noise cancellation output stage of the second level.

The distortion cancellation input stage of the first order is made up of resistance R1, NMOS tube M1a, PMOS M1b, resistance R2 and coupling capacitance C1 and coupling capacitance C2.Wherein, NMOS tube M1a and PMOS M1b constitutes two complementations gate junction structure altogether, and both source electrode points are connected.The advantage of common gate structure is adopted to be to meet wide-band impedance coupling, as follows:

$\begin{array}{c}{R}_{\mathrm{in}}=\frac{R_1+r_{o1a}}{1+g_{m1a}\·r_{o1a}}\left|\right|\frac{R_2+r_{o1b}}{1+g_{m1b}\·r_{o1b}}\\ \≈\frac{1}{g_{m1a}+g_{m1b}}\end{array}---\left(1\right)$

In formula (1), R ₁, R ₂for resistance value, r _o1a, r _o1bfor the output impedance of metal-oxide-semiconductor M1a and M1b, g _m1a, g _m1bfor the mutual conductance of metal-oxide-semiconductor M1a and M1b.

Under the condition of impedance matching, have:

$\frac{1}{g_{m1a}+g_{m1b}}=R_S---\left(2\right)$

In formula (2), g _m1a, g _m1bfor the mutual conductance of metal-oxide-semiconductor M1a and M1b.

Meanwhile, this class reverser PMOS and NMOS combination has bias current multiplexing (Current-reuse) function concurrently, thus saves power.

Concrete distortion cancellation principle is as follows:

The ac leakage stream of a MOS transistor and the relation of gate source voltage can be expressed as:

$i_d=g_1\·v_{\mathrm{gs}}+g_2\·v_{\mathrm{gs}}^2+g_3\·v_{\mathrm{gs}}^3+...---\left(3\right)$

Wherein g1 is first-order linear item, g2 and g3 is respectively second order and third-order non-linear item.Fig. 2 is a single NMOS grid level circuit altogether adopting noise cancellation technique, and its linearity limits by two factors: (1) two-stage circuit intrinsic third order intermodulation item IMD3 separately; (2) first order is total to the second order inter-modulation item IMD2 in grid output.IMD2 from the first order contributes IMD3 by meeting after the amplifying circuit of the second level at output, thus worsens circuit linearity degree.In the present invention, we are total on the basis of grid level at single NMOS and additionally add PMOS grid level circuit altogether, as shown in Figure 3, from the second nonlinear electric current gm2*Vin of NMOS tube Mn and PMOS Mp ²and gp2*Vin ²flow through R1 and R2, produce contrary second nonlinear voltage Vx and Vy of two phase places respectively at X point and Y point.Realize offsetting at the output of the first order finally by two coupling capacitance C1, C2.Meanwhile, two synchronous first-order linear items are enhanced at output.

The noise cancellation level of the described second level is made up of resistance R3 and three nmos pass transistor M2, M3 and M4, and actual noise cancellation function is realized by M2 and M3 respectively.As shown in Figure 2, the channel noise electric current of the common gate transistor M1 of first order circuit flows through R1 and RS respectively, at the noise voltage V that X point is contrary with Y point place's generation two phase places _x, noise and V _y, noise.After electric capacity C1 and C2 is coupled, delivers to the grid of M2 and M3, when meeting following condition, can noise cancellation be realized:

$\begin{array}{c}{R}_1\·(-I_{\mathrm{noise},m1})\·g_{m2}+R_S\·I_{\mathrm{noise},m1}\·g_{m3}=0\\ \⇒\frac{g_{m3}}{g_{m2}}=\frac{R_1}{R_S}\end{array}---\left(4\right)$

In formula (4), R ₁, R _sfor resistance value, g _m2, g _m3for the mutual conductance of metal-oxide-semiconductor M2 and M3, I _{noise, m1}for the channel noise electric current of metal-oxide-semiconductor M1.

Nmos pass transistor M4 and M2 and M3 constitutes cascodes, and this combination has high output impedance.The output impedance Zout of whole circuit is formed by load resistance R3 is in parallel with the output impedance of cascade, is about the resistance of resistance R3, and resistance R3 plays the effect of output impedance coupling, and wherein nmos pass transistor M4 also serves the buffer action exporting input to.

As shown in Figures 1 to 5, the annexation in amplifier circuit of the present invention between each components and parts is: signal enters circuit and is divided into two-way:

The source electrode access of one route NMOS tube M1a and PMOS M1b, above-mentioned NMOS tube M1a is connected with the source electrode of PMOS M1b; The grid of NMOS tube M1a is connected to direct voltage VB1, the grid of PMOS M1b is connected to direct voltage VB2; The drain electrode of NMOS tube M1a is connected to one end of resistance R1, and the other end of resistance R1 is connected to power vd D, the drain electrode connecting resistance R2 of PMOS M1b, and the other end of resistance R2 holds GND with being connected to; The drain electrode of NMOS tube M1a is connected to electric capacity C1, and the drain electrode of PMOS M1b is connected to electric capacity C2, and electric capacity C1 is connected with the other end of electric capacity C2 and is together connected to the grid of NMOS tube M2 in the second level.

As shown in Figure 1 and Figure 4, electric capacity C3 is connected to after the source electrode access of another route NMOS tube M1a and PMOS M1b, the other end of electric capacity C3 is connected to the grid of NMOS tube M3, the source electrode of NMOS tube M2 and NMOS tube M3 is held with being connected to, the drain terminal of NMOS tube M2 and NMOS tube M3 is connected to the source electrode of NMOS tube M4, the grid of NMOS tube M4 is connected to direct voltage VB3, and the drain terminal of NMOS tube M4 is connected to resistance R3, and the other end of resistance R3 is connected to power vd D; The gate bias voltage of NMOS tube M2 and NMOS tube M3 is realized by two biasing circuits.

The composition of two biasing circuits is as shown in Figure 5: the grid of NMOS tube M5 is connected with drain electrode and is connected to resistance R4 and resistance R6, and the other end of resistance R4 is connected to power vd D, and the other end of resistance R6 is connected to the grid of NMOS tube M2; The grid of NMOS tube M6 is connected with drain electrode and is connected to resistance R5 and resistance R7, and the other end of resistance R5 is connected to power vd D, and the other end of resistance R7 is connected to the grid of NMOS tube M3.

Fig. 4 gives complete circuit structure, and wherein Vs is radio-frequency signal source, and resistance RS is genertor impedance, gets 50 Ω, and wherein, RL is load impedance (also getting 50 Ω, the impedance of analog network analyzer Term2).By electric capacity C1, C2 and C3 coupling between two-stage.The channel noise current canceling principle that the PMOS additionally added is total to grid level is identical with the NMOS noise cancellation principle of Fig. 2.Noise cancellation NMOS tube is realized by active electric current mirror the biased of M2 and M3, and as shown in Figure 5, wherein resistance R6, R7 is respectively the noise that large resistance (M Ω level) produces for isolating bias current mirror.Bias voltage VB1, VB2 and VB3 can provide by sheet or outside sheet respectively, and in the present invention, for the sake of simplicity and avoid process deviation to cause variation, above-mentioned three voltages VB1, VB2 and VB3 are provided by same simple resistor bleeder circuit.Finally, device gain can be amplified by simple circuit analysis.Notice and divide a two-way to enter circuit after input signal is connected to the source electrode of NMOS tube M1a and PMOS M1b, wherein a road directly enters complementary common gate structure respectively by the grid being coupled to M2 after X, Y, its signal phase and input signal homophase; Electric capacity C3 of separately leading up to couples directly to the grid of M3, to exporting after the second level is amplified, in turn enhances signal like this while realizing noise cancellation,

A _v＝[(g _m1b·R ₁+g _m1a·R ₂)·g _m2+g _m3]·R ₃(5)

In formula (5), R ₁, R ₂, R ₃for resistance value, g _m1a, g _m1bfor the mutual conductance of metal-oxide-semiconductor M1a and M1b, g _m2, g _m3for the mutual conductance of metal-oxide-semiconductor M2 and M3.

As shown in Figure 4, the present invention adopts distortion and noise cancellation technique to realize CMOS wideband low noise amplifier, comprises distortion cancellation input stage and noise cancellation output stage.Described distortion cancellation input stage is made up of resistance R1, NMOS tube M1a, PMOS M1b and resistance R2, wherein PMOS M1b and NMOS tube M1a constitutes a current multiplexing structure, and the gate bias voltage of above-mentioned NMOS tube M1a and PMOS M1b is provided by simple resistor voltage divider circuit.

Concrete distortion cancellation function is completed by above-mentioned four elements, the second order inter-modulation item IMD2 that the second nonlinear item of namely offsetting gate device generation altogether produces at first order output.Described noise cancellation output stage is made up of resistance R3 and three nmos pass transistor M2, M3 and M4, concrete noise cancellation function is completed by nmos pass transistor M2 and M3, namely the channel noise electric current that the first order is total to gate transistor is offset, because this noise source accounts for the largest percentage in overall noise coefficient.Nmos pass transistor M4 is for realizing the isolation exporting input to.Realize signal coupling by electric capacity C1, C2 and C3 between above-mentioned two-layer configuration, the bias voltage of second level entering apparatus nmos pass transistor M2 and M3 is realized by one group of active electric current mirror, and physical circuit is shown in Fig. 5.The gate bias voltage of NMOS tube M4 is realized by resistor voltage divider circuit, and in order to save extra power consumption and keep process consistency, metal-oxide-semiconductor M1a, M1b and M4 share a resistor voltage divider circuit.In addition, conveniently with the test of the network analyzer of 50 Ω internal resistances, load resistance R3 about gets 50 Ω.

Embodiment:

The present embodiment adopts circuit structure shown in Fig. 4, and circuit design, based on CHRT 0.18 μm of RFCMOS 1P6M technique, uses the emulation of Cadence SpectreRF instrument.Supply voltage VDD is 1.8V, and working frequency range is at 0.1 ~ 1.6GHz.

For the standard radio frequency system of 50 Ω, the input impedance of CMOS wideband low noise amplifier LNA should meet (gm1a+gm1b)=20ms, and be compared to single NMOS grid level altogether, this structure can save the bias current of nearly half.

Adopt the biasing circuit of Fig. 5 that M2 and M3 is biased in 0.55V and 0.6V respectively.Resistance R1 and R2 be value 500 Ω respectively, 480 Ω.In order to S22 convenient test, resistance R3 gets 50 Ω.

Fig. 6 gives the simulation result figure of S parameter, and wherein S11, S12 and S22 represent input reflection coefficient, reverse transfer coefficient and output reflection coefficient respectively, from simulation result, in corresponding frequency band, has good Input matching, reaches-27dB at 0.2GHz place; Fig. 7 gives power gain and noise factor, and from simulation result, under above-mentioned working frequency range, the mean value of noise factor is about about 2.4dB, and the maximum gain of circuit is 11.73dB, and three dB bandwidth is from 0.1GHz ~ 1.8GHz; Fig. 8 gives linearity parameter of measurement third order intermodulation point IIP3 and the variation tendency of 1dB compression point IP1dB under above-mentioned operating frequency, can see that IIP3 excursion changes near about-5dBm from-2 ~ 9.14dBm, IP1dB.The power consumption of integrated circuit is 19.8mW.These results illustrate that the present invention obtains high linearity at the same time, low noise aspect has great advantage, and also have good performance in Input matching, power gain.

Although invention has been described for composition graphs above; but the present invention is not limited to above-mentioned embodiment; above-mentioned embodiment is only schematic; instead of it is restrictive; those of ordinary skill in the art is under enlightenment of the present invention; when not departing from present inventive concept, utilize technology provided by the invention can also make a lot of distortion, these all belong within protection of the present invention.

Claims (1)

1., based on a high linearity CMOS wideband low noise amplifier for distortion and noise cancellation, it is characterized in that, this amplifier is divided into two-stage, comprises the distortion cancellation input stage of the first order and the noise cancellation output stage of the second level, wherein:

Described distortion cancellation input stage is made up of resistance R1, NMOS tube M1a, PMOS M1b, resistance R2 and coupling capacitance C1 and coupling capacitance C2, and wherein NMOS tube M1a and PMOS M1b constitutes complementary common gate structure;

Described noise cancellation output stage is made up of resistance R3, electric capacity C3 and nmos pass transistor M2, nmos pass transistor M3 and nmos pass transistor M4, described nmos pass transistor M2 and nmos pass transistor M3 is used for realizing noise cancellation, the input that exports to that described nmos pass transistor M4 is used for this amplifier is isolated, and resistance R3 is for realizing the output impedance coupling of this amplifier;

Annexation between above-mentioned each components and parts is:

Signal is divided into two-way after entering this amplifier:

The source electrode access of one route NMOS tube M1a and PMOS M1b, above-mentioned NMOS tube M1a is connected with the source electrode of PMOS M1b; The grid of NMOS tube M1a is connected to direct voltage VB1, the grid of PMOS M1b is connected to direct voltage VB2; The drain electrode of NMOS tube M1a is connected to one end of resistance R1, and the other end of resistance R1 is connected to power vd D, the drain electrode connecting resistance R2 of PMOS M1b, and the other end of resistance R2 holds GND with being connected to; The drain electrode of NMOS tube M1a is connected to electric capacity C1, and the drain electrode of PMOS M1b is connected to electric capacity C2, and electric capacity C1 is connected with the other end of electric capacity C2 and is together connected to the grid of NMOS tube M2 in the second level;

Electric capacity C3 is connected to after the source electrode access of another route NMOS tube M1a and PMOS M1b, the other end of electric capacity C3 is connected to the grid of NMOS tube M3, the source electrode of NMOS tube M2 and NMOS tube M3 is held with being connected to, the drain terminal of NMOS tube M2 and NMOS tube M3 is connected to the source electrode of NMOS tube M4, the grid of NMOS tube M4 is connected to direct voltage VB3, the drain terminal of NMOS tube M4 is connected to resistance R3, and the other end of resistance R3 is connected to power vd D; The gate bias voltage of NMOS tube M2 and NMOS tube M3 is realized by two biasing circuits;

Consisting of of described two biasing circuits:

The grid of NMOS tube M5 is connected with drain electrode and is connected to resistance R4 and resistance R6, and the other end of resistance R4 is connected to power vd D, and the other end of resistance R6 is connected to the grid of NMOS tube M2; The grid of NMOS tube M6 is connected with drain electrode and is connected to resistance R5 and resistance R7, and the other end of resistance R5 is connected to power vd D, and the other end of resistance R7 is connected to the grid of NMOS tube M3.