CN104539244A - Distortion and noise cancellation based high-linearity CMOS broadband low noise amplifier - Google Patents

Abstract

The invention discloses a high-linearity CMOS wideband low-noise amplifier based on distortion and noise cancellation, the structure of which includes a distortion cancellation input stage and a noise cancellation output stage. The distortion cancellation input stage is the first stage of the low noise amplifier. It adopts CMOS complementary common gate combination to realize input impedance matching and second-order intermodulation IMD2 cancellation. At the same time, the complementary structure has the characteristics of current multiplexing to save power consumption. The second stage is the noise cancellation output stage, the main purpose is to offset the channel thermal noise current of the two common gate devices in the first stage, thereby reducing the noise figure of the whole circuit. The present invention can simultaneously realize high linearity and low noise figure within a wide band range, while taking into account other design parameters, such as input impedance matching, power gain, power consumption, and the like.

Description

High Linearity CMOS Broadband Low Noise Amplifier Based on Distortion and Noise Cancellation

technical field

The invention belongs to the technical field of radio frequency integrated circuits, and in particular relates to a CMOS broadband low-noise amplifier (LNA) which simultaneously adopts distortion and noise canceling technologies.

Background technique

With the continuous emergence of mobile communication technologies such as 3G/4G, wireless transceiver technology represented by radio frequency microwave is developing unprecedentedly. Different from the mature second-generation mobile communication devices, the current mobile communication terminals are tending to integrate multiple communication standards to meet the seamless connection of the network to realize real-time sharing of information. For example, smart phones can use GSM, WCDMA, WIFI and RFTV wait. Traditional solutions are based on paralleling multiple narrowband paths to achieve multi-standard communication. This solution often occupies a large chip area and has stability problems and lacks reconfigurability. Wideband module-based RF transceivers are attracting more and more researchers' attention, which cover all or some of the above-mentioned communication standards with a single wideband module.

As the first RF active module of a wireless receiver, a low noise amplifier plays a key role in the entire wireless system. The weak signal received from the antenna first passes through the band-pass filter, and then is first amplified by the low-noise amplifier, and then sent to the subsequent RF module and baseband circuit for processing. In order to ensure that the post-stage module can process signals correctly, the low-noise amplifier itself must introduce as low noise as possible, while satisfying input impedance matching, appropriate gain, and certain linearity. The challenge in designing a wideband LNA is to meet the above design requirements over a wide frequency band. Since there are a variety of radio frequency signals with different strengths in the wide frequency range, intermodulation and intermodulation between these signals are very easy to occur, thereby destroying useful signals in a certain sub-band and affecting the quality of signal transmission. Therefore, satisfying both low noise and high linearity within a wide band has become the key to the successful design of a wide band LNA.

Integrated circuits based on CMOS technology have high integration and low power consumption, and have become the mainstream design choice for integrated circuits today. With the continuous development of CMOS technology towards deep submicron, MOS devices are increasingly meeting the design requirements of radio frequency integrated circuits. Under the current technology, the cut-off frequency of 0.18μm process MOS devices can reach about 30GHz, which can already meet the needs of RF circuit design below 10GHz. Related reports can be found in references [1][2][3]. However, the reduction in size is accompanied by the emergence of higher-order effects of devices, such as nonlinear drain-output conductance, velocity saturation effects, mobility decay, and multi-gate depletion, which continue to complicate CMOS circuit design.

As a common component of radio frequency integrated circuits, inductance has been another important factor limiting circuit performance. The Q value of the on-chip integrated inductor is limited (generally less than 10), which cannot well meet the needs of narrowband matching and frequency selection, and manufacturers generally do not provide inductor models or the accuracy of the models provided is very low; designing an on-chip inductor by yourself often requires the help of Professional design software, such as Ansoft's HFSS software, etc., these software often need to consume a lot of computer resources and designers have a certain experience in use, these factors limit the development of radio frequency integrated circuits to a large extent. In addition, the power supply voltage of integrated circuits continues to decrease as the process size decreases, which makes circuit design more and more challenging.

references:

[1] Federico Bruccoleri, Eric A.M. Klumperink,, and Bram Nauta, "Wide-Band CMOS Low-Noise Amplifier Exploiting Thermal Noise Canceling," IEEE J.Solid-State Circuits, vol.39, pp.275-282, Feb.2004 .

[2] C.-F.Liao and S.I.Liu, "A broadband noise-canceling MOS LNA for 3.1–10.6-GHz UWB receiver," IEEE J.Solid-State Circuits, vol.42, no.2, pp.329– 339, Feb. 2007.

[3] A.Bevilacqua and A.M.Niknejad, "An ultra-wideband CMOS LNA for 3.1to 10.6GHz wireless receiver," in IEEE ISSCC Dig.Tech.Papers,pp.382–383,2004.

Contents of the invention

Aiming at the prior art, the invention proposes a high-linearity CMOS broadband low-noise amplifier based on distortion and noise cancellation, which is a broadband low-noise amplifier. The circuit of the amplifier does not use an inductance, which avoids the problem that the narrow-band matching and frequency selection requirements cannot be well met due to the limited Q value. Two independent techniques: Distortion Cancellation and Noise Cancellation are used in the same circuit to achieve high linearity and low noise in wideband while taking into account input matching, power gain and power consumption parameters. The amplifier of the present invention is realized by a CMOS 0.18μm process, and the design is reproducible.

In order to solve the above-mentioned technical problems, a kind of high-linearity CMOS broadband low-noise amplifier based on distortion and noise cancellation of the present invention realizes the technical scheme as follows: the amplifier is divided into two stages, including the distortion cancellation input stage of the first stage and the second stage The noise canceling output stage of the stage, wherein: the distortion canceling input stage is composed of a resistor R1, an NMOS transistor M1a, a PMOS transistor M1b, a resistor R2, a coupling capacitor C1, and a coupling capacitor C2, wherein the NMOS transistor M1a and the PMOS transistor M1b form a complementary common gate structure; the noise cancellation output stage is composed of a resistor R3, a capacitor C3, an NMOS transistor M2, an NMOS transistor M3 and an NMOS transistor M4, the NMOS transistor M2 and the NMOS transistor M3 are used to implement noise cancellation, and the NMOS transistor M4 Used for output-to-input isolation of the amplifier circuit, resistor R3 is used to achieve output impedance matching of the amplifier.

The connection relationship between the above components is: the signal entering the amplifier circuit is divided into two paths:

One route is connected to the sources of the NMOS transistor M1a and the PMOS transistor M1b, and the sources of the NMOS transistor M1a and the PMOS transistor M1b are connected; the gate of the NMOS transistor M1a is connected to the DC voltage VB1, and the gate of the PMOS transistor M1b is connected to the DC voltage VB2; the drain of the NMOS transistor M1a is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the power supply VDD, the drain of the PMOS transistor M1b is connected to the resistor R2, and the other end of the resistor R2 is connected to the ground terminal GND; the NMOS transistor M1a The drain is connected to the capacitor C1, the drain of the PMOS transistor M1b is connected to the capacitor C2, the capacitor C1 and the other end of the capacitor C2 are connected together and connected to the gate of the NMOS transistor M2 in the second stage.

Another route connects the sources of the NMOS transistor M1a and the PMOS transistor M1b to the capacitor C3, the other end of the capacitor C3 is connected to the gate of the NMOS transistor M3, and the sources of the NMOS transistor M2 and the NMOS transistor M3 are connected to the ground terminal. The drains of the NMOS transistor M2 and the NMOS transistor M3 are connected to the source of the NMOS transistor M4, the gate of the NMOS transistor M4 is connected to the DC voltage VB3, the drain of the NMOS transistor M4 is connected to the resistor R3, and the other end of the resistor R3 is connected to the power supply VDD; the gate bias voltage of NMOS transistor M2 and NMOS transistor M3 is realized by two bias circuits, and the composition of the two bias circuits is: the gate of NMOS transistor M5 is connected to the drain and connected to resistor R4 and resistor R6 , the other end of resistor R4 is connected to the power supply VDD, the other end of resistor R6 is connected to the gate of NMOS transistor M2; the gate of NMOS transistor M6 is connected to the drain and connected to resistor R5 and resistor R7, and the other end of resistor R5 is connected to to the power supply VDD, and the other end of the resistor R7 is connected to the gate of the NMOS transistor M3.

Compared with prior art, the beneficial effect of amplifier of the present invention is:

(1) The present invention combines noise cancellation technology, distortion cancellation technology and current multiplexing technology to obtain high linearity and low noise performance at the same time, and the current multiplexing technology is used to save power consumption.

(2) In the present invention, a common gate structure is used to realize broadband input matching, which can realize the integration of multiple communication standards at the same time, and facilitate wireless multi-interface connection of communication terminals.

(3) The present invention is realized by using a deep submicron 0.18 μm CMOS process, powered by a low power supply voltage of 1.8V, and its power consumption is relatively low.

(4) The devices used in the present invention mainly include MOS transistors, resistors and capacitors, and the overall circuit does not contain inductors, thereby saving chip area and reducing costs.

(5) The realization of the present invention adopts the mainstream CMOS technology, and can be integrated on the same chip with the digital baseband circuit generally adopting the CMOS technology, and it is easy to realize system-on-chip integration.

Description of drawings

Fig. 1 is the block diagram of the circuit structure of low noise amplifier of the present invention;

Fig. 2 is a schematic diagram of noise cancellation technology in the present invention;

Fig. 3 is a schematic diagram of the distortion cancellation technology in the present invention;

Fig. 4 is the complete circuit realization diagram of the low noise amplifier of the present invention;

Fig. 5 is the bias circuit implementation figure of M2 and M3 among the present invention;

Fig. 6 is the simulation result figure of the S parameter of low noise amplifier of the present invention;

Fig. 7 is the power gain and noise figure simulation result figure of low noise amplifier of the present invention;

Fig. 8 is the IP1dB and IIP3 simulation result figure of low noise amplifier of the present invention;

Detailed ways

The present invention will be further described in detail below in combination with specific embodiments.

As shown in Fig. 1, a kind of high-linearity CMOS broadband low-noise amplifier based on distortion and noise cancellation proposed by the present invention, this amplifier is divided into two stages, and the distortion of the first stage cancels the input stage and the noise of the second stage successively offset output stage.

The distortion canceling input stage of the first stage is composed of resistor R1, NMOS transistor M1a, PMOS transistor M1b, resistor R2, coupling capacitor C1 and coupling capacitor C2. Wherein, the NMOS transistor M1a and the PMOS transistor M1b constitute two complementary common-gate structures, and the sources of the two are connected. The advantage of using a common gate structure is that it can meet the broadband input impedance matching, as follows:

$\begin{array}{c}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; a</span>}}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; a</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; a</span>}}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; |</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; b</span>}}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; b</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; b</span>}}}\\ <span\; class="notranslate">\; \&ap;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; a</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; b</span>}}}\end{array}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

In formula (1), R ₁ and R ₂ are resistance values, r _o1a and r _o1b are output impedances of MOS transistors M1a and M1b, and g _m1a and g _m1b are transconductances of MOS transistors M1a and M1b.

Under the condition of impedance matching, there are:

$\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; a</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; b</span>}}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

In formula (2), g _m1a and g _m1b are the transconductances of MOS transistors M1a and M1b.

At the same time, the combination of PMOS and NMOS of this kind of inverter also has the function of bias current multiplexing (Current-reuse), thus saving power.

The specific distortion cancellation principle is as follows:

The relationship between the AC leakage current and the gate-source voltage of a MOS transistor can be expressed as:

${\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; gs</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; gs</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; gs</span>}}^{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Among them, g1 is a first-order linear term, and g2 and g3 are second-order and third-order nonlinear terms, respectively. Figure 2 shows a single NMOS common-gate circuit using noise cancellation technology. Its linearity is limited by two factors: (1) the intrinsic third-order intermodulation term IMD3 of the two-stage circuits; (2) the first-stage common-gate The second-order intermodulation term IMD2 in the output. IMD2 from the first stage will contribute IMD3 at the output after passing through the second stage amplifying circuit, thus deteriorating the linearity of the circuit. In the present invention, we add an additional PMOS common gate circuit on the basis of the single NMOS common gate level, as shown in Figure 3, the second-order nonlinear current gm2*Vin ² and gp2* from the NMOS transistor Mn and the PMOS transistor Mp Vin ² flows through R1 and R2, and generates two second-order nonlinear voltages Vx and Vy with opposite phases at point X and point Y respectively. Finally, the offset is realized at the output end of the first stage through two coupling capacitors C1 and C2. At the same time, two in-phase first-order linear terms are enhanced at the output.

The noise cancellation stage of the second stage is composed of a resistor R3 and three NMOS transistors M2, M3 and M4, and the actual noise cancellation function is realized by M2 and M3 respectively. As shown in Figure 2, the channel thermal noise current of the common-gate transistor M1 of the first-stage circuit flows through R1 and RS respectively, and two noise voltages V _X , noise and V _Y with opposite phases are generated at points X and Y , noise. After being coupled by capacitors C1 and C2, it is sent to the gates of M2 and M3. Noise cancellation can be realized when the following conditions are met:

$\begin{array}{c}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; \&CenterDot;</span><span\; class="notranslate">\; (</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; noise</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; noise</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}\\ <span\; class="notranslate">\; \&DoubleRightArrow;</span>\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}}}\end{array}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

In formula (4), R ₁ and R _S are resistance values, g _m2 and g _m3 are transconductances of MOS transistors M2 and M3, and I _noise,m1 is channel thermal noise current of MOS transistor M1.

The NMOS transistor M4 forms a cascode structure with M2 and M3, and the combination has a high output impedance. The output impedance Zout of the whole circuit is composed of the load resistor R3 and the output impedance of the cascode in parallel, which is about the resistance value of the resistor R3. The resistor R3 plays the role of output impedance matching, and the NMOS transistor M4 also plays the role of isolation from the output to the input. effect.

As shown in Figures 1 to 5, the connection relationship between the components in the amplifier circuit of the present invention is: the signal entering circuit is divided into two paths:

One route is connected to the sources of the NMOS transistor M1a and the PMOS transistor M1b, and the sources of the NMOS transistor M1a and the PMOS transistor M1b are connected; the gate of the NMOS transistor M1a is connected to the DC voltage VB1, and the gate of the PMOS transistor M1b is connected to the DC voltage VB2; the drain of the NMOS transistor M1a is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the power supply VDD, the drain of the PMOS transistor M1b is connected to the resistor R2, and the other end of the resistor R2 is connected to the ground terminal GND; the NMOS transistor M1a The drain is connected to the capacitor C1, the drain of the PMOS transistor M1b is connected to the capacitor C2, the capacitor C1 and the other end of the capacitor C2 are connected together and connected to the gate of the NMOS transistor M2 in the second stage.

As shown in Figure 1 and Figure 4, another route is connected to the capacitor C3 after the sources of the NMOS transistor M1a and PMOS transistor M1b are connected, and the other end of the capacitor C3 is connected to the gate of the NMOS transistor M3, and the NMOS transistor M2 and the NMOS transistor The source of M3 is connected to the ground, the drains of the NMOS transistor M2 and the NMOS transistor M3 are connected to the source of the NMOS transistor M4, the gate of the NMOS transistor M4 is connected to the DC voltage VB3, and the drain of the NMOS transistor M4 is connected to the resistor R3 , the other end of the resistor R3 is connected to the power supply VDD; the gate bias voltages of the NMOS transistor M2 and the NMOS transistor M3 are realized by two bias circuits.

The composition of the two bias circuits is shown in Figure 5: the gate of the NMOS transistor M5 is connected to the drain and connected to the resistors R4 and R6, the other end of the resistor R4 is connected to the power supply VDD, and the other end of the resistor R6 is connected to the NMOS The gate of the tube M2; the gate of the NMOS tube M6 is connected to the drain and connected to the resistors R5 and R7, the other end of the resistor R5 is connected to the power supply VDD, and the other end of the resistor R7 is connected to the gate of the NMOS tube M3.

Figure 4 shows the complete circuit structure, where Vs is the RF signal source, and the resistance RS is the signal source impedance, which is 50Ω, where RL is the load impedance (also 50Ω, the impedance of the analog network analyzer Term2). The two stages are coupled through capacitors C1, C2 and C3. The principle of channel thermal noise current cancellation of the additionally added PMOS common gate stage is the same as the principle of NMOS noise cancellation in FIG. 2 . Noise cancellation NMOS transistor biases M2 and M3 through an active current mirror, as shown in Figure 5, where resistors R6 and R7 are large resistors (MΩ level) used to isolate the noise generated by the bias current mirror. The bias voltages VB1, VB2 and VB3 can be provided on-chip or off-chip respectively. In the present invention, for the sake of simplicity and to avoid voltage offset caused by process deviation, the above-mentioned three voltages VB1, VB2 and VB3 are provided by the same simple resistor divider circuit supply. Finally, the amplifier gain can be obtained by simple circuit analysis. Note that the input signal is connected to the sources of NMOS transistor M1a and PMOS transistor M1b and then enters the circuit in two ways, one of which directly enters the complementary common gate structure and is coupled to the gate of M2 through X and Y respectively. The signal phase is the same as that of the input signal The same phase; the other is directly coupled to the gate of M3 through the capacitor C3, and then amplified by the second stage to the output, so as to achieve noise cancellation and enhance the signal at the same time.

A _v ＝[(g _m1b ·R ₁ +g _m1a ·R ₂ )·g _m2 +g _m3 ]·R ₃ (5)

In formula (5), R ₁ , R ₂ , and R ₃ are resistance values, g _m1a , g _m1b are transconductances of MOS transistors M1a and M1b, and g _m2 and g _m3 are transconductances of MOS transistors M2 and M3.

As shown in Fig. 4, the present invention adopts distortion and noise cancellation technology to realize CMOS broadband low noise amplifier, including distortion cancellation input stage and noise cancellation output stage. The distortion canceling input stage is composed of a resistor R1, an NMOS transistor M1a, a PMOS transistor M1b and a resistor R2, wherein the PMOS transistor M1b and the NMOS transistor M1a form a current multiplexing structure, and the gates of the NMOS transistor M1a and the PMOS transistor M1b are biased The set voltage is provided by a simple resistor divider circuit.

The specific distortion canceling function is completed by the above four components, that is, canceling the second-order intermodulation item IMD2 generated by the second-order nonlinear item generated by the common-gate device at the output end of the first stage. The noise cancellation output stage is composed of a resistor R3 and three NMOS transistors M2, M3 and M4. The specific noise cancellation function is completed by the NMOS transistors M2 and M3, that is, to cancel the channel thermal noise current of the first-stage common-gate transistor, because This noise source contributes the largest amount to the overall noise figure. NMOS transistor M4 is used to realize output-to-input isolation. The above-mentioned two-stage structure realizes signal coupling through capacitors C1, C2 and C3, and the bias voltage of the second-stage input device NMOS transistors M2 and M3 is realized through a set of active current mirrors. The specific circuit is shown in FIG. 5 . The gate bias voltage of the NMOS transistor M4 is realized by a resistor divider circuit. In order to save additional power consumption and maintain process consistency, the MOS transistors M1a, M1b and M4 share a resistor divider circuit. In addition, in order to facilitate testing with a network analyzer with an internal resistance of 50Ω, the load resistor R3 is approximately 50Ω.

Example:

This embodiment adopts the circuit structure shown in Figure 4, and the circuit design is based on the CHRT 0.18 μm RFCMOS 1P6M process, and is simulated using the Cadence SpectreRF tool. The power supply voltage VDD is 1.8V, and the working frequency range is 0.1-1.6GHz.

For a standard RF system of 50Ω, the input impedance of the CMOS broadband low-noise amplifier LNA should satisfy (gm1a+gm1b)=20ms. Compared with a single NMOS common-gate stage, this structure can save nearly half of the bias current.

M2 and M3 are biased at 0.55V and 0.6V respectively by using the bias circuit in Fig. 5 . Resistors R1 and R2 take values of 500Ω and 480Ω respectively. For the convenience of S22 test, the resistance R3 is 50Ω.

Figure 6 shows the simulation results of S parameters, where S11, S12 and S22 represent the input reflection coefficient, reverse transmission coefficient and output reflection coefficient respectively. From the simulation results, it has good input matching in the corresponding frequency band, and in It reaches -27dB at 0.2GHz; Figure 7 shows the power gain and noise figure. From the simulation results, the average value of the noise figure is about 2.4dB in the above working frequency band, and the maximum gain of the circuit is 11.73dB, with a 3dB bandwidth From 0.1GHz to 1.8GHz; Fig. 8 shows the change trend of the linearity measurement parameter third-order intermodulation point IIP3 and 1dB compression point IP1dB at the above operating frequency, it can be seen that the change range of IIP3 is from -2 to 9.14dBm, IP1dB varies around -5dBm. The power consumption of the overall circuit is 19.8mW. These results show that the present invention has great advantages in obtaining high linearity and low noise at the same time, and also has good performance in input matching and power gain.

Although the present invention has been described above in conjunction with the drawings, the present invention is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative, rather than restrictive. Under the inspiration, without departing from the gist of the present invention, many modifications can be made by utilizing the technology provided by the present invention, and these all belong to the protection of the present invention.

Claims (1)

1., based on a high linearity CMOS wideband low noise amplifier for distortion and noise cancellation, it is characterized in that, this amplifier is divided into two-stage, comprises the distortion cancellation input stage of the first order and the noise cancellation output stage of the second level, wherein:

Described distortion cancellation input stage is made up of resistance R1, NMOS tube M1a, PMOS M1b, resistance R2 and coupling capacitance C1 and coupling capacitance C2, and wherein NMOS tube M1a and PMOS M1b constitutes complementary common gate structure;

Described noise cancellation output stage is made up of resistance R3, electric capacity C3 and nmos pass transistor M2, nmos pass transistor M3 and nmos pass transistor M4, described nmos pass transistor M2 and nmos pass transistor M3 is used for realizing noise cancellation, the input that exports to that described nmos pass transistor M4 is used for this amplifier is isolated, and resistance R3 is for realizing the output impedance coupling of this amplifier;

Annexation between above-mentioned each components and parts is:

Signal is divided into two-way after entering this amplifier:

The source electrode access of one route NMOS tube M1a and PMOS M1b, above-mentioned NMOS tube M1a is connected with the source electrode of PMOS M1b; The grid of NMOS tube M1a is connected to direct voltage VB1, the grid of PMOS M1b is connected to direct voltage VB2; The drain electrode of NMOS tube M1a is connected to one end of resistance R1, and the other end of resistance R1 is connected to power vd D, the drain electrode connecting resistance R2 of PMOS M1b, and the other end of resistance R2 holds GND with being connected to; The drain electrode of NMOS tube M1a is connected to electric capacity C1, and the drain electrode of PMOS M1b is connected to electric capacity C2, and electric capacity C1 is connected with the other end of electric capacity C2 and is together connected to the grid of NMOS tube M2 in the second level;

Electric capacity C3 is connected to after the source electrode access of another route NMOS tube M1a and PMOS M1b, the other end of electric capacity C3 is connected to the grid of NMOS tube M3, the source electrode of NMOS tube M2 and NMOS tube M3 is held with being connected to, the drain terminal of NMOS tube M2 and NMOS tube M3 is connected to the source electrode of NMOS tube M4, the grid of NMOS tube M4 is connected to direct voltage VB3, the drain terminal of NMOS tube M4 is connected to resistance R3, and the other end of resistance R3 is connected to power vd D; The gate bias voltage of NMOS tube M2 and NMOS tube M3 is realized by two biasing circuits;

Consisting of of described two biasing circuits:

The grid of NMOS tube M5 is connected with drain electrode and is connected to resistance R4 and resistance R6, and the other end of resistance R4 is connected to power vd D, and the other end of resistance R6 is connected to the grid of NMOS tube M2; The grid of NMOS tube M6 is connected with drain electrode and is connected to resistance R5 and resistance R7, and the other end of resistance R5 is connected to power vd D, and the other end of resistance R7 is connected to the grid of NMOS tube M3.