CN104539244A - Distortion and noise cancellation based high-linearity CMOS broadband low noise amplifier - Google Patents
Distortion and noise cancellation based high-linearity CMOS broadband low noise amplifier Download PDFInfo
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Abstract
本发明公开了一种基于失真和噪声抵消的高线性度CMOS宽带低噪声放大器,其结构包括失真抵消输入级和噪声抵消输出级。失真抵消输入级作为本低噪声放大器的第一级,采用CMOS互补共栅组合来实现输入阻抗匹配、二阶交调IMD2抵消,同时互补结构具备电流复用的特点从而节省功耗。第二级为噪声抵消输出级,主要目的是抵消第一级中两个共栅器件的沟道热噪声电流,从而降低整个电路的噪声系数。本发明可以在宽带范围内同时实现高线性度和低噪声系数,同时兼顾其他设计参数,如输入阻抗匹配、功率增益、功耗等。
The invention discloses a high-linearity CMOS wideband low-noise amplifier based on distortion and noise cancellation, the structure of which includes a distortion cancellation input stage and a noise cancellation output stage. The distortion cancellation input stage is the first stage of the low noise amplifier. It adopts CMOS complementary common gate combination to realize input impedance matching and second-order intermodulation IMD2 cancellation. At the same time, the complementary structure has the characteristics of current multiplexing to save power consumption. The second stage is the noise cancellation output stage, the main purpose is to offset the channel thermal noise current of the two common gate devices in the first stage, thereby reducing the noise figure of the whole circuit. The present invention can simultaneously realize high linearity and low noise figure within a wide band range, while taking into account other design parameters, such as input impedance matching, power gain, power consumption, and the like.
Description
技术领域technical field
本发明为射频集成电路技术领域,具体涉及一种同时采用失真和噪声抵消技术的CMOS宽带低噪声放大器(LNA)。The invention belongs to the technical field of radio frequency integrated circuits, and in particular relates to a CMOS broadband low-noise amplifier (LNA) which simultaneously adopts distortion and noise canceling technologies.
背景技术Background technique
随着3G/4G等移动通信技术的不断涌现,以射频微波为代表的无线收发技术正得到空前的发展。不同于已经成熟的第二代移动通信设备,当前的移动通信终端正趋向于集成多种通信标准来满足网络无缝链接实现信息的实时互享,例如智能手机能应用GSM、WCDMA、WIFI以及RFTV等。传统的解决方案基于将多个窄带路径并联来实现多标准通信,这种方案往往占用大芯片面积且有稳定性问题,缺乏可重构性。基于宽带模块的射频收发机正在吸引越来越多的研究人员的注意,其使用单个宽带模块覆盖上述全部通信标准或部分标准。With the continuous emergence of mobile communication technologies such as 3G/4G, wireless transceiver technology represented by radio frequency microwave is developing unprecedentedly. Different from the mature second-generation mobile communication devices, the current mobile communication terminals are tending to integrate multiple communication standards to meet the seamless connection of the network to realize real-time sharing of information. For example, smart phones can use GSM, WCDMA, WIFI and RFTV wait. Traditional solutions are based on paralleling multiple narrowband paths to achieve multi-standard communication. This solution often occupies a large chip area and has stability problems and lacks reconfigurability. Wideband module-based RF transceivers are attracting more and more researchers' attention, which cover all or some of the above-mentioned communication standards with a single wideband module.
作为无线接收机的第一个射频有源模块,低噪声放大器在整个无线系统中起到非常关键作用。从天线接收到的微弱信号首先经过频带选通滤波器,然后通过低噪声放大器进行第一次放大,再送到后级射频模块以及基带电路进行处理。为了保证后级模块能正确处理信号,低噪声放大器本身必须引入尽可能低的噪声,同时满足输入阻抗匹配、合适的增益以及一定的线性度。设计一个宽带低噪声放大器的挑战在于要在一个很宽的频带范围内满足上述的设计要求。由于在宽频带范围内包含了多种强弱不同的射频信号,这些信号间极易发生互调和交调,从而破坏某一子频带内有用信号,影响信号传输质量。所以在宽带内同时满足低噪声和高线性度成为了宽带低噪声放大器设计成功的关键。As the first RF active module of a wireless receiver, a low noise amplifier plays a key role in the entire wireless system. The weak signal received from the antenna first passes through the band-pass filter, and then is first amplified by the low-noise amplifier, and then sent to the subsequent RF module and baseband circuit for processing. In order to ensure that the post-stage module can process signals correctly, the low-noise amplifier itself must introduce as low noise as possible, while satisfying input impedance matching, appropriate gain, and certain linearity. The challenge in designing a wideband LNA is to meet the above design requirements over a wide frequency band. Since there are a variety of radio frequency signals with different strengths in the wide frequency range, intermodulation and intermodulation between these signals are very easy to occur, thereby destroying useful signals in a certain sub-band and affecting the quality of signal transmission. Therefore, satisfying both low noise and high linearity within a wide band has become the key to the successful design of a wide band LNA.
基于CMOS工艺的集成电路具有高集成度和低功耗消耗,已经成为当今集成电路的主流设计所选。随着CMOS工艺不断朝着深亚微米方向发展,MOS器件正越来越符合射频集成电路的设计需求。当前技术下,0.18μm工艺MOS器件的截止频率能达到约30GHz,已经能满足10GHz以下射频电路设计的需要,相关报道如参考文献[1][2][3]。但是,尺寸的减小伴随着器件高阶效应的出现,例如非线性漏输出电导、速度饱和效应、迁移率衰减以及多栅耗尽等不断使CMOS电路设计更加复杂化。Integrated circuits based on CMOS technology have high integration and low power consumption, and have become the mainstream design choice for integrated circuits today. With the continuous development of CMOS technology towards deep submicron, MOS devices are increasingly meeting the design requirements of radio frequency integrated circuits. Under the current technology, the cut-off frequency of 0.18μm process MOS devices can reach about 30GHz, which can already meet the needs of RF circuit design below 10GHz. Related reports can be found in references [1][2][3]. However, the reduction in size is accompanied by the emergence of higher-order effects of devices, such as nonlinear drain-output conductance, velocity saturation effects, mobility decay, and multi-gate depletion, which continue to complicate CMOS circuit design.
作为射频集成电路常用元件,电感一直是限制电路性能的另一个重要因素。片上集成电感的Q值有限(一般小于10)不能很好的满足窄带匹配、选频需求,而且生产厂家一般不提供电感模型或者提供的模型精确度很低;自己设计一枚片上电感往往需要借助专业的设计软件,如Ansoft公司的HFSS软件等,这些软件往往需要消耗大量计算机资源和设计者具备一定的使用经验,以上这些因素在很大程度上限制了射频集成电路的发展。此外,集成电路的电源电压也不断随着工艺尺寸下降而下降,这使得电路设计愈发具有挑战性。As a common component of radio frequency integrated circuits, inductance has been another important factor limiting circuit performance. The Q value of the on-chip integrated inductor is limited (generally less than 10), which cannot well meet the needs of narrowband matching and frequency selection, and manufacturers generally do not provide inductor models or the accuracy of the models provided is very low; designing an on-chip inductor by yourself often requires the help of Professional design software, such as Ansoft's HFSS software, etc., these software often need to consume a lot of computer resources and designers have a certain experience in use, these factors limit the development of radio frequency integrated circuits to a large extent. In addition, the power supply voltage of integrated circuits continues to decrease as the process size decreases, which makes circuit design more and more challenging.
参考文献:references:
[1]Federico Bruccoleri,Eric A.M.Klumperink,,and Bram Nauta,“Wide-Band CMOSLow-Noise Amplifier Exploiting Thermal Noise Canceling,”IEEE J.Solid-State Circuits,vol.39,pp.275-282,Feb.2004。[1] Federico Bruccoleri, Eric A.M. Klumperink,, and Bram Nauta, "Wide-Band CMOS Low-Noise Amplifier Exploiting Thermal Noise Canceling," IEEE J.Solid-State Circuits, vol.39, pp.275-282, Feb.2004 .
[2]C.-F.Liao and S.I.Liu,“A broadband noise-canceling MOS LNA for 3.1–10.6-GHzUWB receiver,”IEEE J.Solid-State Circuits,vol.42,no.2,pp.329–339,Feb.2007。[2] C.-F.Liao and S.I.Liu, "A broadband noise-canceling MOS LNA for 3.1–10.6-GHz UWB receiver," IEEE J.Solid-State Circuits, vol.42, no.2, pp.329– 339, Feb. 2007.
[3]A.Bevilacqua and A.M.Niknejad,“An ultra-wideband CMOS LNA for 3.1to 10.6GHzwireless receiver,”in IEEE ISSCC Dig.Tech.Papers,pp.382–383,2004。[3] A.Bevilacqua and A.M.Niknejad, "An ultra-wideband CMOS LNA for 3.1to 10.6GHz wireless receiver," in IEEE ISSCC Dig.Tech.Papers,pp.382–383,2004.
发明内容Contents of the invention
针对现有技术,本发明提出的一种基于失真和噪声抵消的高线性度CMOS宽带低噪声放大器是一种宽带低噪声放大器。该放大器的电路中不使用电感,避免了由于Q值有限造成的不能很好的满足窄带匹配、选频需求的问题。将两种独立的技术:失真抵消和噪声抵消技术用于同一个电路中,从而实现了宽带下高线性度和低噪声,同时兼顾输入匹配、功率增益和功耗参数。本发明放大器采用CMOS 0.18μm工艺实现,设计具有可复制性。Aiming at the prior art, the invention proposes a high-linearity CMOS broadband low-noise amplifier based on distortion and noise cancellation, which is a broadband low-noise amplifier. The circuit of the amplifier does not use an inductance, which avoids the problem that the narrow-band matching and frequency selection requirements cannot be well met due to the limited Q value. Two independent techniques: Distortion Cancellation and Noise Cancellation are used in the same circuit to achieve high linearity and low noise in wideband while taking into account input matching, power gain and power consumption parameters. The amplifier of the present invention is realized by a CMOS 0.18μm process, and the design is reproducible.
为了解决上述技术问题,本发明一种基于失真和噪声抵消的高线性度CMOS宽带低噪声放大器予以实现的技术方案是:该放大器分为两级,包括第一级的失真抵消输入级和第二级的噪声抵消输出级,其中:所述失真抵消输入级由电阻R1、NMOS管M1a、PMOS管M1b、电阻R2和耦合电容C1和耦合电容C2组成,其中NMOS管M1a和PMOS管M1b构成了互补共栅结构;所述噪声抵消输出级由电阻R3、电容C3和NMOS晶体管M2、NMOS晶体管M3和NMOS晶体管M4组成,所述NMOS晶体管M2和NMOS晶体管M3用于实现噪声抵消,所述NMOS晶体管M4用于该放大器电路的输出至输入隔离,电阻R3用于实现该放大器的输出阻抗匹配。In order to solve the above-mentioned technical problems, a kind of high-linearity CMOS broadband low-noise amplifier based on distortion and noise cancellation of the present invention realizes the technical scheme as follows: the amplifier is divided into two stages, including the distortion cancellation input stage of the first stage and the second stage The noise canceling output stage of the stage, wherein: the distortion canceling input stage is composed of a resistor R1, an NMOS transistor M1a, a PMOS transistor M1b, a resistor R2, a coupling capacitor C1, and a coupling capacitor C2, wherein the NMOS transistor M1a and the PMOS transistor M1b form a complementary common gate structure; the noise cancellation output stage is composed of a resistor R3, a capacitor C3, an NMOS transistor M2, an NMOS transistor M3 and an NMOS transistor M4, the NMOS transistor M2 and the NMOS transistor M3 are used to implement noise cancellation, and the NMOS transistor M4 Used for output-to-input isolation of the amplifier circuit, resistor R3 is used to achieve output impedance matching of the amplifier.
上述各元器件之间的连接关系为:信号进入该放大器电路分为两路:The connection relationship between the above components is: the signal entering the amplifier circuit is divided into two paths:
一路由NMOS管M1a和PMOS管M1b的源极接入,上述NMOS管M1a和PMOS管M1b的源极相连;NMOS管M1a的栅极连至直流电压VB1、PMOS管M1b的栅极连至直流电压VB2;NMOS管M1a的漏极连接至电阻R1的一端,电阻R1的另一端连至电源VDD,PMOS管M1b的漏极接电阻R2,电阻R2的另一端连至地端GND;NMOS管M1a的漏极连至电容C1,PMOS管M1b的漏极连至电容C2,电容C1和电容C2的另一端相连并一同连至第二级中NMOS管M2的栅极。One route is connected to the sources of the NMOS transistor M1a and the PMOS transistor M1b, and the sources of the NMOS transistor M1a and the PMOS transistor M1b are connected; the gate of the NMOS transistor M1a is connected to the DC voltage VB1, and the gate of the PMOS transistor M1b is connected to the DC voltage VB2; the drain of the NMOS transistor M1a is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the power supply VDD, the drain of the PMOS transistor M1b is connected to the resistor R2, and the other end of the resistor R2 is connected to the ground terminal GND; the NMOS transistor M1a The drain is connected to the capacitor C1, the drain of the PMOS transistor M1b is connected to the capacitor C2, the capacitor C1 and the other end of the capacitor C2 are connected together and connected to the gate of the NMOS transistor M2 in the second stage.
另一路由NMOS管M1a和PMOS管M1b的源极接入后连接至电容C3,电容C3的另一端连至NMOS管M3的栅极,NMOS管M2和NMOS管M3的源极连至地端,NMOS管M2和NMOS管M3的漏端连至NMOS管M4的源极,NMOS管M4的栅极连至直流电压VB3,NMOS管M4的漏端连至电阻R3,电阻R3的另一端连至电源VDD;NMOS管M2和NMOS管M3的栅极偏置电压由两个偏置电路实现,两个偏置电路的组成为:NMOS管M5的栅极与漏极相连并连至电阻R4和电阻R6,电阻R4的另一端连至电源VDD,电阻R6的另一端连至NMOS管M2的栅极;NMOS管M6的栅极与漏极相连并连至电阻R5和电阻R7,电阻R5的另一端连至电源VDD,电阻R7的另一端连至NMOS管M3的栅极。Another route connects the sources of the NMOS transistor M1a and the PMOS transistor M1b to the capacitor C3, the other end of the capacitor C3 is connected to the gate of the NMOS transistor M3, and the sources of the NMOS transistor M2 and the NMOS transistor M3 are connected to the ground terminal. The drains of the NMOS transistor M2 and the NMOS transistor M3 are connected to the source of the NMOS transistor M4, the gate of the NMOS transistor M4 is connected to the DC voltage VB3, the drain of the NMOS transistor M4 is connected to the resistor R3, and the other end of the resistor R3 is connected to the power supply VDD; the gate bias voltage of NMOS transistor M2 and NMOS transistor M3 is realized by two bias circuits, and the composition of the two bias circuits is: the gate of NMOS transistor M5 is connected to the drain and connected to resistor R4 and resistor R6 , the other end of resistor R4 is connected to the power supply VDD, the other end of resistor R6 is connected to the gate of NMOS transistor M2; the gate of NMOS transistor M6 is connected to the drain and connected to resistor R5 and resistor R7, and the other end of resistor R5 is connected to to the power supply VDD, and the other end of the resistor R7 is connected to the gate of the NMOS transistor M3.
与现有技术相比,本发明放大器的有益效果是:Compared with prior art, the beneficial effect of amplifier of the present invention is:
(1)本发明将噪声抵消技术、失真抵消技术和电流复用技术相结合,可以同时获得高线性度和低噪声性能,电流复用技术用于节省功耗。(1) The present invention combines noise cancellation technology, distortion cancellation technology and current multiplexing technology to obtain high linearity and low noise performance at the same time, and the current multiplexing technology is used to save power consumption.
(2)本发明中使用共栅结构实现宽带输入匹配,可以同时实现多通信标准集成,方便通信终端无线多接口连接。(2) In the present invention, a common gate structure is used to realize broadband input matching, which can realize the integration of multiple communication standards at the same time, and facilitate wireless multi-interface connection of communication terminals.
(3)本发明采用深亚微米0.18μmCMOS工艺实现,1.8V低电源电压供电,其功耗消耗较低。(3) The present invention is realized by using a deep submicron 0.18 μm CMOS process, powered by a low power supply voltage of 1.8V, and its power consumption is relatively low.
(4)本发明中使用的器件主要包括MOS晶体管、电阻和电容,整体电路不含电感,从而节省芯片面积,降低了成本。(4) The devices used in the present invention mainly include MOS transistors, resistors and capacitors, and the overall circuit does not contain inductors, thereby saving chip area and reducing costs.
(5)本发明的实现采用主流CMOS工艺,可以与普遍采用CMOS工艺的数字基带电路集成在同一块芯片上,容易实现片上系统集成。(5) The realization of the present invention adopts the mainstream CMOS technology, and can be integrated on the same chip with the digital baseband circuit generally adopting the CMOS technology, and it is easy to realize system-on-chip integration.
附图说明Description of drawings
图1是本发明低噪声放大器的电路结构框图;Fig. 1 is the block diagram of the circuit structure of low noise amplifier of the present invention;
图2是本发明中噪声抵消技术原理图;Fig. 2 is a schematic diagram of noise cancellation technology in the present invention;
图3是本发明中失真抵消技术原理图;Fig. 3 is a schematic diagram of the distortion cancellation technology in the present invention;
图4是本发明低噪声放大器的完整电路实现图;Fig. 4 is the complete circuit realization diagram of the low noise amplifier of the present invention;
图5是本发明中M2和M3的偏置电路实现图;Fig. 5 is the bias circuit implementation figure of M2 and M3 among the present invention;
图6是本发明低噪声放大器的S参数的仿真结果图;Fig. 6 is the simulation result figure of the S parameter of low noise amplifier of the present invention;
图7是本发明低噪声放大器的功率增益和噪声系数仿真结果图;Fig. 7 is the power gain and noise figure simulation result figure of low noise amplifier of the present invention;
图8是本发明低噪声放大器的IP1dB和IIP3仿真结果图;Fig. 8 is the IP1dB and IIP3 simulation result figure of low noise amplifier of the present invention;
具体实施方式Detailed ways
下面结合具体实施方式对本发明作进一步详细地描述。The present invention will be further described in detail below in combination with specific embodiments.
如图1所示,本发明提出的一种基于失真和噪声抵消的高线性度CMOS宽带低噪声放大器,该放大器分为两级,依次为第一级的失真抵消输入级和第二级的噪声抵消输出级。As shown in Fig. 1, a kind of high-linearity CMOS broadband low-noise amplifier based on distortion and noise cancellation proposed by the present invention, this amplifier is divided into two stages, and the distortion of the first stage cancels the input stage and the noise of the second stage successively offset output stage.
第一级的失真抵消输入级由电阻R1、NMOS管M1a、PMOS管M1b、电阻R2和耦合电容C1和耦合电容C2组成。其中,NMOS管M1a和PMOS管M1b构成了两个互补共栅级结构,两者源极点相连。采用共栅结构的优点在于可以满足宽带输入阻抗匹配,如下:The distortion canceling input stage of the first stage is composed of resistor R1, NMOS transistor M1a, PMOS transistor M1b, resistor R2, coupling capacitor C1 and coupling capacitor C2. Wherein, the NMOS transistor M1a and the PMOS transistor M1b constitute two complementary common-gate structures, and the sources of the two are connected. The advantage of using a common gate structure is that it can meet the broadband input impedance matching, as follows:
公式(1)中,R1、R2为电阻值,ro1a、ro1b为MOS管M1a和M1b的输出阻抗,gm1a、gm1b为MOS管M1a和M1b的跨导。In formula (1), R 1 and R 2 are resistance values, r o1a and r o1b are output impedances of MOS transistors M1a and M1b, and g m1a and g m1b are transconductances of MOS transistors M1a and M1b.
在阻抗匹配的条件下,有:Under the condition of impedance matching, there are:
公式(2)中,gm1a、gm1b为MOS管M1a和M1b的跨导。In formula (2), g m1a and g m1b are the transconductances of MOS transistors M1a and M1b.
同时,这种类反向器PMOS和NMOS组合兼具偏置电流复用(Current-reuse)功能,从而节省了功率。At the same time, the combination of PMOS and NMOS of this kind of inverter also has the function of bias current multiplexing (Current-reuse), thus saving power.
具体失真抵消原理如下:The specific distortion cancellation principle is as follows:
一个MOS晶体管的交流漏电流与栅源电压的关系可以表示为:The relationship between the AC leakage current and the gate-source voltage of a MOS transistor can be expressed as:
其中g1为一阶线性项,g2和g3分别为二阶和三阶非线性项。图2为一个采用噪声抵消技术的单NMOS共栅级电路,其线性度受两个因素限制:(1)两级电路各自的本征三阶交调项IMD3;(2)第一级共栅输出中的二阶交调项IMD2。来自第一级的IMD2通过第二级放大电路后会在输出端贡献IMD3,从而恶化电路线性度。本发明中,我们在单NMOS共栅级的基础上额外加入一个PMOS共栅级电路,如图3所示,来自NMOS管Mn和PMOS管Mp的二阶非线性电流gm2*Vin2和gp2*Vin2流经R1和R2,在X点和Y点分别产生两个相位相反的二阶非线性电压Vx和Vy。最后通过两个耦合电容C1、C2在第一级的输出端实现抵消。同时,两个同相位的一阶线性项在输出端得到增强。Among them, g1 is a first-order linear term, and g2 and g3 are second-order and third-order nonlinear terms, respectively. Figure 2 shows a single NMOS common-gate circuit using noise cancellation technology. Its linearity is limited by two factors: (1) the intrinsic third-order intermodulation term IMD3 of the two-stage circuits; (2) the first-stage common-gate The second-order intermodulation term IMD2 in the output. IMD2 from the first stage will contribute IMD3 at the output after passing through the second stage amplifying circuit, thus deteriorating the linearity of the circuit. In the present invention, we add an additional PMOS common gate circuit on the basis of the single NMOS common gate level, as shown in Figure 3, the second-order nonlinear current gm2*Vin 2 and gp2* from the NMOS transistor Mn and the PMOS transistor Mp Vin 2 flows through R1 and R2, and generates two second-order nonlinear voltages Vx and Vy with opposite phases at point X and point Y respectively. Finally, the offset is realized at the output end of the first stage through two coupling capacitors C1 and C2. At the same time, two in-phase first-order linear terms are enhanced at the output.
所述第二级的噪声抵消级由电阻R3和三个NMOS晶体管M2、M3和M4组成,实际的噪声抵消功能分别由M2和M3实现。如图2所示,第一级电路的共栅晶体管M1的沟道热噪声电流分别流经R1和RS,在X点和Y点处产生两个相位相反的噪声电压VX,noise和VY,noise。经过电容C1和C2耦合后送至M2和M3的栅极,满足如下条件时即可实现噪声抵消:The noise cancellation stage of the second stage is composed of a resistor R3 and three NMOS transistors M2, M3 and M4, and the actual noise cancellation function is realized by M2 and M3 respectively. As shown in Figure 2, the channel thermal noise current of the common-gate transistor M1 of the first-stage circuit flows through R1 and RS respectively, and two noise voltages V X , noise and V Y with opposite phases are generated at points X and Y , noise. After being coupled by capacitors C1 and C2, it is sent to the gates of M2 and M3. Noise cancellation can be realized when the following conditions are met:
公式(4)中,R1、RS为电阻值,gm2、gm3为MOS管M2和M3的跨导,Inoise,m1为MOS管M1的沟道热噪声电流。In formula (4), R 1 and R S are resistance values, g m2 and g m3 are transconductances of MOS transistors M2 and M3, and I noise,m1 is channel thermal noise current of MOS transistor M1.
NMOS晶体管M4与M2和M3构成了共源共栅结构,该组合具有高输出阻抗。整个电路的输出阻抗Zout由负载电阻R3与共源共栅的输出阻抗并联构成,约为电阻R3的阻值,电阻R3起到输出阻抗匹配的作用,其中NMOS晶体管M4还起到了输出至输入的隔离作用。The NMOS transistor M4 forms a cascode structure with M2 and M3, and the combination has a high output impedance. The output impedance Zout of the whole circuit is composed of the load resistor R3 and the output impedance of the cascode in parallel, which is about the resistance value of the resistor R3. The resistor R3 plays the role of output impedance matching, and the NMOS transistor M4 also plays the role of isolation from the output to the input. effect.
如图1至图5所示,本发明放大器电路中各元器件之间的连接关系是:信号进入电路分为两路:As shown in Figures 1 to 5, the connection relationship between the components in the amplifier circuit of the present invention is: the signal entering circuit is divided into two paths:
一路由NMOS管M1a和PMOS管M1b的源极接入,上述NMOS管M1a和PMOS管M1b的源极相连;NMOS管M1a的栅极连至直流电压VB1、PMOS管M1b的栅极连至直流电压VB2;NMOS管M1a的漏极连接至电阻R1的一端,电阻R1的另一端连至电源VDD,PMOS管M1b的漏极接电阻R2,电阻R2的另一端连至地端GND;NMOS管M1a的漏极连至电容C1,PMOS管M1b的漏极连至电容C2,电容C1和电容C2的另一端相连并一同连至第二级中NMOS管M2的栅极。One route is connected to the sources of the NMOS transistor M1a and the PMOS transistor M1b, and the sources of the NMOS transistor M1a and the PMOS transistor M1b are connected; the gate of the NMOS transistor M1a is connected to the DC voltage VB1, and the gate of the PMOS transistor M1b is connected to the DC voltage VB2; the drain of the NMOS transistor M1a is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the power supply VDD, the drain of the PMOS transistor M1b is connected to the resistor R2, and the other end of the resistor R2 is connected to the ground terminal GND; the NMOS transistor M1a The drain is connected to the capacitor C1, the drain of the PMOS transistor M1b is connected to the capacitor C2, the capacitor C1 and the other end of the capacitor C2 are connected together and connected to the gate of the NMOS transistor M2 in the second stage.
如图1和图4所示,另一路由NMOS管M1a和PMOS管M1b的源极接入后连接至电容C3,电容C3的另一端连至NMOS管M3的栅极,NMOS管M2和NMOS管M3的源极连至地端,NMOS管M2和NMOS管M3的漏端连至NMOS管M4的源极,NMOS管M4的栅极连至直流电压VB3,NMOS管M4的漏端连至电阻R3,电阻R3的另一端连至电源VDD;NMOS管M2和NMOS管M3的栅极偏置电压由两个偏置电路实现。As shown in Figure 1 and Figure 4, another route is connected to the capacitor C3 after the sources of the NMOS transistor M1a and PMOS transistor M1b are connected, and the other end of the capacitor C3 is connected to the gate of the NMOS transistor M3, and the NMOS transistor M2 and the NMOS transistor The source of M3 is connected to the ground, the drains of the NMOS transistor M2 and the NMOS transistor M3 are connected to the source of the NMOS transistor M4, the gate of the NMOS transistor M4 is connected to the DC voltage VB3, and the drain of the NMOS transistor M4 is connected to the resistor R3 , the other end of the resistor R3 is connected to the power supply VDD; the gate bias voltages of the NMOS transistor M2 and the NMOS transistor M3 are realized by two bias circuits.
两个偏置电路的组成如图5所示:NMOS管M5的栅极与漏极相连并连至电阻R4和电阻R6,电阻R4的另一端连至电源VDD,电阻R6的另一端连至NMOS管M2的栅极;NMOS管M6的栅极与漏极相连并连至电阻R5和电阻R7,电阻R5的另一端连至电源VDD,电阻R7的另一端连至NMOS管M3的栅极。The composition of the two bias circuits is shown in Figure 5: the gate of the NMOS transistor M5 is connected to the drain and connected to the resistors R4 and R6, the other end of the resistor R4 is connected to the power supply VDD, and the other end of the resistor R6 is connected to the NMOS The gate of the tube M2; the gate of the NMOS tube M6 is connected to the drain and connected to the resistors R5 and R7, the other end of the resistor R5 is connected to the power supply VDD, and the other end of the resistor R7 is connected to the gate of the NMOS tube M3.
图4给出了完整的电路结构,其中Vs为射频信号源,电阻RS为信号源阻抗,取50Ω,其中,RL为负载阻抗(亦取50Ω,模拟网络分析仪Term2的阻抗)。两级之间通过电容C1、C2和C3耦合。额外加入的PMOS共栅级的沟道热噪声电流抵消原理与图2的NMOS噪声抵消原理相同。噪声抵消NMOS管对M2和M3的偏置通过有源电流镜实现,如图5所示,其中电阻R6、R7分别为大电阻(MΩ级)用于隔离偏置电流镜产生的噪声。偏置电压VB1、VB2和VB3可分别由片上或者片外提供,本发明中,为简单起见以及避免工艺偏差造成电压偏移,上述三个电压VB1、VB2和VB3由同一个简单电阻分压电路提供。最后,通过简单的电路分析可以得到放大器增益。注意到输入信号连至NMOS管M1a和PMOS管M1b的源极后分两路进入电路,其中一路直接进入互补共栅结构分别通过X、Y后耦合至M2的栅极,其信号相位与输入信号同相;另一路通过电容C3直接耦合至M3的栅极,经第二级放大后至输出,这样在实现噪声抵消的同时又增强了信号,Figure 4 shows the complete circuit structure, where Vs is the RF signal source, and the resistance RS is the signal source impedance, which is 50Ω, where RL is the load impedance (also 50Ω, the impedance of the analog network analyzer Term2). The two stages are coupled through capacitors C1, C2 and C3. The principle of channel thermal noise current cancellation of the additionally added PMOS common gate stage is the same as the principle of NMOS noise cancellation in FIG. 2 . Noise cancellation NMOS transistor biases M2 and M3 through an active current mirror, as shown in Figure 5, where resistors R6 and R7 are large resistors (MΩ level) used to isolate the noise generated by the bias current mirror. The bias voltages VB1, VB2 and VB3 can be provided on-chip or off-chip respectively. In the present invention, for the sake of simplicity and to avoid voltage offset caused by process deviation, the above-mentioned three voltages VB1, VB2 and VB3 are provided by the same simple resistor divider circuit supply. Finally, the amplifier gain can be obtained by simple circuit analysis. Note that the input signal is connected to the sources of NMOS transistor M1a and PMOS transistor M1b and then enters the circuit in two ways, one of which directly enters the complementary common gate structure and is coupled to the gate of M2 through X and Y respectively. The signal phase is the same as that of the input signal The same phase; the other is directly coupled to the gate of M3 through the capacitor C3, and then amplified by the second stage to the output, so as to achieve noise cancellation and enhance the signal at the same time.
Av=[(gm1b·R1+gm1a·R2)·gm2+gm3]·R3 (5)A v =[(g m1b ·R 1 +g m1a ·R 2 )·g m2 +g m3 ]·R 3 (5)
公式(5)中,R1、R2、R3为电阻值,gm1a、gm1b为MOS管M1a和M1b的跨导,gm2、gm3为MOS管M2和M3的跨导。In formula (5), R 1 , R 2 , and R 3 are resistance values, g m1a , g m1b are transconductances of MOS transistors M1a and M1b, and g m2 and g m3 are transconductances of MOS transistors M2 and M3.
如图4所示,本发明采用失真和噪声抵消技术来实现CMOS宽带低噪声放大器,包括失真抵消输入级和噪声抵消输出级。所述失真抵消输入级由电阻R1、NMOS管M1a、PMOS管M1b和电阻R2组成,其中PMOS管M1b和NMOS管M1a构成了一个电流复用结构,上述NMOS管M1a和PMOS管M1b的栅极偏置电压通过简单的电阻分压电路提供。As shown in Fig. 4, the present invention adopts distortion and noise cancellation technology to realize CMOS broadband low noise amplifier, including distortion cancellation input stage and noise cancellation output stage. The distortion canceling input stage is composed of a resistor R1, an NMOS transistor M1a, a PMOS transistor M1b and a resistor R2, wherein the PMOS transistor M1b and the NMOS transistor M1a form a current multiplexing structure, and the gates of the NMOS transistor M1a and the PMOS transistor M1b are biased The set voltage is provided by a simple resistor divider circuit.
具体的失真抵消功能由上述四个元件完成,即抵消共栅器件产生的二阶非线性项在第一级输出端产生的二阶交调项IMD2。所述噪声抵消输出级由电阻R3和三个NMOS晶体管M2、M3和M4组成,具体的噪声抵消功能由NMOS晶体管M2和M3完成,即抵消第一级共栅晶体管的沟道热噪声电流,因为该噪声源在整体噪声系数中所占比重最大。NMOS晶体管M4用于实现输出至输入的隔离。上述两级结构之间通过电容C1、C2和C3实现信号耦合,第二级输入器件NMOS晶体管M2和M3的偏置电压通过一组有源电流镜实现,具体电路见图5。NMOS管M4的栅极偏置电压由电阻分压电路实现,为了节省额外功耗和保持工艺一致性,MOS管M1a、M1b和M4共用一个电阻分压电路。此外,为了方便以50Ω内阻的网络分析仪测试,负载电阻R3约取50Ω。The specific distortion canceling function is completed by the above four components, that is, canceling the second-order intermodulation item IMD2 generated by the second-order nonlinear item generated by the common-gate device at the output end of the first stage. The noise cancellation output stage is composed of a resistor R3 and three NMOS transistors M2, M3 and M4. The specific noise cancellation function is completed by the NMOS transistors M2 and M3, that is, to cancel the channel thermal noise current of the first-stage common-gate transistor, because This noise source contributes the largest amount to the overall noise figure. NMOS transistor M4 is used to realize output-to-input isolation. The above-mentioned two-stage structure realizes signal coupling through capacitors C1, C2 and C3, and the bias voltage of the second-stage input device NMOS transistors M2 and M3 is realized through a set of active current mirrors. The specific circuit is shown in FIG. 5 . The gate bias voltage of the NMOS transistor M4 is realized by a resistor divider circuit. In order to save additional power consumption and maintain process consistency, the MOS transistors M1a, M1b and M4 share a resistor divider circuit. In addition, in order to facilitate testing with a network analyzer with an internal resistance of 50Ω, the load resistor R3 is approximately 50Ω.
实施例:Example:
本实施例采用图4所示电路结构,电路设计基于CHRT 0.18μm RFCMOS 1P6M工艺,使用Cadence SpectreRF工具仿真。电源电压VDD为1.8V,工作频段在0.1~1.6GHz。This embodiment adopts the circuit structure shown in Figure 4, and the circuit design is based on the CHRT 0.18 μm RFCMOS 1P6M process, and is simulated using the Cadence SpectreRF tool. The power supply voltage VDD is 1.8V, and the working frequency range is 0.1-1.6GHz.
对于50Ω的标准射频系统,CMOS宽带低噪声放大器LNA的输入阻抗应满足(gm1a+gm1b)=20ms,相比较于单NMOS共栅级,本结构可以节省近一半的偏置电流。For a standard RF system of 50Ω, the input impedance of the CMOS broadband low-noise amplifier LNA should satisfy (gm1a+gm1b)=20ms. Compared with a single NMOS common-gate stage, this structure can save nearly half of the bias current.
采用图5的偏置电路将M2和M3分别偏置在0.55V和0.6V。电阻R1和R2分别取值500Ω,480Ω。为了S22测试方便,电阻R3取50Ω。M2 and M3 are biased at 0.55V and 0.6V respectively by using the bias circuit in Fig. 5 . Resistors R1 and R2 take values of 500Ω and 480Ω respectively. For the convenience of S22 test, the resistance R3 is 50Ω.
图6给出了S参数的仿真结果图,其中S11,S12和S22分别表示输入反射系数、反向传输系数和输出反射系数,从仿真结果来看,在对应频带内具有良好的输入匹配,在0.2GHz处达到-27dB;图7给出了功率增益和噪声系数,从仿真结果来看,上述工作频段下,噪声系数的平均值约为2.4dB左右,电路的最大增益为11.73dB,3dB带宽从0.1GHz~1.8GHz;图8给出了线性度衡量参数三阶交调点IIP3和1dB压缩点IP1dB在上述工作频率下的变化趋势,可以看到IIP3变化范围从-2~9.14dBm,IP1dB在-5dBm左右附近变化。整体电路的功耗为19.8mW。这些结果说明本发明在同时获得高线性度、低噪声方面有很大优势,并且在输入匹配、功率增益方面也具有不错的表现。Figure 6 shows the simulation results of S parameters, where S11, S12 and S22 represent the input reflection coefficient, reverse transmission coefficient and output reflection coefficient respectively. From the simulation results, it has good input matching in the corresponding frequency band, and in It reaches -27dB at 0.2GHz; Figure 7 shows the power gain and noise figure. From the simulation results, the average value of the noise figure is about 2.4dB in the above working frequency band, and the maximum gain of the circuit is 11.73dB, with a 3dB bandwidth From 0.1GHz to 1.8GHz; Fig. 8 shows the change trend of the linearity measurement parameter third-order intermodulation point IIP3 and 1dB compression point IP1dB at the above operating frequency, it can be seen that the change range of IIP3 is from -2 to 9.14dBm, IP1dB varies around -5dBm. The power consumption of the overall circuit is 19.8mW. These results show that the present invention has great advantages in obtaining high linearity and low noise at the same time, and also has good performance in input matching and power gain.
尽管上面结合图对本发明进行了描述,但是本发明并不局限于上述的具体实施方式,上述的具体实施方式仅仅是示意性的,而不是限制性的,本领域的普通技术人员在本发明的启示下,在不脱离本发明宗旨的情况下,利用本发明提供的技术还可以作出很多变形,这些均属于本发明的保护之内。Although the present invention has been described above in conjunction with the drawings, the present invention is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative, rather than restrictive. Under the inspiration, without departing from the gist of the present invention, many modifications can be made by utilizing the technology provided by the present invention, and these all belong to the protection of the present invention.
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Application publication date: 20150422 |