KR101408946B1 - Method for plaaning and apparatus circuits for transconductor - Google Patents

Abstract

The present invention relates to a transconductor circuit device and a method of designing the same. The transconductor circuit device includes a first MOS (Metal Oxide Semiconductor) transistor having a gate receiving AC and DC voltages, a drain connected to a current output terminal, A second MOS transistor having a gate receiving the same AC and DC voltage as the first MOS transistor, a drain connected to the source of the third MOS transistor, and a source connected to the ground, And a third MOS transistor connected to a current output terminal and having a source connected to a drain of the second transistor, wherein the second and third IMD current components can be canceled without using a coupling capacitance, It can be used in up mixer to improve linearity.

A transconductor, an up mixer, a metal oxide semiconductor (MOS)

Description

[0001] METHOD FOR PLAANING AND APPARATUS CIRCUITS FOR TRANSCONDUCTOR [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transconductor circuit and, more particularly, to a high-linearity transconductor circuit for improving the linearity of a wireless communication device used in a CMOS (Complementary Metal Oxide Semiconductor) Circuit and design method.

1, a CMOS (complementary metal oxide semi-conductor) RFIC (Radio Frequency IC) 101 processes a signal from a baseband modem 103 by high-frequency processing, And converts the high frequency signal received through the antenna 105 into a baseband signal without distortion and transmits the baseband signal to the baseband modem 103.

Conventionally, techniques for improving the linearity of the high-frequency integrated circuit (RFIC) have been studied to prevent the signal distortion. Particularly, the transconductance of the transconductors used in the low noise amplifiers (LNA) 111 and 113 or the up mixer 115 and the down mixer 117 of the high-frequency integrated circuit transconductance; g _m) and that is designed to operate with only the linearly study of techniques to prevent the signal distortion.

The transconductor is a circuit for processing an electrical signal, which converts an input voltage into a current and outputs it. In general, the transconductance (g _m ) of an ideal transconductor should always be constant regardless of the magnitude of the input voltage. However, in the actual transconductor configured as shown in FIG. 2, the transconductance (g _m ) value is changed by a predetermined input voltage (Vin) 201 input to the MOS transistor (M) 203, The current Iout 205 is distorted.

Equation 1 represents the drain-source current in a typical transconductor.

Here, i _DS represents a drain-source current, Idc represents a DC current, g _m represents a transconductance, and v _gs represents a gate-source voltage.

As shown in Equation (1), the drain-source current is distorted due to the non-linearity due to the secondary and tertiary IMD components, do. Thus, conventionally, circuits are provided to remove the third IMD component, i.e., the g _m "component, to increase the linearity of the mixer. For example, -distortion technique and a multiple gated transistor circuit as shown in FIG. 4 are provided.

The transconductor circuit with a Previous distortion techniques as described above, illustrated in Figure 3 was added to the distortion with the distortion and the characteristics of the reverse generated in the transconductance (g _m) stage to an input voltage, the transconductance (g _m) stage Thereby compensating for the distortion occurring in the transconductance (g _m ) stage.

However, the transconductor circuit using the previous distortion circuit technique requires an additional power source for the previous distortion, and ultimately has a problem of reducing battery life in a mobile environment by increasing current consumption. In order to compensate for the non-linearity due to the previous distortion, the previous distortion should be performed so as to have a characteristic exactly opposite to that of the non-linear characteristic of the transconductance (g _m ). However, Since the nonlinearity is compensated only in the specific input voltage section and the nonlinearity is not compensated in the remaining period, the third input intercept point (IIP3) or the third output intercept point (OIP3) ) Value is not greatly improved.

On the other hand, in the multi gated transistor circuit, as shown in FIG. 4 (a), a MOS filed effect transistor (hereinafter referred to as " MOS FET ") is used to cancel the tertiary transconductance g _m " The gate bias of the MOSFET is operated in a weak inversion region as shown in Figure 4 (b). As a result, as shown in Figure 4 (b), the gate bias of the MOSFET having a niegative value third transconductance (g _m "), as shown in 4 (c) also the offset each other and third-order transconductance (g _m has a positive value (positive) in the sub-MOSFET"), the third section And the linearity is improved.

However, in the method using the multi-gate transistor, since the gate voltage must be shifted by biasing so that the auxiliary MOSFET has a positive value, the bias must be separately supplied to the main MOSFET and the auxiliary MOSFET. In addition, a coupling capacitor is used to separately supply the bias. In general, a low noise amplifier (LNA) or a down mixer of a receiving end receives a signal of a high frequency band, It is possible to use a coupling capacitor. However, when receiving a baseband signal as in an up mixer of a transmitting terminal, the size of the coupling capacitor increases, which makes it difficult to use in a mobile communication device .

Further, in the case to operate the auxiliary FET at about inversion region, in the prior art as shown in FIG. 1 may be increased without yi g _m 'value for determining a second IMD components are canceled out. Accordingly, in the case of a communication system using the direct conversion method in which the second IMD component is important, the above-described conventional technique can not be used. Further, in order to improve the improvement effect, the high-order termination is made into an LC resonance structure. In this case, the size of the entire circuit is increased due to the inductor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a transconductor circuit device and a method of designing the same.

It is another object of the present invention to provide a transconductor circuit device and a design method for improving the linearity of an upmixer.

It is still another object of the present invention to provide a linear transconductor circuit device and a design method for eliminating secondary and tertiary IMD current components.

It is another object of the present invention to provide a transconductor having improved linearity by connecting two MOS transistors in a cascode structure in parallel to an existing transconductor.

According to a first aspect of the present invention, there is provided a transconductor circuit device including a first MOS (Metal Oxide) device having a gate receiving AC and DC voltages, a drain connected to a current output terminal, A second MOS transistor having a gate receiving the same AC and DC voltages as the first MOS transistor and having a drain connected to the source of the third MOS transistor and a source connected to the ground, And a third MOS transistor receiving a voltage and having a drain connected to the current output terminal and a source connected to a drain of the second transistor.

According to a second aspect of the present invention, a mixer (Up Mixer) in a wireless communication device includes a switching circuit for switching an output current provided from two transconductors according to a local oscillation signal, And the two transconductors connected to the switching circuitry to provide an output current.

In the present invention, by providing a transconductor circuit device that connects two MOS transistors configured in a cascode structure to a conventional transconductor in parallel, it is possible to cancel the secondary and tertiary IMD current components without using a coupling capacitance And an upmixer for receiving a baseband signal, thereby improving the linearity. In addition, since the coupling capacitance is not used, it is possible to reduce the size of the upmixer when compared with the conventional one.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In the present invention, two MOS transistors, each having a cascode structure, are connected in parallel to a conventional transconductor so that a second and a third IMDs (not shown) are used without coupling capacitance, A transconductor circuit device for removing components and a method of designing the same will be described.

In general, secondary and tertiary IMD components by the magnitude of the first derivative, wherein (g _m ') and the second derivative term (g _m "), the transconductance (g _m) as shown in Equation (1) it can be seen determined. here, the transconductance means a change amount of the output current corresponding to the input voltage. in this way, the magnitude of the first derivative, wherein (g _m ') and the second derivative term (g _m ") is less The relationship between the input voltage and the output current must be linearized.

However, under the assumption that Vgs has a value larger than Vth, in the conventional transconductor, since the relationship between the input voltage and the output current becomes non-linear as shown in the following Equation 2, the first derivative term and the second derivative term become 0 And the value is not.

Here, Iout denotes an output current, Vin denotes an input voltage, Vth denotes a threshold voltage, and Vds denotes a drain-source voltage. Μ is the mobility, Cox is the gate oxide capacitance of the MOS transistor, W is the width of the transistor, and L is the length.

Therefore, hereinafter in the present invention, as the Vgs is having an input voltage and an output current linearly related to the assumption has the value greater than the Vth, the first derivative, wherein (g _m ') and the second derivative term (g _m "≪ / RTI > will have a zero value will now be described.

Figure 5 shows a transconductor circuit according to the invention.

Referring to FIG. 5, the transconductor according to the present invention includes first, second and third MOS transistors M1, M2, and M3 (501, 503, and 505).

The gate of the first MOS transistor (M1) 501 is connected to the Vin (511), the drain is connected to the current output terminal, and the source is connected to the ground. Here, the size of the first MOS transistor (M1) (501) is reduced such that the current flowing in the first MOS transistor (M1) (501) is smaller than the current flowing in the existing transconductor.

The gate of the second MOS transistor M2 and 503 is connected to the Vin 511 like the first MOS transistor M1 and the drain thereof is connected to the source of the second MOS transistor M3 505, And the source is connected to the ground.

The gate of the third MOS transistor M3 505 is connected to Vb 513, the drain thereof is connected to the current output terminal, and the source thereof is connected to the drain of the second MOS transistor M3.

The first MOS transistor (M1) 501 is connected in parallel with the second and third MOS transistors (M3, M3) 503, 505 through a current output terminal. That is, the drain of the first MOS transistor (M1) 501 and the drain of the third MOS transistor (M3) 505 are connected in parallel.

Also, the second MOS transistor (M2) 503 and the third MOS transistor (M3) 505 are connected in a cascode structure. That is, the drain of the second MOS transistor M2 is connected to the source of the third MOS transistor M3. In this case, the cascode structure generally connects the input voltage Vb 513 to VDD in order to operate the second and third MOS transistors in a saturation region. In contrast, in the present invention, the Vb 513 And is supplied with the same DC voltage as the Vin 511. This is because the second MOS transistor 503 must be operated in the deep triode region and the third MOS transistor 505 should be operated in the saturation region according to the present invention. The Vb 513 is connected to VDD The second MOS transistor 503 operates not only in the third MOS transistor 505 but also in the saturation region. That is, in the present invention, the Vb 513 is set to a value capable of operating the second MOS transistor 503 in the deep triode region.

In the present invention, Vd 515 is set to a value for operating the first MOS transistor 501 in the saturation region. The drain voltage of the second MOS transistor 503 is lowered so that the second and third MOS transistors 503 and 505 are turned on to turn on the second MOS transistor 503, Deep triode region, and exhibits a resistance characteristic controlled by a voltage that changes nonlinearly according to the Vin 511. In other words, the equivalent resistance of the second MOS transistor 503 changes nonlinearly according to the input voltage Vin (511), and as a result, the characteristics of the Vin (511) and I2 (521) .

That is, in the present invention, the current flowing in the second and third MOS transistors (M2, M3) 503, 505 is non-linearly adjusted to compensate for the nonlinearity of the current flowing in the first MOS transistor The relationship between the total input voltage and the output current can be made linear.

The characteristics of the input voltage and the output current will now be described with reference to the configuration of FIG.

6 shows characteristics of an output current according to an input voltage in a transconductor according to an embodiment of the present invention. Here, the horizontal axis represents the input voltage and the vertical axis represents the output current.

6, an output current I1 (519) generated by the first MOS transistor 501 and an output current I2 (521) generated by the second and third MOS transistors 503 and 505 Have a nonlinear characteristic and a total output current Iout 517 having a nonlinear characteristic of the I1 519 and a nonlinear characteristic of the I2 521 has a linear characteristic.

Figure 7 illustrates a design procedure for a transconductor in accordance with an embodiment of the present invention.

Referring to FIG. 7, in order to design a transconductor according to the present invention, the designer first determines the total DC current Iout 517 to be outputted in step 701, and determines the size of the first MOS transistor 501 , I.e., the ratio of the width to the length (W1 / L1). Here, the size (W1 / L1) of the first MOS transistor 501 is set to be smaller than the size (W / L) of the MOS transistor constituting the conventional transconductor, as shown in FIG. This is to make the current flowing through the first MOS transistor 501 smaller than the current flowing through the transconductor.

Then, in step 705, the designer determines the size (W2 / L2) of the second MOS transistor 503 for operating in the deep triode region and the size of the third MOS transistor 505 for operating in the saturation region.

Then, in step 707, the designer calculates the sum of the output current I1 (519) of the first MOS transistor 501 and the output current I2 (521) of the second and third MOS transistors 503 and 505 It is checked whether or not it is equal to the total output current Iout 517 set in step 701.

If the sum of I1 519 and I2 521 is not equal to Iout 517, the designer returns to step 705 to adjust the size of the second and third MOS transistors 503 and 505 . On the other hand, the I1 (519) and when the sum of I2 (521) the same as the Iout (517), the designer proceeds to 709 steps on an input voltage within a specific range transconductance deokteon switch (g _m) values are constant We will check.

If the transconductance (g _m ) value is not constant for the input voltage within the specific range, the designer returns to step 705 and executes the following steps. If the transconductance g _m ) is constant, the design of the transconductor according to the present invention is completed and the algorithm is terminated.

When the sizes of the first, second, and third MOS transistors 501, 503, and 505 are determined according to the above-described procedure, the sizes of the MOS transistors can be determined as shown in Table 1 below.

M1 (W1 / L1) M2 (W2 / L2) M3 (W3 / L3) W1 = 50um, L1 = 0.25um W2 = 150 [mu] m, L2 = 0.25 [mu] m W3 = 275 [mu] m, L3 = 0.25 [mu] m

That is, as shown in Table 1, the width W1 and the length L1 of the first MOS transistor 501 are determined to be 50um and 0.25um, respectively, and the width W2 of the second MOS transistor 503 The length L2 is determined to be 150um and the width W3 and length L3 of the third MOS transistor 505 are determined to be 275um and 0.25um, respectively.

The first, the second and the 3 MOS transistor when the crystal size of (501, 503, 505), a transconductance (g _m, g _m ', g _m ") linearized characteristic in the vicinity of the DC operating point is obtained a as described above Can be obtained.

As described above, the linear transconductor circuit proposed by the present invention can be used in a communication-use integrated circuit as shown in FIG. 8 for a transmitter-side up mixer (Tx Up Mixer). The upmixer of the transmitting stage includes two transconductors, and the current output terminals of the two transconductors are connected to the FETs 813, 815, 817, and 818 included in the switching circuit 811 of the upmixer, Lt; / RTI > Accordingly, the currents output from the two transconductors 801 and 803 are switched by the local oscillation signals 821 and 823 and transmitted to the impedances Z _L (825 and 827).

Up mixer configured as described above, illustrated in Figure 8 includes a differential (Differential) because it operates in a structure Obtaining a transconductance (g _m) of the differential current flowing to the respective transconductors (801, 803), shown in Figure 9 Similarly, the transconductance (g _m ) value is constant at the vicinity of the DC operating point (901). That is, the second first derivative, wherein (g _m ') of the transconductance of determining the non-linearity is therefore zero in the vicinity of 901, the value of the transconductance constant operating point, thereby reducing the second IMD components. In addition, since the third-order zero at the non-linearity of the second order derivative, wherein (g _m ") also operates said transconductance value certain point of the transconductance for determining a, decreases the third IMD component, that is, a conventional transconductor The second and third IMD components are greatly reduced and the linearity is improved.

FIG. 10 shows the power of the first and third IMD terms in an upmixer using a conventional transconductor and an upmixer using a transconductor according to the present invention. Here, the horizontal axis represents the input power (Pin), and the vertical axis represents the output power (Pout).

As shown in FIG. 10, the voltage gain of the upmixer using the transconductor according to the present invention is reduced by 2 dB as compared with the upmixer using the conventional transconductor. However, OIP3 is -4.92 dBm It is 4.45dBm, which is improved by 9.4dB.

As described above, since the transconductor according to the present invention has a small size by improving the linearity by using three MOS transistors without using a coupling capacitor, the transconductor according to the present invention can be used as a CMOS The RFIC may be applied to the upmixer 115 at the transmitting end.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. Therefore, the scope of the present invention should not be limited by the illustrated embodiments, but should be determined by the scope of the appended claims and equivalents thereof.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a wireless communication device to which a transconductor is applied; Fig.

Figure 2 shows a transconductor circuit according to the prior art,

3 shows a transconductor linearization circuit using prior distortion according to the prior art,

Figure 4 illustrates a transconductor linearization circuit using a multi-gate transistor technique in accordance with the prior art;

Figure 5 shows a transconductor circuit according to the invention,

6 is a graph showing the characteristics of an output current according to an input voltage in a transconductor according to an embodiment of the present invention;

Figure 7 illustrates a design procedure for a transconductor in accordance with an embodiment of the present invention;

8 is a diagram illustrating an upmixer to which a transconductor according to an embodiment of the present invention is applied,

9 is a diagram showing the characteristics of transconductance in a transconductor according to an embodiment of the present invention, and Fig.

10 is a diagram showing the power of the first and third IMD terms in an upmixer to which a conventional transconductor is applied and an upmixer to which a transconductor according to the present invention is applied;

Claims (9)

In a transconductor circuit device, A first MOS (Metal Oxide Semiconductor) transistor having a gate receiving an alternating current (AC) voltage and a direct current (DC) voltage and having a drain connected to a current output terminal and a source connected to a ground, A second MOS transistor having a gate receiving the same AC and DC voltage as the first MOS transistor, a drain connected to the source of the third MOS transistor, and a source connected to the ground, And a third MOS transistor receiving the DC voltage as a gate and having a drain connected to the current output terminal and a source connected to a drain of the second transistor. The method according to claim 1, Wherein the first MOS transistor is connected in parallel with the second and third MOS transistors through a current output terminal. The method according to claim 1, Wherein the second MOS transistor operates in a deep triode region and the first and third MOS transistors operate in a saturation region. The method according to claim 1, And the output current of the first MOS transistor and the output current of the second and third MOS transistors have non-linearity. 1. A mixer (Up Mixer) device in a wireless communication device, A switching circuit for switching an output current provided from the two transconductors according to a local oscillation signal, And the two transconductors coupled to the switching circuitry to provide an output current, Each of the transconductors comprises: A first MOS (Metal Oxide Semiconductor) transistor having a gate receiving an AC and a DC voltage, a drain connected to a current output terminal, and a source connected to a ground, A second MOS transistor having a gate receiving the same AC and DC voltage as the first MOS transistor, a drain connected to the source of the third MOS transistor, and a source connected to the ground, And a third MOS transistor having a gate receiving the DC voltage, a drain coupled to the current output, and a source coupled to a drain of the second transistor. delete 6. The method of claim 5, Wherein the first MOS transistor is connected in parallel with the second and third MOS transistors through a current output terminal. 6. The method of claim 5, Wherein the second MOS transistor operates in a deep triode region and the first and third MOS transistors operate in a saturation region. 6. The method of claim 5, And the output current of the first MOS transistor and the output current of the second and third MOS transistors have non-linearity.

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