WO2024099060A1 - Passive circuit in radio frequency receiving module bypass mode, and radio frequency receiving module - Google Patents

Passive circuit in radio frequency receiving module bypass mode, and radio frequency receiving module Download PDF

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Publication number
WO2024099060A1
WO2024099060A1 PCT/CN2023/125997 CN2023125997W WO2024099060A1 WO 2024099060 A1 WO2024099060 A1 WO 2024099060A1 CN 2023125997 W CN2023125997 W CN 2023125997W WO 2024099060 A1 WO2024099060 A1 WO 2024099060A1
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transistor
path
resistor
circuit
receiving module
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PCT/CN2023/125997
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French (fr)
Chinese (zh)
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贾钧浩
郭嘉帅
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深圳飞骧科技股份有限公司
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Publication of WO2024099060A1 publication Critical patent/WO2024099060A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/24—Frequency-independent attenuators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the utility model relates to the technical field of signal processing, and in particular to a passive circuit in a bypass mode of a radio frequency receiving module and a radio frequency receiving module.
  • the low noise amplifier circuit is a basic circuit used in signal receiving and transmitting devices, which mainly includes an amplification unit and an output matching circuit.
  • the existing low-noise amplifier circuit may receive high-power signals. At this time, the signal does not need to be amplified again, but needs to be attenuated to a certain extent so that the high-power signal is attenuated into the required power signal, so as to be output to the next stage circuit.
  • the existing low-noise amplifier circuit only has an amplification unit for amplifying the signal, and does not have a related circuit for attenuating the received high-power signal. That is, the existing low-noise amplifier circuit cannot attenuate the high-power signal.
  • the existing low-noise amplifier circuit cannot attenuate the high-power signal.
  • the utility model aims to provide a passive circuit in a bypass mode of a radio frequency receiving module to solve the problem of the contradiction between the low power requirement of the next stage circuit of the existing low noise amplifier and the excessive power signal received by the radio frequency receiving module.
  • the utility model provides a passive circuit in a bypass mode of a radio frequency receiving module, which comprises a signal input terminal, an amplifying unit, an output matching circuit and a signal output terminal connected in sequence; the passive circuit further comprises an attenuation circuit connected between the input terminal of the amplifying unit and the input terminal of the output matching circuit;
  • the attenuation circuit includes a first transistor, a first path, a second path, a third path and a second transistor;
  • the gate of the first transistor is connected to a first control electrode voltage, and the source of the first transistor is connected to the input terminal of the amplification unit as the input terminal of the attenuation circuit;
  • the first end of the first path, the first end of the second path and the first end of the third path are all connected to the drain of the first transistor;
  • the gate of the second transistor is connected to a second control electrode voltage, the source of the second transistor is respectively connected to the second end of the first path, the second end of the second path and the second end of the third path, and the drain of the second transistor is connected to the input end of the output matching circuit as the output end of the attenuation circuit;
  • the first path, the second path and the third path are respectively used to attenuate the signal input to the signal input end to different degrees; when the passive circuit is in the bypass mode of the RF receiving module, the signal received by the signal input end is attenuated to different degrees by the attenuation circuit and then output to the input end of the output matching circuit.
  • the first path includes a third transistor, a first resistor, a second resistor, a third resistor and a fourth transistor;
  • the gate of the third transistor is connected to a third control electrode voltage, and the source of the third transistor is connected to the drain of the first transistor as the first end of the first path;
  • the first end of the first resistor is connected to the drain of the third transistor
  • the first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is grounded;
  • the first end of the third resistor is connected to the second end of the first resistor
  • the gate of the fourth transistor is connected to the fourth control electrode voltage
  • the source of the fourth transistor is connected to the second end of the third resistor
  • the drain of the fourth transistor is used as the The second end of the first path is connected to the source of the second transistor.
  • the second path includes a fifth transistor, a fourth resistor, a fifth resistor and a sixth transistor;
  • the gate of the fifth transistor is connected to a fifth control electrode voltage, and the source of the fifth transistor is connected to the drain of the first transistor as the first end of the second path;
  • the first end of the fourth resistor is connected to the drain of the fifth transistor
  • the first end of the fifth resistor is connected to the second end of the fourth resistor
  • the gate of the sixth transistor is connected to a sixth control electrode voltage, the source of the sixth transistor is connected to the second end of the fifth resistor, and the drain of the sixth transistor is connected to the source of the second transistor as the second end of the second path.
  • the third path includes a seventh transistor, a sixth resistor and an eighth transistor;
  • the gate of the seventh transistor is connected to a seventh control electrode voltage, and the source of the seventh transistor is connected to the drain of the first transistor as the first end of the third path;
  • the first end of the sixth resistor is connected to the drain of the seventh transistor
  • the gate of the eighth transistor is connected to the eighth control electrode voltage, the source of the eighth transistor is connected to the second end of the sixth resistor, and the drain of the eighth transistor is connected to the source of the second transistor as the second end of the third path.
  • the attenuation circuit further includes a first capacitor, which is connected in series between the drain of the second transistor and the input end of the output matching circuit.
  • the amplifying unit includes a ninth transistor and a tenth transistor
  • the gate of the ninth transistor serves as the input terminal of the amplifying unit and is connected to the signal input terminal, and the source of the ninth transistor is grounded;
  • the gate of the tenth transistor is connected to the power supply voltage, the source of the tenth transistor is connected to the drain of the ninth transistor, and the drain of the tenth transistor is connected to the input terminal of the output matching circuit.
  • the amplifying unit further includes a feedback inductor, a first end of the feedback inductor is connected to the source of the ninth transistor, and a second end of the feedback inductor is grounded.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are all NMOS transistors.
  • the output matching circuit includes a power supply inductor and a second capacitor;
  • the first end of the power supply inductor is connected to a power supply voltage
  • the first end of the second capacitor is connected to the second end of the power supply inductor and serves as the input end of the output matching circuit, and the second end of the second capacitor is connected to the signal output end.
  • the utility model provides a radio frequency receiving module, wherein the radio frequency receiving module includes the passive circuit in the radio frequency receiving module bypass mode as described above.
  • the passive circuit in the bypass mode of the RF receiving module of the utility model realizes the function of attenuating and outputting a high-power signal by adding an attenuation circuit between the input end of the amplification unit and the input end of the output matching circuit for attenuating the signal received at the signal input end to different degrees, and outputting the attenuated signal to the input end of the output matching circuit, thereby attenuating the high-power signal into the required power signal to be output to the next-stage circuit, thereby solving the contradiction between the low-power requirement of the next-stage circuit of the existing low-noise amplifier and the excessively high-power signal received by the RF receiving module.
  • FIG1 is a circuit diagram of a passive circuit in a bypass mode of a radio frequency receiving module provided by an embodiment of the present utility model.
  • An embodiment of the utility model provides a passive circuit 100 in a bypass mode of a radio frequency receiving module, as shown in FIG. 1 , which includes a signal input terminal VIN, an amplifying unit 10, an output matching circuit 20 and a signal output terminal VOUT connected in sequence; the passive circuit 100 also includes an attenuation circuit 30 connected between the input terminal of the amplifying unit 10 and the input terminal of the output matching circuit 20.
  • the passive circuit 100 in the bypass mode of the RF receiving module may be referred to as the passive circuit 100 hereinafter.
  • the attenuation circuit 30 includes a first transistor S1 , a first path 31 , a second path 32 , a third path 33 and a second transistor S8 .
  • the gate of the first transistor S1 is connected to the first control electrode voltage VG1 , and the source of the first transistor S1 is connected to the input terminal of the amplification unit 10 as the input terminal of the attenuation circuit 30 .
  • a first end of the first path 31 , a first end of the second path 32 , and a first end of the third path 33 are all connected to the drain of the first transistor S1 .
  • the gate of the second transistor S8 is connected to the second control electrode voltage VG8, the source of the second transistor S8 is respectively connected to the second end of the first path 31, the second end of the second path 32 and the second end of the third path 33, and the drain of the second transistor S8 is connected to the input end of the output matching circuit 20 as the output end of the attenuation circuit 30.
  • the first path 31, the second path 32 and the third path 33 are respectively used to attenuate the signal input to the signal input terminal VIN to different degrees; when the passive circuit 100 is in the RF receiving module bypass mode, the signal received by the signal input terminal VIN is attenuated to different degrees by the attenuation circuit 30 and then output to the input terminal of the output matching circuit 20.
  • the first path 31 includes a third transistor S2 , a first resistor R4 , a second resistor R6 , a third resistor R5 and a fourth transistor S3 .
  • the gate of the third transistor S2 is connected to the third control electrode voltage VG2 , and the source of the third transistor S2 is connected to the drain of the first transistor S1 as the first end of the first path 31 .
  • a first end of the first resistor R4 is connected to the drain of the third transistor S2.
  • a first end of the second resistor R6 is connected to the second end of the first resistor R4 , and a second end of the second resistor R6 is grounded.
  • a first end of the third resistor R5 is connected to a second end of the first resistor R4.
  • the gate of the fourth transistor S3 is connected to the fourth control electrode voltage VG3 , the source of the fourth transistor S3 is connected to the second end of the third resistor R5 , and the drain of the fourth transistor S3 is connected to the source of the second transistor S8 as the second end of the first path 31 .
  • the second path 32 includes a fifth transistor S4 , a fourth resistor R2 , a fifth resistor R3 , and a sixth transistor S5 .
  • the gate of the fifth transistor S4 is connected to the fifth control electrode voltage VG4 , and the source of the fifth transistor S4 is connected to the drain of the first transistor S1 as the first end of the second path 32 .
  • a first end of the fourth resistor R2 is connected to the drain of the fifth transistor S4.
  • a first end of the fifth resistor R3 is connected to a second end of the fourth resistor R2.
  • the gate of the sixth transistor S5 is connected to the sixth control electrode voltage VG5, the source of the sixth transistor S5 is connected to the second end of the fifth resistor R3, and the drain of the sixth transistor S5 is connected to the source of the second transistor S8 as the second end of the second path 32.
  • the third path 33 includes a seventh transistor S6 , a sixth resistor R1 , and an eighth transistor S7 .
  • the gate of the seventh transistor S6 is connected to the seventh control electrode voltage VG6 , and the source of the seventh transistor S6 is connected to the drain of the first transistor S1 as the first end of the third path 33 .
  • a first end of the sixth resistor R1 is connected to a drain of the seventh transistor S6 .
  • the gate of the eighth transistor S7 is connected to the eighth control electrode voltage VG7, the source of the eighth transistor S7 is connected to the second end of the sixth resistor R1, and the drain of the eighth transistor S7 is connected to the source of the second transistor S8 as the second end of the third path 33.
  • the attenuation circuit 30 further includes a first capacitor C1 , which is connected in series between the drain of the second transistor S8 and the input terminal of the output matching circuit 20 .
  • the amplifying unit 10 includes a ninth transistor M1 and a tenth transistor M2 .
  • the gate of the ninth transistor M1 serves as the input terminal of the amplifying unit 10 and is connected to the signal input terminal VIN, and the source of the ninth transistor M1 is grounded.
  • a gate of the tenth transistor M2 is connected to the power supply voltage Vb, a source of the tenth transistor M2 is connected to a drain of the ninth transistor M1 , and a drain of the tenth transistor M2 is connected to an input terminal of the output matching circuit 20 .
  • the amplifying unit 10 further includes a feedback inductor Ls, a first end of the feedback inductor Ls is connected to the source of the ninth transistor M1 , and a second end of the feedback inductor Ls is grounded.
  • the first transistor S1, the second transistor S8, the third transistor S2, the fourth transistor S3, the fifth transistor S4, the sixth transistor S5, the seventh transistor S6, the eighth transistor S7, the ninth transistor M1 and the tenth transistor M2 are all NMOS transistors.
  • the first transistor S1 to the tenth transistor M2 can also be arbitrarily selected from other replaceable transistors.
  • the output matching circuit 20 includes a power supply inductor Ld and a second capacitor C1.
  • a first terminal of the power supply inductor Ld is connected to a power supply voltage VDD.
  • a first end of the second capacitor C1 is connected to the second end of the power supply inductor Ld and serves as an input end of the output matching circuit 20 , and a second end of the second capacitor C1 is connected to the signal output end VOUT.
  • the first path 31, the second path 32 and the third path 33 are respectively used to attenuate the signal input from the signal input terminal VIN to different degrees, and then output it through the output matching network (output matching circuit 20) composed of the power supply inductor Ld and the second capacitor C1. Due to the matching effect of the output matching network composed of the power supply inductor Ld and the second capacitor C1, the signal output in the bypass mode will be greatly improved, and can be better matched with the load, reducing the loss caused by reflection.
  • the power supply inductor Ld and the second capacitor C1 form an output matching network of the low noise amplifier.
  • the power supply inductor Ld also plays a role of power supply.
  • the ninth transistor M1 and the tenth transistor M2 do not have an amplification effect, and the signal no longer passes through the ninth transistor M1 and the tenth transistor M2.
  • the ninth transistor M1 and the tenth transistor M2 form a low-noise amplifier with a common source and common gate structure
  • the power supply inductor Ld is the drain inductance of the low-noise amplifier
  • the feedback inductor Ls is the inductance of the source feedback of the low-noise amplifier
  • the second capacitor C1 forms an output matching capacitor
  • the second capacitor C1 is a DC blocking capacitor
  • the first transistor S1 to the eighth transistor S7 are all MOS switches
  • the first resistor R4 to the sixth resistor R1 are all attenuation resistors in bypass mode
  • the first control electrode voltage VG1 to the eighth control electrode voltage VG7 are all control voltages of the MOS switches.
  • the first control electrode voltage VG1 to the eighth control electrode voltage VG7 respectively control the opening of the first transistor S1 to the eighth transistor S7, and the bypass path is opened.
  • the third control electrode voltage VG2 to the eighth control electrode voltage VG7 turn on the third transistor S2 to the eighth transistor S7. Note that the two transistors on each path are turned on at the same time. By controlling the opening or closing of the switches of different paths, different equivalent resistance values can be obtained to achieve adjustable signal gain.
  • connections are all electrical connections or electrical connections, that is, the two or more connected devices are all electrically connected or electrically connected.
  • the passive circuit 100 of the RF receiving module in bypass mode of the utility model realizes the function of attenuating and outputting a high-power signal by adding an attenuation circuit 30 between the input end of the amplification unit 10 and the input end of the output matching circuit 20 for attenuating the signal received at the signal input end VIN to different degrees, and outputting the attenuated signal to the input end of the output matching circuit 20, thereby attenuating the high-power signal into a required power signal to be output to the next-stage circuit, thereby solving the contradiction between the low-power requirement of the next-stage circuit of the existing low-noise amplifier and the excessively high-power signal received by the RF receiving module.
  • the present invention also provides another embodiment, a radio frequency receiving module, which includes the passive circuit 100 in the bypass mode of the radio frequency receiving module in the above embodiment.
  • the RF receiving module in this embodiment includes the passive circuit 100 in the bypass mode of the RF receiving module in the above embodiment, it can also achieve the technical effect achieved by the passive circuit 100 in the bypass mode of the RF receiving module in the above embodiment, and no further explanation is given here. State.

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Abstract

The present application discloses a passive circuit in a radio frequency receiving module passive mode. The passive circuit comprises: successively connected, a signal input end, an amplification unit, an output matching circuit, and a signal output end; the passive circuit further comprises an attenuation circuit connected between an input end of the amplification unit and an input end of the output matching circuit; the attenuation circuit comprises a first transistor, a first path, a second path, a third path, and a second transistor; when the passive circuit is in a radio frequency receiving module bypass mode, signals received by the signal input end are attenuated to different degrees by means of the attenuation circuit and are then outputted to the input end of the output matching circuit. In the present application, the passive circuit in the radio frequency receiving module bypass mode achieves the function of attenuating high-power signals, and is further able to cause high-power signals to be attenuated to a required power signal to be outputted to a next-stage circuit.

Description

射频接收模组旁路模式下的无源电路及射频接收模组Passive circuit and RF receiving module in RF receiving module bypass mode 【技术领域】[Technical field]
本实用新型涉及信号处理技术领域，尤其涉及一种射频接收模组旁路模式下的无源电路及射频接收模组。The utility model relates to the technical field of signal processing, and in particular to a passive circuit in a bypass mode of a radio frequency receiving module and a radio frequency receiving module.
【背景技术】【Background technique】
低噪声放大器电路是一种应用于信号接收与发射器件的基本电路，其主要包括放大单元和输出匹配电路等。The low noise amplifier circuit is a basic circuit used in signal receiving and transmitting devices, which mainly includes an amplification unit and an output matching circuit.
现有的低噪声放大器电路在接收信号时，会存在接收到大功率信号的可能，此时的信号是不需要再次进行放大的，而是需要对信号进行一定程度上的衰减，以使大功率信号衰减成所需的功率信号，从而输出至下一级电路。When receiving signals, the existing low-noise amplifier circuit may receive high-power signals. At this time, the signal does not need to be amplified again, but needs to be attenuated to a certain extent so that the high-power signal is attenuated into the required power signal, so as to be output to the next stage circuit.
但现有的低噪声放大器电路只存在对信号进行放大的放大单元，其并不存在对接收到的大功率信号进行衰减的相关电路，即现有低噪声放大器电路并不能对大功率信号进行衰减，相应的则是现有的低噪声放大器的下一级电路低功率需求和射频接收模组接收到过大功率信号之间存在矛盾。However, the existing low-noise amplifier circuit only has an amplification unit for amplifying the signal, and does not have a related circuit for attenuating the received high-power signal. That is, the existing low-noise amplifier circuit cannot attenuate the high-power signal. Correspondingly, there is a contradiction between the low-power requirement of the next-level circuit of the existing low-noise amplifier and the excessively high-power signal received by the RF receiving module.
因此，有必要提供一种射频接收模组旁路模式下的无源电路以及射频接收模组来解决上述问题。Therefore, it is necessary to provide a passive circuit in the bypass mode of the RF receiving module and a RF receiving module to solve the above problems.
【实用新型内容】[Utility Model Content]
本实用新型的目的在于提供一种射频接收模组旁路模式下的无源电路，以解决现有的低噪声放大器的下一级电路低功率需求和射频接收模组接收到过大功率信号之间存在矛盾的问题。 The utility model aims to provide a passive circuit in a bypass mode of a radio frequency receiving module to solve the problem of the contradiction between the low power requirement of the next stage circuit of the existing low noise amplifier and the excessive power signal received by the radio frequency receiving module.
第一方面，本实用新型提供了一种射频接收模组旁路模式下的无源电路，其包括依次连接的信号输入端、放大单元、输出匹配电路以及信号输出端；所述无源电路还包括连接至所述放大单元的输入端与所述输出匹配电路的输入端之间的衰减电路；In a first aspect, the utility model provides a passive circuit in a bypass mode of a radio frequency receiving module, which comprises a signal input terminal, an amplifying unit, an output matching circuit and a signal output terminal connected in sequence; the passive circuit further comprises an attenuation circuit connected between the input terminal of the amplifying unit and the input terminal of the output matching circuit;
所述衰减电路包括第一晶体管、第一通路、第二通路、第三通路以及第二晶体管；The attenuation circuit includes a first transistor, a first path, a second path, a third path and a second transistor;
所述第一晶体管的栅极连接至第一控制极电压，所述第一晶体管的源极作为所述衰减电路的输入端与所述放大单元的输入端连接；The gate of the first transistor is connected to a first control electrode voltage, and the source of the first transistor is connected to the input terminal of the amplification unit as the input terminal of the attenuation circuit;
所述第一通路的第一端、所述第二通路的第一端以及所述第三通路的第一端均与所述第一晶体管的漏极连接；The first end of the first path, the first end of the second path and the first end of the third path are all connected to the drain of the first transistor;
所述第二晶体管的栅极连接至第二控制极电压，所述第二晶体管的源极分别与所述第一通路的第二端、所述第二通路的第二端以及所述第三通路的第二端连接，所述第二晶体管的漏极作为所述衰减电路的输出端与所述输出匹配电路的输入端连接；The gate of the second transistor is connected to a second control electrode voltage, the source of the second transistor is respectively connected to the second end of the first path, the second end of the second path and the second end of the third path, and the drain of the second transistor is connected to the input end of the output matching circuit as the output end of the attenuation circuit;
所述第一通路、所述第二通路以及所述第三通路分别用于对所述信号输入端输入的信号进行不同程度的衰减；所述无源电路处于所述射频接收模组旁路模式时，所述信号输入端接收的信号经过所述衰减电路进行不同程度的衰减后输出至所述输出匹配电路的输入端。The first path, the second path and the third path are respectively used to attenuate the signal input to the signal input end to different degrees; when the passive circuit is in the bypass mode of the RF receiving module, the signal received by the signal input end is attenuated to different degrees by the attenuation circuit and then output to the input end of the output matching circuit.
更优的，所述第一通路包括第三晶体管、第一电阻、第二电阻、第三电阻以及第四晶体管；More preferably, the first path includes a third transistor, a first resistor, a second resistor, a third resistor and a fourth transistor;
所述第三晶体管的栅极连接至第三控制极电压，所述第三晶体管的源极作为所述第一通路的第一端与所述第一晶体管的漏极连接；The gate of the third transistor is connected to a third control electrode voltage, and the source of the third transistor is connected to the drain of the first transistor as the first end of the first path;
所述第一电阻的第一端与所述第三晶体管的漏极连接；The first end of the first resistor is connected to the drain of the third transistor;
所述第二电阻的第一端与所述第一电阻的第二端连接，所述第二电阻的第二端接地；The first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is grounded;
所述第三电阻的第一端与所述第一电阻的第二端连接；The first end of the third resistor is connected to the second end of the first resistor;
所述第四晶体管的栅极连接至第四控制极电压，所述第四晶体管的源极与所述第三电阻的第二端连接，所述第四晶体管的漏极作为所 述第一通路的第二端与所述第二晶体管的源极连接。The gate of the fourth transistor is connected to the fourth control electrode voltage, the source of the fourth transistor is connected to the second end of the third resistor, and the drain of the fourth transistor is used as the The second end of the first path is connected to the source of the second transistor.
更优的，所述第二通路包括第五晶体管、第四电阻、第五电阻以及第第六晶体管；More preferably, the second path includes a fifth transistor, a fourth resistor, a fifth resistor and a sixth transistor;
所述第五晶体管的栅极连接至第五控制极电压，所述第五晶体管的源极作为所述第二通路的第一端与所述第一晶体管的漏极连接；The gate of the fifth transistor is connected to a fifth control electrode voltage, and the source of the fifth transistor is connected to the drain of the first transistor as the first end of the second path;
所述第四电阻的第一端与所述第五晶体管的漏极连接；The first end of the fourth resistor is connected to the drain of the fifth transistor;
所述第五电阻的第一端与所述第四电阻的第二端连接；The first end of the fifth resistor is connected to the second end of the fourth resistor;
所述第六晶体管的栅极连接至第六控制极电压，所述第六晶体管的源极与所述第五电阻的第二端连接，所述第六晶体管的漏极作为第二通路的第二端与所述第二晶体管源极连接。The gate of the sixth transistor is connected to a sixth control electrode voltage, the source of the sixth transistor is connected to the second end of the fifth resistor, and the drain of the sixth transistor is connected to the source of the second transistor as the second end of the second path.
更优的，所述第三通路包括第七晶体管、第六电阻以及第八晶体管；More preferably, the third path includes a seventh transistor, a sixth resistor and an eighth transistor;
所述第七晶体管的栅极连接至第七控制极电压，所述第七晶体管的源极作为所述第三通路的第一端与所述第一晶体管的漏极连接；The gate of the seventh transistor is connected to a seventh control electrode voltage, and the source of the seventh transistor is connected to the drain of the first transistor as the first end of the third path;
所述第六电阻的第一端与所述第七晶体管的漏极连接；The first end of the sixth resistor is connected to the drain of the seventh transistor;
所述第八晶体管的栅极连接至第八控制极电压，所述第八晶体管的源极与所述第六电阻的第二端连接，所述第八晶体管的漏极作为第三通路的第二端与所述第二晶体管的源极连接。The gate of the eighth transistor is connected to the eighth control electrode voltage, the source of the eighth transistor is connected to the second end of the sixth resistor, and the drain of the eighth transistor is connected to the source of the second transistor as the second end of the third path.
更优的，所述衰减电路还包括第一电容，所述第一电容串联至所述第二晶体管的漏极与所述输出匹配电路的输入端之间。More preferably, the attenuation circuit further includes a first capacitor, which is connected in series between the drain of the second transistor and the input end of the output matching circuit.
更优的，所述放大单元包括第九晶体管以及第十晶体管；More preferably, the amplifying unit includes a ninth transistor and a tenth transistor;
所述第九晶体管的栅极作为所述放大单元的输入端并与所述信号输入端连接，所述第九晶体管的源极接地；The gate of the ninth transistor serves as the input terminal of the amplifying unit and is connected to the signal input terminal, and the source of the ninth transistor is grounded;
所述第十晶体管的栅极连接至供电电压，所述第十晶体管的源极与所述第九晶体管的漏极连接，所述第十晶体管的漏极与所述输出匹配电路的输入端连接。The gate of the tenth transistor is connected to the power supply voltage, the source of the tenth transistor is connected to the drain of the ninth transistor, and the drain of the tenth transistor is connected to the input terminal of the output matching circuit.
更优的，所述放大单元还包括反馈电感，所述反馈电感的第一端与所述第九晶体管的源极连接，所述反馈电感的第二端接地。 More preferably, the amplifying unit further includes a feedback inductor, a first end of the feedback inductor is connected to the source of the ninth transistor, and a second end of the feedback inductor is grounded.
更优的，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管、所述第九晶体管以及所述第十晶体管均为NMOS管。More preferably, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are all NMOS transistors.
更优的，所述输出匹配电路包括供电电感和第二电容；More preferably, the output matching circuit includes a power supply inductor and a second capacitor;
所述供电电感的第一端连接至电源电压；The first end of the power supply inductor is connected to a power supply voltage;
所述第二电容的第一端与所述供电电感的第二端连接并作为所述输出匹配电路的输入端，所述第二电容的第二端与所述信号输出端连接。The first end of the second capacitor is connected to the second end of the power supply inductor and serves as the input end of the output matching circuit, and the second end of the second capacitor is connected to the signal output end.
第二方面，本实用新型提供了一种射频接收模组，所述射频接收模组包括如上所述的射频接收模组旁路模式下的无源电路。In a second aspect, the utility model provides a radio frequency receiving module, wherein the radio frequency receiving module includes the passive circuit in the radio frequency receiving module bypass mode as described above.
与现有技术相比，本实用新型的射频接收模组旁路模式下的无源电路通过在放大单元的输入端与输出匹配电路的输入端之间增设用于对信号输入端接收的信号进行不同程度衰减的衰减电路，并将衰减后的信号输出至输出匹配电路的输入端，从而实现了对大功率信号进行衰减后输出的功能，进而可以使大功率信号衰减成所需的功率信号以输出至下一级电路，即解决了现有低噪声放大器的下一级电路低功率需求和射频接收模组接收到过大功率信号之间存在的矛盾。Compared with the prior art, the passive circuit in the bypass mode of the RF receiving module of the utility model realizes the function of attenuating and outputting a high-power signal by adding an attenuation circuit between the input end of the amplification unit and the input end of the output matching circuit for attenuating the signal received at the signal input end to different degrees, and outputting the attenuated signal to the input end of the output matching circuit, thereby attenuating the high-power signal into the required power signal to be output to the next-stage circuit, thereby solving the contradiction between the low-power requirement of the next-stage circuit of the existing low-noise amplifier and the excessively high-power signal received by the RF receiving module.
【附图说明】【Brief Description of the Drawings】
为了更清楚地说明本实用新型实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本实用新型的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图，其中：In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:
图1为本实用新型实施例提供的一种射频接收模组旁路模式下的无源电路的电路图。FIG1 is a circuit diagram of a passive circuit in a bypass mode of a radio frequency receiving module provided by an embodiment of the present utility model.
【具体实施方式】 【Detailed ways】
下面将结合本实用新型实施例中的附图，对本实用新型实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本实用新型的一部分实施例，而不是全部的实施例。基于本实用新型中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本实用新型保护的范围。The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
本实用新型实施例提供了一种射频接收模组旁路模式下的无源电路100，结合图1所示，其包括依次连接的信号输入端VIN、放大单元10、输出匹配电路20以及信号输出端VOUT；无源电路100还包括连接至放大单元10的输入端与输出匹配电路20的输入端之间的衰减电路30。An embodiment of the utility model provides a passive circuit 100 in a bypass mode of a radio frequency receiving module, as shown in FIG. 1 , which includes a signal input terminal VIN, an amplifying unit 10, an output matching circuit 20 and a signal output terminal VOUT connected in sequence; the passive circuit 100 also includes an attenuation circuit 30 connected between the input terminal of the amplifying unit 10 and the input terminal of the output matching circuit 20.
其中，射频接收模组旁路模式下的无源电路100以下可以简称为无源电路100。Among them, the passive circuit 100 in the bypass mode of the RF receiving module may be referred to as the passive circuit 100 hereinafter.
衰减电路30包括第一晶体管S1、第一通路31、第二通路32、第三通路33以及第二晶体管S8。The attenuation circuit 30 includes a first transistor S1 , a first path 31 , a second path 32 , a third path 33 and a second transistor S8 .
第一晶体管S1的栅极连接至第一控制极电压VG1，第一晶体管S1的源极作为衰减电路30的输入端与放大单元10的输入端连接。The gate of the first transistor S1 is connected to the first control electrode voltage VG1 , and the source of the first transistor S1 is connected to the input terminal of the amplification unit 10 as the input terminal of the attenuation circuit 30 .
第一通路31的第一端、第二通路32的第一端以及第三通路33的第一端均与第一晶体管S1的漏极连接。A first end of the first path 31 , a first end of the second path 32 , and a first end of the third path 33 are all connected to the drain of the first transistor S1 .
第二晶体管S8的栅极连接至第二控制极电压VG8，第二晶体管S8的源极分别与第一通路31的第二端、第二通路32的第二端以及第三通路33的第二端连接，第二晶体管S8的漏极作为衰减电路30的输出端与输出匹配电路20的输入端连接。The gate of the second transistor S8 is connected to the second control electrode voltage VG8, the source of the second transistor S8 is respectively connected to the second end of the first path 31, the second end of the second path 32 and the second end of the third path 33, and the drain of the second transistor S8 is connected to the input end of the output matching circuit 20 as the output end of the attenuation circuit 30.
第一通路31、第二通路32以及第三通路33分别用于对信号输入端VIN输入的信号进行不同程度的衰减；无源电路100处于射频接收模组旁路模式时，信号输入端VIN接收的信号经过衰减电路30进行不同程度的衰减后输出至输出匹配电路20的输入端。The first path 31, the second path 32 and the third path 33 are respectively used to attenuate the signal input to the signal input terminal VIN to different degrees; when the passive circuit 100 is in the RF receiving module bypass mode, the signal received by the signal input terminal VIN is attenuated to different degrees by the attenuation circuit 30 and then output to the input terminal of the output matching circuit 20.
本实施例中，第一通路31包括第三晶体管S2、第一电阻R4、第二电阻R6、第三电阻R5以及第四晶体管S3。 In this embodiment, the first path 31 includes a third transistor S2 , a first resistor R4 , a second resistor R6 , a third resistor R5 and a fourth transistor S3 .
第三晶体管S2的栅极连接至第三控制极电压VG2，第三晶体管S2的源极作为第一通路31的第一端与第一晶体管S1的漏极连接。The gate of the third transistor S2 is connected to the third control electrode voltage VG2 , and the source of the third transistor S2 is connected to the drain of the first transistor S1 as the first end of the first path 31 .
第一电阻R4的第一端与第三晶体管S2的漏极连接。A first end of the first resistor R4 is connected to the drain of the third transistor S2.
第二电阻R6的第一端与第一电阻R4的第二端连接，第二电阻R6的第二端接地。A first end of the second resistor R6 is connected to the second end of the first resistor R4 , and a second end of the second resistor R6 is grounded.
第三电阻R5的第一端与第一电阻R4的第二端连接。A first end of the third resistor R5 is connected to a second end of the first resistor R4.
第四晶体管S3的栅极连接至第四控制极电压VG3，第四晶体管S3的源极与第三电阻R5的第二端连接，第四晶体管S3的漏极作为第一通路31的第二端与第二晶体管S8的源极连接。The gate of the fourth transistor S3 is connected to the fourth control electrode voltage VG3 , the source of the fourth transistor S3 is connected to the second end of the third resistor R5 , and the drain of the fourth transistor S3 is connected to the source of the second transistor S8 as the second end of the first path 31 .
本实施例中，第二通路32包括第五晶体管S4、第四电阻R2、第五电阻R3以及第第六晶体管S5。In this embodiment, the second path 32 includes a fifth transistor S4 , a fourth resistor R2 , a fifth resistor R3 , and a sixth transistor S5 .
第五晶体管S4的栅极连接至第五控制极电压VG4，第五晶体管S4的源极作为第二通路32的第一端与第一晶体管S1的漏极连接。The gate of the fifth transistor S4 is connected to the fifth control electrode voltage VG4 , and the source of the fifth transistor S4 is connected to the drain of the first transistor S1 as the first end of the second path 32 .
第四电阻R2的第一端与第五晶体管S4的漏极连接。A first end of the fourth resistor R2 is connected to the drain of the fifth transistor S4.
第五电阻R3的第一端与第四电阻R2的第二端连接。A first end of the fifth resistor R3 is connected to a second end of the fourth resistor R2.
第六晶体管S5的栅极连接至第六控制极电压VG5，第六晶体管S5的源极与第五电阻R3的第二端连接，第六晶体管S5的漏极作为第二通路32的第二端与第二晶体管S8源极连接。The gate of the sixth transistor S5 is connected to the sixth control electrode voltage VG5, the source of the sixth transistor S5 is connected to the second end of the fifth resistor R3, and the drain of the sixth transistor S5 is connected to the source of the second transistor S8 as the second end of the second path 32.
本实施例中，第三通路33包括第七晶体管S6、第六电阻R1以及第八晶体管S7。In this embodiment, the third path 33 includes a seventh transistor S6 , a sixth resistor R1 , and an eighth transistor S7 .
第七晶体管S6的栅极连接至第七控制极电压VG6，第七晶体管S6的源极作为第三通路33的第一端与第一晶体管S1的漏极连接。The gate of the seventh transistor S6 is connected to the seventh control electrode voltage VG6 , and the source of the seventh transistor S6 is connected to the drain of the first transistor S1 as the first end of the third path 33 .
第六电阻R1的第一端与第七晶体管S6的漏极连接。A first end of the sixth resistor R1 is connected to a drain of the seventh transistor S6 .
第八晶体管S7的栅极连接至第八控制极电压VG7，第八晶体管S7的源极与第六电阻R1的第二端连接，第八晶体管S7的漏极作为第三通路33的第二端与第二晶体管S8的源极连接。The gate of the eighth transistor S7 is connected to the eighth control electrode voltage VG7, the source of the eighth transistor S7 is connected to the second end of the sixth resistor R1, and the drain of the eighth transistor S7 is connected to the source of the second transistor S8 as the second end of the third path 33.
本实施例中，衰减电路30还包括第一电容C1，第一电容C1串联至第二晶体管S8的漏极与输出匹配电路20的输入端之间。 In this embodiment, the attenuation circuit 30 further includes a first capacitor C1 , which is connected in series between the drain of the second transistor S8 and the input terminal of the output matching circuit 20 .
本实施例中，放大单元10包括第九晶体管M1以及第十晶体管M2。In this embodiment, the amplifying unit 10 includes a ninth transistor M1 and a tenth transistor M2 .
第九晶体管M1的栅极作为放大单元10的输入端并与信号输入端VIN连接，第九晶体管M1的源极接地。The gate of the ninth transistor M1 serves as the input terminal of the amplifying unit 10 and is connected to the signal input terminal VIN, and the source of the ninth transistor M1 is grounded.
第十晶体管M2的栅极连接至供电电压Vb，第十晶体管M2的源极与第九晶体管M1的漏极连接，第十晶体管M2的漏极与输出匹配电路20的输入端连接。A gate of the tenth transistor M2 is connected to the power supply voltage Vb, a source of the tenth transistor M2 is connected to a drain of the ninth transistor M1 , and a drain of the tenth transistor M2 is connected to an input terminal of the output matching circuit 20 .
另外，放大单元10还包括反馈电感Ls，反馈电感Ls的第一端与第九晶体管M1的源极连接，反馈电感Ls的第二端接地。In addition, the amplifying unit 10 further includes a feedback inductor Ls, a first end of the feedback inductor Ls is connected to the source of the ninth transistor M1 , and a second end of the feedback inductor Ls is grounded.
本实施例中，第一晶体管S1、第二晶体管S8、第三晶体管S2、第四晶体管S3、第五晶体管S4、第六晶体管S5、第七晶体管S6、第八晶体管S7、第九晶体管M1以及第十晶体管M2均为NMOS管。当然，根据实际需求，第一晶体管S1至第十晶体管M2还可以任意选用其它可替代的晶体管。In this embodiment, the first transistor S1, the second transistor S8, the third transistor S2, the fourth transistor S3, the fifth transistor S4, the sixth transistor S5, the seventh transistor S6, the eighth transistor S7, the ninth transistor M1 and the tenth transistor M2 are all NMOS transistors. Of course, according to actual needs, the first transistor S1 to the tenth transistor M2 can also be arbitrarily selected from other replaceable transistors.
本实施例中，输出匹配电路20包括供电电感Ld和第二电容C1。In this embodiment, the output matching circuit 20 includes a power supply inductor Ld and a second capacitor C1.
供电电感Ld的第一端连接至电源电压VDD。A first terminal of the power supply inductor Ld is connected to a power supply voltage VDD.
第二电容C1的第一端与供电电感Ld的第二端连接并作为输出匹配电路20的输入端，第二电容C1的第二端与信号输出端VOUT连接。A first end of the second capacitor C1 is connected to the second end of the power supply inductor Ld and serves as an input end of the output matching circuit 20 , and a second end of the second capacitor C1 is connected to the signal output end VOUT.
本实施例中，第一通路31、第二通路32以及第三通路33分别用于对信号输入端VIN输入的信号进行不同程度的衰减，然后经过供电电感Ld和第二电容C1组成的输出匹配网络(输出匹配电路20)进行输出，由于有供电电感Ld和第二电容C1组成的输出匹配网路的匹配作用，旁路模式下输出的信号会得到较大程度的改善，能更好的和负载进行匹配，减小反射产生的损耗。In this embodiment, the first path 31, the second path 32 and the third path 33 are respectively used to attenuate the signal input from the signal input terminal VIN to different degrees, and then output it through the output matching network (output matching circuit 20) composed of the power supply inductor Ld and the second capacitor C1. Due to the matching effect of the output matching network composed of the power supply inductor Ld and the second capacitor C1, the signal output in the bypass mode will be greatly improved, and can be better matched with the load, reducing the loss caused by reflection.
本实施例中，供电电感Ld和第二电容C1组成低噪声放大器的输出匹配网络，供电电感Ld同时起到供电的作用，在旁路模式下，第九晶体管M1和第十晶体管M2不具备放大作用，信号不再从第九晶体管M1和第十晶体管M2通过。 In this embodiment, the power supply inductor Ld and the second capacitor C1 form an output matching network of the low noise amplifier. The power supply inductor Ld also plays a role of power supply. In the bypass mode, the ninth transistor M1 and the tenth transistor M2 do not have an amplification effect, and the signal no longer passes through the ninth transistor M1 and the tenth transistor M2.
本实施例中，第九晶体管M1和第十晶体管M2组成共源极共栅极结构的低噪声放大器，供电电感Ld为低噪声放大器的漏极电感，反馈电感Ls为低噪声放大器的源极反馈的电感，第二电容C1形成输出匹配电容，第二电容C1为隔直电容，第一晶体管S1至第八晶体管S7均为MOS开关，第一电阻R4至第六电阻R1均为旁路模式下的衰减电阻，第一控制极电压VG1至第八控制极电压VG7均为MOS开关的控制电压。In this embodiment, the ninth transistor M1 and the tenth transistor M2 form a low-noise amplifier with a common source and common gate structure, the power supply inductor Ld is the drain inductance of the low-noise amplifier, the feedback inductor Ls is the inductance of the source feedback of the low-noise amplifier, the second capacitor C1 forms an output matching capacitor, the second capacitor C1 is a DC blocking capacitor, the first transistor S1 to the eighth transistor S7 are all MOS switches, the first resistor R4 to the sixth resistor R1 are all attenuation resistors in bypass mode, and the first control electrode voltage VG1 to the eighth control electrode voltage VG7 are all control voltages of the MOS switches.
当需要工作在旁路模式时，第一控制极电压VG1至第八控制极电压VG7分别控制第一晶体管S1至第八晶体管S7的开启，此时旁路的通路打开。根据需要，第三控制极电压VG2至第八控制极电压VG7开启第三晶体管S2至第八晶体管S7，注意每个通路上的两个晶体管是同时开启，通过控制不同通路的开关的开启或关段，可以得到不同的等效阻值，实现信号增益的可调节。When it is necessary to work in the bypass mode, the first control electrode voltage VG1 to the eighth control electrode voltage VG7 respectively control the opening of the first transistor S1 to the eighth transistor S7, and the bypass path is opened. According to the needs, the third control electrode voltage VG2 to the eighth control electrode voltage VG7 turn on the third transistor S2 to the eighth transistor S7. Note that the two transistors on each path are turned on at the same time. By controlling the opening or closing of the switches of different paths, different equivalent resistance values can be obtained to achieve adjustable signal gain.
本实施例中所描述的“连接”均为电连接或电性连接，即连接的两个器件或多个器件均为电连接或电性连接。The “connections” described in this embodiment are all electrical connections or electrical connections, that is, the two or more connected devices are all electrically connected or electrically connected.
与现有技术相比，本实用新型的射频接收模组旁路模式下的无源电路100通过在放大单元10的输入端与输出匹配电路20的输入端之间增设用于对信号输入端VIN接收的信号进行不同程度衰减的衰减电路30，并将衰减后的信号输出至输出匹配电路20的输入端，从而实现了对大功率信号进行衰减后输出的功能，进而可以使大功率信号衰减成所需的功率信号以输出至下一级电路，即解决了现有低噪声放大器的下一级电路低功率需求和射频接收模组接收到过大功率信号之间存在的矛盾。Compared with the prior art, the passive circuit 100 of the RF receiving module in bypass mode of the utility model realizes the function of attenuating and outputting a high-power signal by adding an attenuation circuit 30 between the input end of the amplification unit 10 and the input end of the output matching circuit 20 for attenuating the signal received at the signal input end VIN to different degrees, and outputting the attenuated signal to the input end of the output matching circuit 20, thereby attenuating the high-power signal into a required power signal to be output to the next-stage circuit, thereby solving the contradiction between the low-power requirement of the next-stage circuit of the existing low-noise amplifier and the excessively high-power signal received by the RF receiving module.
本实用新型还提供了另一实施例，一种射频接收模组，射频接收模组包括如上述实施例中的射频接收模组旁路模式下的无源电路100。The present invention also provides another embodiment, a radio frequency receiving module, which includes the passive circuit 100 in the bypass mode of the radio frequency receiving module in the above embodiment.
由于本实施例中的射频接收模组包括了上述实施例中的射频接收模组旁路模式下的无源电路100，因此其也能达到上述实施例中射频接收模组旁路模式下的无源电路100所达到的技术效果，在此不作赘 述。Since the RF receiving module in this embodiment includes the passive circuit 100 in the bypass mode of the RF receiving module in the above embodiment, it can also achieve the technical effect achieved by the passive circuit 100 in the bypass mode of the RF receiving module in the above embodiment, and no further explanation is given here. State.
以上所述的仅是本实用新型的实施方式，在此应当指出，对于本领域的普通技术人员来说，在不脱离本实用新型创造构思的前提下，还可以做出改进，但这些均属于本实用新型的保护范围。 The above is only an implementation method of the present invention. It should be pointed out that a person skilled in the art can make improvements without departing from the inventive concept of the present invention, but these improvements are all within the protection scope of the present invention.

Claims (10)

  1. 一种射频接收模组旁路模式下的无源电路，包括依次连接的信号输入端、放大单元、输出匹配电路以及信号输出端；其特征在于，所述无源电路还包括连接至所述放大单元的输入端与所述输出匹配电路的输入端之间的衰减电路；A passive circuit in a bypass mode of a radio frequency receiving module, comprising a signal input terminal, an amplifying unit, an output matching circuit and a signal output terminal connected in sequence; characterized in that the passive circuit also includes an attenuation circuit connected between the input terminal of the amplifying unit and the input terminal of the output matching circuit;
    所述衰减电路包括第一晶体管、第一通路、第二通路、第三通路以及第二晶体管；The attenuation circuit includes a first transistor, a first path, a second path, a third path and a second transistor;
    所述第一晶体管的栅极连接至第一控制极电压，所述第一晶体管的源极作为所述衰减电路的输入端与所述放大单元的输入端连接；The gate of the first transistor is connected to a first control electrode voltage, and the source of the first transistor is connected to the input terminal of the amplification unit as the input terminal of the attenuation circuit;
    所述第一通路的第一端、所述第二通路的第一端以及所述第三通路的第一端均与所述第一晶体管的漏极连接；The first end of the first path, the first end of the second path and the first end of the third path are all connected to the drain of the first transistor;
    所述第二晶体管的栅极连接至第二控制极电压，所述第二晶体管的源极分别与所述第一通路的第二端、所述第二通路的第二端以及所述第三通路的第二端连接，所述第二晶体管的漏极作为所述衰减电路的输出端与所述输出匹配电路的输入端连接；The gate of the second transistor is connected to a second control electrode voltage, the source of the second transistor is respectively connected to the second end of the first path, the second end of the second path and the second end of the third path, and the drain of the second transistor is connected to the input end of the output matching circuit as the output end of the attenuation circuit;
    所述第一通路、所述第二通路以及所述第三通路分别用于对所述信号输入端输入的信号进行不同程度的衰减；所述无源电路处于所述射频接收模组旁路模式时，所述信号输入端接收的信号经过所述衰减电路进行不同程度的衰减后输出至所述输出匹配电路的输入端。The first path, the second path and the third path are respectively used to attenuate the signal input to the signal input end to different degrees; when the passive circuit is in the bypass mode of the RF receiving module, the signal received by the signal input end is attenuated to different degrees by the attenuation circuit and then output to the input end of the output matching circuit.
  2. 如权利要求1所述的射频接收模组旁路模式下的无源电路，其特征在于，所述第一通路包括第三晶体管、第一电阻、第二电阻、第三电阻以及第四晶体管；The passive circuit in the bypass mode of the RF receiving module according to claim 1, characterized in that the first path includes a third transistor, a first resistor, a second resistor, a third resistor and a fourth transistor;
    所述第三晶体管的栅极连接至第三控制极电压，所述第三晶体管的源极作为所述第一通路的第一端与所述第一晶体管的漏极连接；The gate of the third transistor is connected to a third control electrode voltage, and the source of the third transistor is connected to the drain of the first transistor as the first end of the first path;
    所述第一电阻的第一端与所述第三晶体管的漏极连接；The first end of the first resistor is connected to the drain of the third transistor;
    所述第二电阻的第一端与所述第一电阻的第二端连接，所述第二电阻的第二端接地；The first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is grounded;
    所述第三电阻的第一端与所述第一电阻的第二端连接； The first end of the third resistor is connected to the second end of the first resistor;
    所述第四晶体管的栅极连接至第四控制极电压，所述第四晶体管的源极与所述第三电阻的第二端连接，所述第四晶体管的漏极作为所述第一通路的第二端与所述第二晶体管的源极连接。The gate of the fourth transistor is connected to a fourth control electrode voltage, the source of the fourth transistor is connected to the second end of the third resistor, and the drain of the fourth transistor is connected to the source of the second transistor as the second end of the first path.
  3. 如权利要求2所述的射频接收模组旁路模式下的无源电路，其特征在于，所述第二通路包括第五晶体管、第四电阻、第五电阻以及第第六晶体管；The passive circuit in the bypass mode of the RF receiving module according to claim 2, characterized in that the second path includes a fifth transistor, a fourth resistor, a fifth resistor and a sixth transistor;
    所述第五晶体管的栅极连接至第五控制极电压，所述第五晶体管的源极作为所述第二通路的第一端与所述第一晶体管的漏极连接；The gate of the fifth transistor is connected to a fifth control electrode voltage, and the source of the fifth transistor is connected to the drain of the first transistor as the first end of the second path;
    所述第四电阻的第一端与所述第五晶体管的漏极连接；The first end of the fourth resistor is connected to the drain of the fifth transistor;
    所述第五电阻的第一端与所述第四电阻的第二端连接；The first end of the fifth resistor is connected to the second end of the fourth resistor;
    所述第六晶体管的栅极连接至第六控制极电压，所述第六晶体管的源极与所述第五电阻的第二端连接，所述第六晶体管的漏极作为第二通路的第二端与所述第二晶体管源极连接。The gate of the sixth transistor is connected to a sixth control electrode voltage, the source of the sixth transistor is connected to the second end of the fifth resistor, and the drain of the sixth transistor is connected to the source of the second transistor as the second end of the second path.
  4. 如权利要求3所述的射频接收模组旁路模式下的无源电路，其特征在于，所述第三通路包括第七晶体管、第六电阻以及第八晶体管；The passive circuit in the bypass mode of the RF receiving module according to claim 3, characterized in that the third path includes a seventh transistor, a sixth resistor and an eighth transistor;
    所述第七晶体管的栅极连接至第七控制极电压，所述第七晶体管的源极作为所述第三通路的第一端与所述第一晶体管的漏极连接；The gate of the seventh transistor is connected to a seventh control electrode voltage, and the source of the seventh transistor is connected to the drain of the first transistor as the first end of the third path;
    所述第六电阻的第一端与所述第七晶体管的漏极连接；The first end of the sixth resistor is connected to the drain of the seventh transistor;
    所述第八晶体管的栅极连接至第八控制极电压，所述第八晶体管的源极与所述第六电阻的第二端连接，所述第八晶体管的漏极作为第三通路的第二端与所述第二晶体管的源极连接。The gate of the eighth transistor is connected to the eighth control electrode voltage, the source of the eighth transistor is connected to the second end of the sixth resistor, and the drain of the eighth transistor is connected to the source of the second transistor as the second end of the third path.
  5. 如权利要求4所述的射频接收模组旁路模式下的无源电路，其特征在于，所述衰减电路还包括第一电容，所述第一电容串联至所述第二晶体管的漏极与所述输出匹配电路的输入端之间。The passive circuit in the bypass mode of the RF receiving module as described in claim 4 is characterized in that the attenuation circuit also includes a first capacitor, and the first capacitor is connected in series between the drain of the second transistor and the input end of the output matching circuit.
  6. 如权利要求1至5任意一项所述的射频接收模组旁路模式下的无源电路，其特征在于，所述放大单元包括第九晶体管以及第十晶体管；The passive circuit in the bypass mode of the RF receiving module according to any one of claims 1 to 5, characterized in that the amplification unit includes a ninth transistor and a tenth transistor;
    所述第九晶体管的栅极作为所述放大单元的输入端并与所述信号 输入端连接，所述第九晶体管的源极接地；The gate of the ninth transistor serves as the input terminal of the amplifying unit and is connected to the signal The input terminal is connected, and the source of the ninth transistor is grounded;
    所述第十晶体管的栅极连接至供电电压，所述第十晶体管的源极与所述第九晶体管的漏极连接，所述第十晶体管的漏极与所述输出匹配电路的输入端连接。The gate of the tenth transistor is connected to the power supply voltage, the source of the tenth transistor is connected to the drain of the ninth transistor, and the drain of the tenth transistor is connected to the input terminal of the output matching circuit.
  7. 如权利要求6所述的射频接收模组旁路模式下的无源电路，其特征在于，所述放大单元还包括反馈电感，所述反馈电感的第一端与所述第九晶体管的源极连接，所述反馈电感的第二端接地。The passive circuit in the bypass mode of the RF receiving module as described in claim 6 is characterized in that the amplification unit also includes a feedback inductor, a first end of the feedback inductor is connected to the source of the ninth transistor, and a second end of the feedback inductor is grounded.
  8. 如权利要求6所述的射频接收模组旁路模式下的无源电路，其特征在于，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管、所述第九晶体管以及所述第十晶体管均为NMOS管。The passive circuit in the bypass mode of the RF receiving module as described in claim 6 is characterized in that the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are all NMOS transistors.
  9. 如权利要求6所述的射频接收模组旁路模式下的无源电路，其特征在于，所述输出匹配电路包括供电电感和第二电容；The passive circuit in the bypass mode of the radio frequency receiving module according to claim 6, characterized in that the output matching circuit includes a power supply inductor and a second capacitor;
    所述供电电感的第一端连接至电源电压；The first end of the power supply inductor is connected to a power supply voltage;
    所述第二电容的第一端与所述供电电感的第二端连接并作为所述输出匹配电路的输入端，所述第二电容的第二端与所述信号输出端连接。The first end of the second capacitor is connected to the second end of the power supply inductor and serves as the input end of the output matching circuit, and the second end of the second capacitor is connected to the signal output end.
  10. 一种射频接收模组，其特征在于，所述射频接收模组包括权利要求1至9任意一项所述的射频接收模组旁路模式下的无源电路。 A radio frequency receiving module, characterized in that the radio frequency receiving module comprises the passive circuit in the radio frequency receiving module bypass mode as described in any one of claims 1 to 9.
PCT/CN2023/125997 2022-11-07 2023-10-23 Passive circuit in radio frequency receiving module bypass mode, and radio frequency receiving module WO2024099060A1 (en)

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