WO2018054151A1

WO2018054151A1 - Low-noise amplifier circuit

Info

Publication number: WO2018054151A1
Application number: PCT/CN2017/093246
Authority: WO
Inventors: 陈家诚; 范丛明; 姚建可; 丁庆
Original assignee: 深圳市华讯方舟卫星通信有限公司; 华讯方舟科技有限公司
Priority date: 2016-09-26
Filing date: 2017-07-18
Publication date: 2018-03-29
Also published as: CN106330107A; CN106330107B; CN108566167A; CN108566167B

Abstract

A low-noise amplifier circuit, comprising cascaded multiple stages of low-noise amplifiers (M1, M2, …, Mn), and a first biasing unit (110) or a second biasing unit (120) which is used for biasing each stage of the low-noise amplifiers (M1, M2, …, Mn). The first biasing unit (110) is used for biasing a forward-stage low-noise amplifier in the multiple stages of low-noise amplifiers (M1, M2, …, Mn). The second biasing unit (120) is used for a backward-stage low-noise amplifier in the multiple stages of low-noise amplifiers (M1, M2, …, Mn). The second biasing unit (120) is also used for providing a bias voltage to the first biasing unit (110). Alternatively, the first biasing unit (110) is used for biasing each of the multiple stages of low-noise amplifiers (M1, M2, …, Mn). Only one or two biasing units are required for biasing multiple stages of low-noise amplifiers (M1, M2, …, Mn) in the low-noise amplifier circuit to enable each stage of low-noise amplifiers work in an optimal state. The low-noise amplifier circuit is simple in structure and low in costs, and also saves the usable area of a PCB board.

Description

Low noise amplifier circuit

Technical field

The present invention relates to the field of electronic circuit technology, and more particularly to a low noise amplifying circuit.

Background technique

The use of Ka-band broadband satellites will become the industry trend for satellite broadband communications in the future. The Ka band is mainly 26.5 to 40 GHz, which greatly increases the bandwidth of communication. A range of supporting equipment and components are critical to the construction of the entire communications network. Among them, for ground stations, transceivers are the key components for building ground stations. In applications for satellite broadcasting, the transceiver's low noise block (LNB) is the most critical module for receiving signals. The down-conversion module receives the weak signal transmitted from the satellite, and the down-conversion module amplifies and down-converts it into an intermediate frequency signal, and then performs subsequent processing through the modem.

Since the noise figure of the receiver system is mainly determined by the low noise amplifier, it is particularly important to design an amplifier with reasonable gain, low noise, reliable performance and large dynamic range in the design of the receiving front end. The conventional low-noise amplifier circuit is composed of a plurality of complicated electronic components, and has high cost and a large area occupied by the PCB.

Summary of the invention

Based on this, it is necessary to provide a low noise amplifying circuit for the problem that the circuit structure is complicated, the cost is high, and the PCB board area is large.

A low noise amplifying circuit comprising a cascaded multi-stage low noise amplifier, a first bias unit or a second bias unit biasing each stage of the low noise amplifier, wherein

Deviating the front stage low noise amplifier of the plurality of stages of the low noise amplifier is the first bias unit, and the second stage of the low level noise amplifier is biased by the second stage a biasing unit, wherein the pre-stage low noise amplifier includes at least a first stage low noise amplifier, the rear stage low noise amplifier includes at least a last stage low noise amplifier, and the second bias unit is further configured to The first bias unit provides a bias voltage; or

All of the low noise amplifiers of each of the plurality of stages of the low noise amplifiers are biased by the first biasing unit.

In one embodiment, the first biasing unit includes a first transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor;

The bases of the first transistors are respectively connected to the first resistor and the second resistor, the other end of the first resistor is grounded, and the other end of the second resistor is connected to the positive voltage power supply end; The collector of the first transistor is connected to the negative voltage supply terminal via the third resistor and the fourth resistor; the emitter of the first transistor is connected to the positive voltage supply terminal via the fifth resistor;

The low noise amplifier is a transistor amplifier, a source of the transistor amplifier is grounded; a gate of the transistor amplifier is connected to a common point of the third resistor and the fourth resistor; a drain of the transistor amplifier and the first The emitter of a triode is connected.

In one embodiment, the first biasing unit is a second transistor; the emitter of the second transistor is connected to the positive voltage supply terminal via the second resistor, the second three The collector of the pole tube is connected to the base of the second transistor; the base of the second transistor is respectively connected to the base of the first resistor and the first transistor.

In one embodiment, the second biasing unit is a DC bias chip;

The DC bias chip includes a plurality of sets of correspondingly disposed gate bias pins and drain bias pins; wherein the gate bias pins provide a positive voltage to a gate of the transistor amplifier, a drain bias pin provides a negative voltage to a drain of the transistor amplifier;

Also included is a positive voltage output and a negative voltage output that provide a voltage to the first biasing unit.

In one embodiment, the low noise amplifying circuit includes a three-stage cascaded first stage transistor amplifier, a second stage transistor amplifier, and a third stage transistor amplifier.

In one embodiment, each of the first-stage transistor amplifier and the second-stage transistor amplifier is biased by the first bias unit; and the third-stage transistor amplifier is biased Two biasing unit;

The positive voltage output end of the second bias unit is respectively connected to the fifth resistor in the first bias unit; the negative voltage output end of the second bias unit is respectively connected to the first bias In the unit Fourth resistor connection;

The gate bias pin and the drain bias pin in any one of the second bias units are respectively connected to the gate and the drain of the third-stage transistor amplifier.

In one embodiment, the low noise amplifying circuit includes a PNP type universal dual transistor that simultaneously biases the first stage transistor amplifier and the second stage transistor amplifier; and biases the third stage transistor amplifier Set as a second bias unit;

The gates of the first-stage transistor amplifier and the second-stage transistor amplifier are respectively connected to the collectors of the PNP-type universal two-transistor; the drains of the first-stage transistor amplifier and the second-stage transistor amplifier are respectively An emitter connection of a PNP type universal two-transistor; a source of the first-stage transistor amplifier and the second-stage transistor amplifier is grounded;

a positive voltage output terminal of the second bias unit is coupled to an emitter of the PNP type universal dual transistor; a negative voltage output terminal of the second bias unit is coupled to a collector of the PNP type universal dual transistor;

The gate bias pin and the drain bias pin in any one of the second bias units are respectively connected to the gate and the drain of the third transistor amplifier.

In one embodiment, the first biasing unit is biased for each of the three stages of the low noise amplifiers;

The emitters of the first triodes of the first biasing unit are each loaded with a positive voltage, and the collectors of the first triodes are all loaded with a negative voltage.

In one embodiment, the first stage transistor amplifier is biased by the first bias unit; the second stage transistor amplifier and the third stage transistor amplifier are simultaneously biased by a second Offset unit

a positive voltage output end of the second bias unit is connected to a fifth resistor of the first bias unit; a negative voltage output end of the second bias unit and a first one of the first bias unit Four-resistance connection;

a first group of the gate bias pin and the drain bias pin of the second bias unit are respectively connected to a gate and a drain of the second-stage transistor amplifier; The second group of the gate bias pins and the drain bias pins of the bias unit are respectively connected to the gates and drains of the third-stage transistor amplifier.

In one embodiment, a plurality of DC blocking capacitors are further included, and the DC blocking capacitors are connected in series between two adjacent low-noise amplifiers.

The low noise amplifying circuit, comprising a cascaded multi-stage low noise amplifier, a first bias unit or a second bias unit biasing each stage of the low noise amplifier, wherein the low noise is applied to multiple stages The first biasing unit is biased by the front stage low noise amplifier in the amplifier, and the second biasing unit is biased to the second stage low noise amplifier of the plurality of low noise amplifiers, The second bias unit is further configured to provide a bias voltage to the first bias unit; or to bias the low noise amplifier of each of the plurality of low noise amplifiers unit. The multi-stage low-noise amplifier in the low-noise amplifier circuit only needs one or two kinds of bias units to bias it, so that the low-noise amplifiers of all stages can be optimally operated, and the structure is simple and the cost is low. At the same time, it also saves the use area of the PCB board.

DRAWINGS

1 is a structural block diagram of a low noise amplifying circuit of an embodiment;

2 is a circuit diagram of a first bias unit in an embodiment;

3 is a circuit diagram of a first bias unit in another embodiment;

4 is a layout diagram of a DC bias chip pin in an embodiment;

5 is a graph showing drain current-drain voltage characteristics of a transistor amplifier in an embodiment;

6 is a circuit diagram of a low noise amplifying circuit in an embodiment;

7 is a second circuit diagram of a low noise amplifying circuit in an embodiment;

8 is a third circuit diagram of a low noise amplifying circuit in an embodiment;

Figure 9 is a fourth circuit diagram of a low noise amplifying circuit in an embodiment.

detailed description

In order to facilitate the understanding of the present invention, the invention will be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the understanding of the present disclosure will be more fully understood.

All technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. The terminology used herein is for the purpose of describing the particular embodiments, The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

A low-noise amplifying circuit that amplifies a signal received or to be transmitted, so that the total noise figure in the circuit is small and the power gain is high, and the low-noise amplifying circuit can be used in the Ka band, the Ku band, and the X band. The transceiver system is medium.

Figure 1 shows the structural frame of a low-noise amplifier circuit, in which the low-noise amplifier circuit includes cascaded multi-stage low-noise amplifiers (M1, M2, ..., Mn) and biases each stage of the low-noise amplifier. The first bias unit 110 or the second bias unit 120 is disposed.

The first bias unit 110 is biased for the pre-stage low noise amplifier of the multi-stage low noise amplifier (M1, M2, ..., Mn), and is applied to the multi-stage low noise amplifier (M1, M2, ..., Mn). The stage low noise amplifier is biased by a second bias unit 120, wherein the front stage low noise amplifier includes at least a first stage low noise amplifier M1, and the latter stage low noise amplifier includes at least a last stage low noise amplifier Mn. The second bias unit 120 is further configured to provide a bias voltage to the first bias unit 110. Or the first bias unit 110 is biased for each of the multi-stage low noise amplifiers (M1, M2, ..., Mn).

In this embodiment, the low noise amplifying circuit is applied in a low noise block (LNB) of the transceiver, and the Ka band high frequency signal received by the multistage low noise amplifier (M1, M2, ..., Mn) is received. amplification. Among them, the low noise amplifier is a transistor amplifier, and the transistor amplifier uses a High Electron Mobility Transistor (HEMT) to amplify the high frequency signal. In other embodiments, the transistor amplifier may also be a Heterojunction Bipolar Transistor (HBT), a Pseudomorphic High Electron Mobility Transistor (pHEMT), or a metal-semiconductor field effect transistor. (Metal-Semiconductor FET) or Junction Field-Effect Transistor (JFET).

The high frequency signal is amplified by the multi-stage transistor amplifiers (M1, M2, ..., Mn), and each stage transistor amplifier is provided with a corresponding first bias unit 110 or second bias unit 120, The body amplifier is biased so that the transistor amplifier is in optimal operation, ie the drain voltage and drain current are operating optimally. At the same time, the second bias unit 120 can also provide a bias voltage for the first bias unit 110, which is simple in circuit design, saves design cost and material cost, and saves PCB area.

Among them, the noise figure is the most important parameter of the low noise amplifier, and the noise figure formula of the multistage cascaded low noise amplifier can be:

NF=NF ₁ +(NF ₂ -1)/G ₁ +(NF ₃ -1)/(G ₁ *G ₂ )+...

Where NF _n is the noise figure of the nth stage low noise amplifier (Noise Figure, NF), and G _n is the gain of the nth stage low noise amplifier. From the above formula, the noise of the first stage low noise amplifier and The essential. It can be seen that in order to make the total noise figure of the receiver small, the noise figure of each level of low noise amplifier is required to be small, and the power gain is high; while the influence of internal noise of each level is different, the higher the number of stages, the greater the influence on the total noise figure. Therefore, the total noise figure depends mainly on the first few stages, which is the main reason why the receiver uses a high-gain low-noise amplifier.

2 is a circuit diagram of a first biasing unit in an embodiment. The first bias unit 110 includes a first transistor Q1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The base of the first transistor Q1 is respectively connected to the first resistor R1 and the second resistor R2, the other end of the first resistor R1 is grounded, and the other end of the second resistor R2 is connected to the positive voltage supply terminal V _OUT ; The collector of the transistor Q1 is connected to the negative voltage supply terminal V _NEG via the third resistor R3 and the fourth resistor R4; the emitter of the first transistor Q1 is connected to the positive voltage supply terminal V _OUT via the fifth resistor R5. The source of the transistor amplifier M1 is grounded; the gate of the transistor amplifier M1 is connected to a common point of the third resistor R3 and the fourth resistor R4; and the drain of the transistor amplifier M1 is connected to the emitter of the first transistor Q1.

Through the first transistor Q1 and the resistor in the first bias unit 110, the transistor amplifier M1 can be supplied with the required positive voltage bias voltage and negative voltage bias voltage, so that the transistor amplifier M1 operates at the drain voltage V _DS = 2V, I _DS = 10mA optimal operating conditions. At the same time, the first bias unit 110 also functions to stabilize the current, so that the transistor amplifier M1 obtains a stable DC state. When the current of the transistor amplifier M1 rises due to the influence of the temperature change, the emitter current of the first transistor Q1 becomes small, and thus the collector current of the first transistor Q1 also becomes small. Further, the voltage of the first transistor collector Q1 connected to the negative voltage supply terminal is also lowered, that is, the gate voltage of the transistor amplifier M1 is lowered, so that the source-drain current I _{DS of the} transistor amplifier M1 is lowered, thereby functioning as a negative feedback. So that the transistor amplifier M1 obtains a stable DC state.

3 is a circuit diagram of a first biasing unit in another embodiment. The first bias unit 110 further includes a second transistor Q2; the emitter of the second transistor Q2 is connected to the positive voltage supply terminal V _OUT via the second resistor R2, and the collector and the second transistor of the second transistor Q2 The base of the transistor Q2 is connected; the base of the second transistor Q2 is connected to the base of the first resistor R1 and the first transistor Q1, respectively. Simultaneously setting the second transistor Q2 also functions as a temperature compensation and stable operating point.

In an embodiment, the first bias unit 110 further includes a sixth resistor R6 and a seventh resistor R7. The seventh resistor R7 is connected in series between the emitter of the first transistor Q1 and the drain of the transistor amplifier M1, and the sixth resistor R6 is connected in series with the common point of the third resistor R3 and the fourth resistor R4 and the transistor amplifier M1. Between the gates. In this embodiment, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are all adjustable resistors, and can be used to adjust the current value of the output of the transistor amplifier.

In this embodiment, the first triode Q1 and the second triode are both PNP type triodes, and may be NPN type first triodes, and adopt PNP type first triodes. In other embodiments, the first triode Q1 and the second triode are all NPN type triodes according to actual needs, and may also be replaced by MOS tubes.

Since the source of the transistor amplifier M1 is grounded, the emitter of the first transistor Q1 is connected to the positive voltage supply terminal V _OUT via the fifth resistor R5, wherein the positive voltage supply terminal V _OUT is a positive voltage supply terminal of 5 volts. In this embodiment, the positive voltage output terminal of the second bias unit 120 supplies a voltage of 5 volts to the positive voltage supply terminal V _OUT . The voltage of 5 volts is divided by the first resistor R1 and the second resistor R2 of the ground, and is divided to the base of the first transistor Q1 to be the base bias of the first transistor Q1. At the same time, the drain of the transistor amplifier M1 is connected to the emitter of the first transistor Q1 via the seventh resistor R7 to obtain a positive voltage bias voltage, and the gate of the transistor amplifier M1 is passed through the sixth resistor R6, the fourth resistor R4 and the negative The voltage supply terminal V _{ENG is} connected. In the present embodiment, the negative voltage output terminal of the second bias unit 120 supplies a voltage of -2.5 volts to the negative voltage supply terminal V _ENG to obtain a negative voltage bias voltage. In other embodiments, the voltages of the positive voltage supply terminal and the negative voltage supply terminal in the first bias unit 110 can also be powered by a DC power source, and are not limited thereto.

The second bias unit 120 is a DC bias chip U1. Referring to FIG. 4, the DC bias chip U1 includes a plurality of sets of correspondingly disposed gate bias pins and drain bias pins and is provided for the first bias unit 110. Positive voltage output terminal V _OUT and negative voltage output terminal V _{ENG of the} voltage. Wherein, the drain bias pin D provides a positive voltage to the gate of the transistor amplifier, and the gate bias pin G provides a negative voltage to the drain of the transistor amplifier. In this embodiment, the DC bias chip U1 includes four sets of correspondingly disposed gate bias pins (G1, G2, G3, G4) and drain bias pins (D1, D2, D3, D4). There is a set of positive voltage output terminals V _OUT and negative voltage output terminals V _{ENG that} supply voltage to the first bias unit 110. Since the drain voltage of a transistor amplifier operating in the Ka band is 2V, the gate is generally negative. In the present embodiment, the drain bias pin D of the DC bias chip U1 outputs a positive voltage of 2 volts, and the gate bias pin G has a negative voltage of -0.6 volts.

As shown in FIG. 5, the drain current-drain voltage characteristic diagram of the transistor amplifier, since each transistor amplifier has a different characteristic curve, in the present embodiment, when the source of the transistor amplifier is grounded, the drain voltage is When the voltage is 2 volts and the drain current is 10 mA, the gate voltage of the transistor amplifier under this operating condition is -0.6 volts. In other embodiments, the specific value of the DC bias voltage can be set based on the actual operating conditions of the transistor amplifier.

In this embodiment, the down-conversion module for satellite signal reception is amplified by a three-stage transistor amplifier. Referring to FIG. 6, a three-stage cascaded first-stage transistor amplifier M1, a second-stage transistor amplifier M2, and a third-stage are included. Transistor amplifier M3. There is also a plurality of DC blocking capacitors (C1, C2), and the DC blocking capacitors are connected in series between adjacent two-stage transistor amplifiers. Each of the transistor amplifiers is cascaded by blocking capacitors (C1, C2), so that the DC bias of the transistor amplifiers of each stage does not affect each other.

In order to make the total noise figure of the receiver small, the noise figure of the first-stage transistor amplifier M1 and the second-stage transistor amplifier M2 has a large influence on the total noise figure of the receiver. Referring to FIG. 5, the first-stage transistor amplifier M1 is performed. The first biasing unit 110 is biased by the first biasing unit 110, and the first biasing unit 110' biases the second-stage transistor amplifier M2. The third biasing unit U1 is biased to the third stage transistor amplifier M3.

The positive voltage output terminal V _{OUT of the} second bias unit U1 is connected to the fifth resistor R5 of the first bias unit (110, 110'); the negative voltage output terminal V _{NEG of the} second bias unit U1 is Connected to a fourth resistor R4 in the first bias unit (110, 110'). The drain of the first stage transistor amplifier M1 is connected to the gate of the second stage transistor amplifier M2 via the first DC blocking capacitor C1. The gate bias pin G and the drain bias pin D of any one of the second bias units U1 are respectively connected to the gate and the drain of the third transistor amplifier M3. In this embodiment, the gate bias pin G3 in the second bias unit U1 is connected to the gate of the third-stage transistor amplifier M3, and the drain bias pin D3 is connected to the drain of the third-stage transistor amplifier M3. connection. The drain of the second stage transistor amplifier M2 is connected to the gate of the third stage transistor amplifier M3 via the second DC blocking capacitor C2. The drain of the third-stage transistor amplifier M3 outputs the amplified high-frequency signal to other devices (filters, etc.).

The first-stage transistor amplifier M1 and the second-stage transistor amplifier M2 all use the same active DC bias, and the transistor amplifier is DC-biased through the first transistor Q1 to ensure the first-stage transistor amplifier M1 and the second stage. The optimum DC operating state of the transistor amplifier M2 also has a certain temperature stability. The third-stage transistor amplifier M3 is biased by the DC bias chip U1, and the DC bias chip U1 directly outputs the gate and drain bias voltages required by the third-stage transistor amplifier M3, and can also be the first triode. Q1 provides positive voltage and negative voltage, which simplifies circuit design and reduces PCB area and cost while satisfying the performance of the first-stage transistor amplifier M1 and the second-stage transistor amplifier M2.

In one embodiment, the low noise amplifying circuit includes a PNP type universal dual transistor U2 that simultaneously biases the first stage transistor amplifier M1 and the second stage transistor amplifier M2; and biases the third stage transistor amplifier M3 It is the second bias unit U1.

The gates M2 of the first-stage transistor amplifier M1 and the second-stage transistor amplifier are respectively connected to the collectors of the PNP-type general-purpose dual-transistor U2; the drains of the first-stage transistor amplifier M1 and the second transistor amplifier M2 are respectively The emitter of the PNP type universal dual transistor U2 is connected; the source of the first stage transistor amplifier M1 and the second stage transistor amplifier M2 is grounded. The positive voltage output terminal of the second bias unit U1 is connected to the emitter of the PNP type universal double transistor U2; the negative voltage output terminal of the second bias unit U1 is connected to the collector of the PNP type universal double transistor U2. The gate bias pin G and the drain bias pin D in any one of the second bias units U1 are respectively connected to the gate and the drain of the third transistor amplifier M3. That is, the first bias unit 110 and the second-stage transistor amplifier M2 that bias the first-stage transistor amplifier M1 may be biased by two first transistors (Q1) in the first bias unit 110'. Q1') can be integrated to form a component. Referring to Figure 7, the integrated components can be replaced with a PNP-type universal dual transistor (NXP/PUMT1), simplifying the electronic components. Use, but also reduce the use of PCB board.

In one embodiment, referring to FIG. 8, each of the three stages of low noise amplifiers is biased by a first biasing unit 110, that is, three first biasing units (110, 110', 110") respectively bias the three-stage transistor amplifiers (M1, M2, M3). The first three transistors (Q1 of the three first biasing units (110, 110', 110") The emitters of Q1', Q1") are all loaded with a positive voltage, and the collectors of the first transistors (Q1, Q1', Q1" are loaded with a negative voltage. The three-stage transistor amplifiers (M1, M2, M3) are biased by three separate first transistors (Q1, Q1', Q1"), which can be supplied to the three-stage transistor amplifiers (M1, M2, M3). The best DC operating state, while also having a certain temperature stability, is that the total noise figure of the receiver is small and the power gain is high. Among the three first biasing units (110, 110', 110"), Any two adjacent first triodes can be replaced with a universal double first triode (NXP/PUMT1).

In one embodiment, referring to FIG. 9, the first stage transistor amplifier M1 is biased by the first bias unit 110; the second stage transistor amplifier M2 and the third stage transistor amplifier M3 are simultaneously biased. Second biasing unit U1.

The positive voltage output terminal V _OUT of the second bias unit U1 is connected to the fifth resistor R5 of the first bias unit 110; the negative voltage output terminal V _{NEG of the} second bias unit U1 and the first bias unit 110 The fourth resistor R4 is connected. The gate bias pin G2 and the drain bias pin D2 of the first group of the second bias unit U1 are respectively connected to the gate and the drain of the second-stage transistor amplifier M2; and the second bias unit U1 In the second group, the gate bias pin G3 and the drain bias pin D3 are respectively connected to the gate and the drain of the third-stage transistor amplifier M3. In another embodiment, the third biasing unit U1 can also be used to bias the three-stage cascaded transistor amplifiers (M1, M2, M3), and the second biasing unit U1 provides a gate bias voltage. The drain bias unit needs to meet the actual needs. By properly setting the first triode and the DC bias chip U1 to bias the three-stage transistor amplifier, the use of electronic components on the PCB can be reduced, the circuit design is simplified, and the area and cost of the PCB are reduced. .

The technical features of the above-described embodiments may be arbitrarily combined. For the sake of brevity of description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be considered as the scope of this manual.

The above-described embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims

A low noise amplifying circuit, comprising: a cascaded multi-stage low noise amplifier, a first bias unit or a second bias unit biasing each stage of the low noise amplifier, wherein

Deviating the front stage low noise amplifier of the plurality of stages of the low noise amplifier is the first bias unit, and the second stage of the low level noise amplifier is biased by the second stage a biasing unit, wherein the pre-stage low noise amplifier comprises at least a first stage low noise amplifier, the latter stage low noise amplifier comprising at least a last stage low noise amplifier, and the second bias unit is further used for The first biasing unit provides a bias voltage; or

All of the low noise amplifiers of each of the plurality of stages of the low noise amplifiers are biased by the first biasing unit.
The low noise amplifying circuit according to claim 1, wherein the first biasing unit comprises a first transistor, a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor;

The bases of the first transistors are respectively connected to the first resistor and the second resistor, the other end of the first resistor is grounded, and the other end of the second resistor is connected to the positive voltage power supply end; The collector of the first transistor is connected to the negative voltage supply terminal via the third resistor and the fourth resistor; the emitter of the first transistor is connected to the positive voltage supply terminal via the fifth resistor;

The low noise amplifier is a transistor amplifier, a source of the transistor amplifier is grounded; a gate of the transistor amplifier is connected to a common point of the third resistor and the fourth resistor; a drain of the transistor amplifier and the first The emitter of a triode is connected.
The low noise amplifying circuit according to claim 2, wherein said first biasing unit further comprises a second triode; said emitter of said second triode passing said said second resistor a positive voltage supply end is connected, a collector of the second triode is connected to a base of the second triode; a base of the second triode is respectively connected to the first resistor, the first three The base of the pole tube is connected.
The low noise amplifying circuit according to claim 2, wherein the second biasing unit is a DC bias chip;

The DC bias chip includes a plurality of sets of correspondingly disposed gate bias pins and drain bias pins; wherein the drain bias pins provide a positive voltage to a drain of the transistor amplifier, A gate bias pin provides a negative voltage to a gate of the transistor amplifier;

Also included is a positive voltage output and a negative voltage output that provide a voltage to the first biasing unit.
The low noise amplifying circuit according to claim 4, wherein said low noise amplifying circuit comprises a three-stage cascaded first stage transistor amplifier, a second stage transistor amplifier, and a third stage transistor amplifier.
The low noise amplifying circuit according to claim 5, wherein each of the first stage transistor amplifier and the second stage transistor amplifier is biased by the first bias unit; The stage transistor amplifier is biased to be a second bias unit;

The positive voltage output end of the second bias unit is respectively connected to the fifth resistor in the first bias unit; the negative voltage output end of the second bias unit is respectively connected to the first bias a fourth resistor connection in the unit;

The gate bias pin and the drain bias pin in any one of the second bias units are respectively connected to the gate and the drain of the third-stage transistor amplifier.
The low noise amplifying circuit according to claim 5, wherein said low noise amplifying circuit comprises a PNP type general-purpose two-transistor that simultaneously biases said first-stage transistor amplifier and said second-stage transistor amplifier; The third stage transistor amplifier is biased to be a second bias unit;

The gates of the first-stage transistor amplifier and the second-stage transistor amplifier are respectively connected to the collectors of the PNP-type universal two-transistor; the drains of the first-stage transistor amplifier and the second-stage transistor amplifier are respectively An emitter connection of a PNP type universal two-transistor; a source of the first-stage transistor amplifier and the second-stage transistor amplifier is grounded;

a positive voltage output terminal of the second bias unit is coupled to an emitter of the PNP type universal dual transistor; a negative voltage output terminal of the second bias unit is coupled to a collector of the PNP type universal dual transistor;

The gate bias pin and the drain bias pin in any one of the second bias units are respectively connected to the gate and the drain of the third transistor amplifier.
The low noise amplifying circuit according to claim 5, wherein said first biasing unit is biased for each of said three stages of said low noise amplifier;

The emitters of the first triodes in the first biasing unit are all loaded with a positive voltage, the first triode The collectors are all loaded with a negative voltage.
The low noise amplifying circuit according to claim 5, wherein said first stage transistor amplifier is biased by said first bias unit; said second stage transistor amplifier, said third stage transistor The amplifier is simultaneously biased to be a second bias unit;

a positive voltage output end of the second bias unit is connected to a fifth resistor of the first bias unit; a negative voltage output end of the second bias unit and a first one of the first bias unit Four-resistance connection;

a first group of the gate bias pin and the drain bias pin of the second bias unit are respectively connected to a gate and a drain of the second-stage transistor amplifier; The second group of the gate bias pins and the drain bias pins of the bias unit are respectively connected to the gates and drains of the third-stage transistor amplifier.
The low noise amplifying circuit according to claim 1, further comprising a plurality of DC blocking capacitors connected in series between the adjacent two stages of the low noise amplifiers.