JP2009005092A - Variable-gain low noise amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To set an appropriate amplification gain according to the strength of a high-frequency input signal level. <P>SOLUTION: When the high-frequency input signal level falls within a weak electric field, an amplifier bypassing FET 4 is placed in an OFF state, first and second signal amplifying FETs 1 and 2 and an FET 3 for gain switching SW are placed in an ON state, and the first and second signal amplifying FETs 1 and 2 perform amplification at a maximum gain. When the high-frequency input signal level falls within an intermediate electric field, the amplifier bypassing FET 4 and the FET 3 for gain switching SW are placed in the OFF state, and the first and second signal amplifying FETs 1 and 2 are placed in the ON state and perform amplification at a prescribed gain not more than the maximum gain as their operating current flows through a gain adjusting inductor 9 and a bias adjusting resistor 10. When the high-frequency input signal level falls within a strong electric field, the amplifier bypassing FET 4 is placed in the ON state and thus input high-frequency signals are output without being amplified. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a variable gain amplifier used in various wireless communication devices such as mobile communication devices, and more particularly to a device that improves a variable amount of freedom in variable gain.

In a low noise amplifier used for wireless communication such as a mobile communication device, a high-frequency signal power to be input is usually weak, but a high-frequency signal with a strong electric field may be input under certain conditions. In such a case, in a low noise amplifier that does not have a gain variable function, when a high frequency signal of a strong electric field is input, the linear operation region of the low noise amplifier is exceeded, causing a problem that the high frequency input signal is distorted. . For this reason, a gain variable function is added to the low noise amplifier, and when the high frequency input signal is weak, the amplification gain is maximized. Conversely, when the high frequency input signal is a strong electric field, the amplification gain is set to the minimum. Thus, it is necessary to reduce signal distortion in the low noise amplifier.
And by changing the gain of the low noise amplifier and minimizing the amplification gain, the signal level input to the subsequent stage of the low noise amplifier is lowered, so that distortion of the input signal in the subsequent stage of the low noise amplifier can be suppressed. There are advantages.

As an example of such a conventional variable gain amplification, there is one disclosed in Patent Document 1, for example.
FIG. 3 shows an example of a conventional circuit. Hereinafter, a conventional variable gain amplification will be described with reference to FIG.
In this variable gain amplifier, an amplifier circuit is configured around a signal amplification field effect transistor (hereinafter referred to as “FET”) 28 for amplifying a high frequency signal, and an amplifier bypass FET 4A for bypassing the high frequency signal. Is provided so as to be connected in parallel to the signal amplification FET 28.
Further, the signal amplification FET 28 is provided with a bias SW FET 29 for controlling the operation thereof connected in series.

  In such a configuration, if the control voltage applied to the second control voltage application terminal 37 is VCONT 37 and the pinch-off voltage of the amplifier bypass FET 4A is Vp, the gain is not varied, in other words, the maximum gain is obtained. First, a power supply voltage for operating the signal amplification FET 28 is applied to the power supply voltage application terminal 27A, while a bias voltage for turning on the bias SW FET 29 is applied to the first control voltage application terminal 36. In addition, a bias voltage that satisfies VCONT 37 ≧ −Vp is applied to the second control voltage application terminal 37.

As a result, the signal amplifying FET 28 is activated, while the amplifier bypassing FET 4A is turned on.
The high frequency signal input from the high frequency signal input terminal 21A via the input impedance matching circuit 18A without being variable in gain is not attenuated by the amplifier bypass FET 4A, and passes through the first DC cut capacitor 5A. Through the first gate terminal G1 of the signal amplification FET 28. The high-frequency signal amplified by the signal amplification FET 28 is output to the high-frequency signal output terminal 22A through the output impedance matching circuit 19A and the fourth DC cut capacitor 20A, which is the same as a normal low noise amplifier. The maximum gain can be obtained by simple operation.

On the other hand, when performing variable gain, in other words, when obtaining a minimum gain, a bias voltage is applied to the first control voltage application terminal 36 so that the bias SW FET 29 is turned off, while the second control voltage application terminal 36 is turned on. By applying a bias voltage such that VCONT 37 ≦ −Vp to the control voltage application terminal 37, the signal amplification FET 28 is turned off, while the amplifier bypass FET 4A is turned on.
As a result, the high frequency input signal does not pass through the signal amplification FET 28 but passes through the amplifier bypass FET 4A and is output to the high frequency signal output terminal 22A. Therefore, the gain when the gain is variable is determined by the passage loss in the bypass circuit constituted by the second DC cut capacitor 7A, the amplifier bypass FET 4A, and the third DC cut capacitor 8A.
JP 2004-274108 A (page 5-8, FIGS. 1 to 2)

However, in the above-described conventional circuit, the gain at the time of variable gain can be selected only in two stages as described above. Therefore, when the high-frequency input signal is an intermediate level (medium electric field) between a strong electric field and a weak electric field Therefore, there arises a problem that an appropriate gain according to the input signal level cannot be selected.
FIG. 4 is a characteristic diagram showing a gain change with respect to the high-frequency input signal level in the above-described conventional circuit. Hereinafter, the above problem will be described in more detail with reference to FIG.

First, in FIG. 4, the horizontal axis represents the level (dBm) of the high-frequency input signal, and the vertical axis represents the amplification gain (dB).
In FIG. 4, for convenience, a region where the high frequency input signal level is −40 dBm to −20 dBm is a weak electric field, a region where the high frequency input signal level is −25 dBm to −15 dBm is a medium electric field, and the high frequency input signal level is − A region from 15 dBm to −0 dBm is defined as a strong electric field.
Furthermore, a gain dynamic range Rdyn is defined as a difference between a gain when the gain is not changed (when the maximum gain is obtained) and a gain when the gain is varied (when the minimum gain is obtained).

Under such a premise, in FIG. 4, when the high-frequency input signal level input to the variable gain low noise amplifier is a weak electric field (a region from −40 dBm to −20 dBm), the sensitivity of the radio receiver is obtained. Therefore, the maximum gain (17.2 dB) can be obtained without changing the gain of the variable gain low noise amplifier (see FIG. 4).
On the other hand, when the high-frequency input signal level input to the variable gain low noise amplifier is a strong electric field (a region from −15 dBm to −0 dBm), by changing the gain to reduce distortion, the minimum gain is obtained. (-7.2 dB) can be obtained (see FIG. 4).
Therefore, the gain dynamic range Rdyn in this case is 24.7 dB.

As described above, in the conventional circuit, when the high-frequency input signal level is a medium electric field, the optimum gain cannot be selected. Therefore, the gain is frequently switched in the large gain dynamic range Rdyn (24.7 dB). However, there was nothing else to deal with the middle electric field region.
In general, when the variable gain state is switched in a state where the gain dynamic range is large, for example, in a device used for data communication, there is a problem that throughput is deteriorated. As the gain dynamic range is smaller, problems such as a decrease in throughput during data communication in the middle electric field region do not occur. However, in the conventional circuit as described above, not only a decrease in throughput during data communication, but also a communication inhibition at a high data rate. Cannot be avoided.

  In recent mobile communication devices, communication is often performed at a high data rate, and a high-frequency input signal level input to a wireless receiver due to addition of a wireless relay base station or the like is often in a middle electric field region. Therefore, as described above, the gain selectivity of the variable gain low noise amplifier when the high frequency input signal is a medium electric field is an important problem.

The present invention has been made in view of the above circumstances, and provides a variable gain low noise amplifier capable of setting a more appropriate amplification gain as compared with the prior art in accordance with the strength of the high frequency input signal level. is there.
Another object of the present invention is to provide a variable gain low noise amplifier that enables gain setting corresponding to each of a strong electric field, a medium electric field, and a weak electric field of a high frequency input signal level.

In order to achieve the above object of the present invention, a variable gain low noise amplifier according to the present invention comprises:
The first and second signal amplification field effect transistors are configured to amplify a high frequency signal, and the first and second signal amplification field effect transistors are bypassed between the input and output terminals. A variable gain low noise amplifier provided with a field effect transistor for amplifier bypass,
In the two signal amplification field effect transistors, the drain of the first signal amplification field effect transistor is connected to the source of the second signal amplification field effect transistor, and the first signal amplification field effect transistor Is provided so that a high frequency input signal can be applied to the gate thereof, and an amplified signal is provided on the drain side of the second signal amplification field effect transistor,
Operating current adjusting means for adjusting the operating current of the first signal amplifying field effect transistor is provided between the source of the first signal amplifying field effect transistor and the ground.
In this configuration, the operating current adjusting means includes the gain switching SW field effect transistor provided in series between the source of the first signal amplification field effect transistor and the ground, and the gain switching SW field effect. It is preferable to include a series circuit that is connected in parallel to the transistor and includes at least a gain adjusting inductor.
More specifically, a high-frequency input signal can be applied to the gate of the first signal amplification field effect transistor via the input impedance matching circuit and the first DC cut capacitor, The connection point of the first DC cut capacitor is connected to the source of the amplifier bypass field effect transistor via the second DC cut capacitor, and the drain of the second signal amplification field effect transistor is connected to the output The amplified signal can be output to the outside via the impedance matching circuit and the fourth DC cut capacitor, and the drain of the second signal amplification field effect transistor is connected to the drain via the third DC cut capacitor. The first signal amplification electric field connected to the drain of the amplifier bypass field effect transistor The gate of the effect transistor is connected to the first gate bias applying bias circuit, and the gate of the second signal amplifying field effect transistor is connected to the gate of the second transistor bias applying circuit. Both of the bias application voltages can be applied, and the gate of the second signal amplifying field effect transistor is connected to the ground via the first bypass capacitor, and the first signal amplifying field effect transistor has a gate connected thereto. The source is preferably connected to the drain of the gain switching SW field effect transistor, while the source of the gain switching SW field effect transistor is connected to the ground.
Furthermore, a plurality of amplifier bypass field effect transistors may be preferably provided in series.

  According to the present invention, the amplification gain can be varied more appropriately than in the past in accordance with the high-frequency input signal level, thereby degrading the reception performance such as the throughput during data communication in the wireless communication device. In this way, an amplified signal corresponding to the variable gain can be output.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 and 2.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a configuration example of a variable gain low noise amplifier according to an embodiment of the present invention will be described with reference to FIG.
The variable gain low noise amplifier according to the embodiment of the present invention receives a high frequency signal by an amplifier circuit composed of a first signal amplification field effect transistor (hereinafter referred to as “FET”) 1 and a second signal amplification FET 2. In addition to being amplified, the gain switching SW FET 3 can be configured to select whether or not the gain can be varied.
Further, the variable gain low noise amplifier according to the embodiment of the present invention is provided with a bypass circuit centered on the amplifier bypass FET 4.

Hereinafter, the circuit connection will be specifically described.
The gate of the first signal amplification FET 1 is connected to the high frequency signal input terminal 21 via the first DC cut capacitor 5 and the input impedance matching circuit 18. The source of the amplifier bypass FET 4 is connected to the connection point between the first DC cut capacitor 5 and the input impedance matching circuit 18 via the second DC cut capacitor 7.

Further, the drain of the first signal amplification FET 1 and the source of the second signal amplification FET 2 are connected to each other, and the first and second signal amplification FETs 1 and 2 are provided in a cascade connection state. .
The drain of the second signal amplification FET 2 is connected to the high-frequency signal output terminal 22 via the output impedance matching circuit 19 and the fourth DC cut capacitor 20, and via the third DC cut capacitor 8. Are connected to the drain of the amplifier bypass FET 4 and further connected to the power supply voltage application terminal 27 via the choke inductor 17.

  The amplifier bypass FET 4 has a gate connected to the second bias application terminal 24 via the first bias resistor 14, while a source connected to the second bias resistor 13 and a drain. Are both connected to a third bias application terminal 25 via a third bias resistor 15.

  The gate of the first signal amplifying FET 1 is passed through the first gate bias applying bias circuit 11, and the gate of the second signal amplifying FET 2 is the second gate bias applying bias circuit 12. And the gate of the second signal amplification FET 2 is connected to the ground via the bypass capacitor 6.

Further, the source of the first signal amplifying FET 1 is connected to the drain of the gain switching SW FET 3 and is also connected to the ground via the gain adjusting inductor 9 and the bias adjusting resistor 10.
The source of the gain switching SW FET 3 is connected to the ground, and the gate is connected to the first bias application terminal 23 via the fourth bias resistor 16.
In the embodiment of the present invention, the operating current of the first signal amplification field effect transistor is adjusted by the gain switching SW FET 3 and the series circuit including the gain adjusting inductor 9 and the bias adjusting resistor 10 ( The operating current adjusting means 51 is configured (details will be described later).

  In such a configuration, the pinch-off voltage of the gain switching SW FET 3 is Vp3, the pinch-off voltage of the amplifier bypass FET 4 is Vp4, the voltage applied to the first bias application terminal 23 is V23, and the second bias application terminal 24 is applied. The applied voltage is defined as V24, and the voltage applied to the third bias application terminal 25 is defined as V25.

  The variable gain low noise amplifier according to the embodiment of the present invention can set the amplification gain to three levels according to the level of the input high frequency input signal. However, the circuit operation will be described in three cases: a weak electric field, a medium electric field, and a strong electric field.

First, when the high frequency input signal is a weak electric field, the gain of the variable gain low noise amplifier is set to the maximum gain (variable gain is not performed). In this case, a power supply voltage sufficient to operate the first and second signal amplification FETs 1 and 2 is applied to the power supply voltage application terminal 27.
On the other hand, a bias voltage is applied to the fourth bias application terminal 26 so that the operating current flowing through the first and second signal amplification FETs 1 and 2 has a desired value, and to the first bias application terminal 23. Applies a bias voltage such that V23> Vp3. Further, a bias voltage that satisfies V24 <Vp4 is applied to the second bias application terminal 24, and a bias voltage that satisfies V25> Vp4 is applied to the third bias application terminal 25, respectively.

As a result, the first and second signal amplification FETs 1 and 2 are in an operating state, while the amplifier bypass FET 4 is in an off state, and the gain switching SW FET 3 is in an on state.
When the gain is not varied, the gain switching SW FET 3 is in the ON state in this way, and therefore the operating currents of the first and second signal amplification FETs 1 and 2 are the drains of the gain switching SW FET 3.・ It will flow between sources.
The gate width of the amplifier bypass FET 4 and the capacitance values of the second and third DC cut capacitors 7 and 8 are the high-frequency input signal and high-frequency output in these elements in a state where the gain is not varied. Since the signal is optimized so as to suppress the attenuation of the signal, the high-frequency signal input from the high-frequency input terminal 21 via the input impedance matching circuit 18 is not attenuated by the amplifier bypass FET 4, and the first DC The signal is input to the gate of the first signal amplifying FET 1 through the cutting capacitor 5.

  The high-frequency signal amplified by the first and second signal amplification FETs 1 and 2 is output from the drain of the second signal amplification FET 2 and is not attenuated by the amplifier bypass FET 4, so that the output impedance matching circuit 19 and the fourth DC cut capacitor 20 to be output to the high frequency signal output terminal 22. That is, in this case, the maximum gain is obtained by operating in the same manner as a normal low noise amplifier.

Next, the case where the high-frequency input signal level input to the variable gain low noise amplifier is a medium electric field will be described. In this case, the gain is set to an intermediate gain as described below. This variable gain state is defined as “variable gain state 1”.
Therefore, in the variable gain state 1, a bias voltage is applied to the fourth bias application terminal 26 so that the operating current flowing through the first and second signal amplification FETs 1 and 2 has a desired value. At the same time, the first bias application terminal 23 has a bias voltage such that V23 <Vp3, the second bias application terminal 24 has a bias voltage such that V24 <Vp4, Bias voltages that satisfy V25> Vp4 are applied to the bias application terminals 25, respectively.
As a result, the first and second signal amplification FETs 1 and 2 are in an operating state, while the amplifier bypass FET 4 and the gain switching SW FET 3 are both turned off.

In the case of the variable gain state 1, unlike the case of the weak electric field, the gain switching SW FET 3 is in the OFF state, so that the operating currents of the first and second signal amplification FETs 1 and 2 are It does not flow between the drain and source of the switching SW FET 3 but flows through a series circuit including the gain adjusting inductor 9 and the bias adjusting resistor 10 connected in parallel with the gain switching SW FET 3.
In this case, the gain adjusting inductor 9 is connected to the source of the first signal amplifying FET 1 instead of the gain switching SW FET 3. That is, in other words, a negative feedback circuit (series feedback circuit) composed of the gain adjusting inductor 9 and the bias adjusting resistor 10 is connected to the source of the first signal amplifying FET 1.

  By connecting the series feedback circuit to the source of the first signal amplifying FET 1 in this way, the gain of the first signal amplifying FET 1 is reduced as compared with the state where the gain variable described above is not performed. Therefore, the variable gain state 1 can be realized.

In the series circuit portion including the gain adjusting inductor 9 and the bias adjusting resistor 10, the dominant element with respect to the gain of the first signal amplifying FET 1 is the gain adjusting inductor 9, so that the inductance is changed. As a result, the magnitude of the gain in the variable gain state 1 can be set to a desired value.
In the variable gain state 1, the operating current flowing through the first and second signal amplification FETs 1 and 2 flows through a series circuit including the gain adjustment inductor 9 and the bias adjustment resistor 10 as described above. Therefore, the source potential of the first signal amplifying FET 1 rises above the ground potential by the voltage drop in the bias adjusting resistor 10. As a result, the potential difference between the gate and the source of the first signal amplifying FET 1 is reduced, and as a result, the operating current flowing through the first and second signal amplifying FETs 1 and 2 is reduced.

  In the case of variable gain state 1, not only the gain is varied, but also the operating current flowing through the first and second signal amplification FETs 1 and 2 is simultaneously varied (reduced), the bias adjusting resistor 10 is varied. The resistor may be configured to be adjusted to a desired operating current value by changing its resistance value. In the case of the variable gain state 1, when it is not necessary to vary the operating current flowing through the first and second signal amplification FETs 1 and 2, the first signal is not provided without providing the bias adjusting resistor 10. Only the gain adjusting inductor 9 may be provided between the source of the amplifying FET 1 and the ground.

Next, the case where the high-frequency input signal level input to the variable gain low noise amplifier is a strong electric field will be described. In this case, the gain is set to the minimum gain as described below. It is defined as “gain variable state 2”.
In the variable gain state 2, a bias voltage is applied to the fourth bias application terminal 26 so that the first and second signal amplification FETs 1 and 2 are turned off, and to the second bias application terminal 24. , V24> Vp4, and the third bias application terminal 25 is applied with a bias voltage such that V25 <Vp4.

As a result, the first and second signal amplification FETs 1 and 2 are turned off, while the amplifier bypass FET 4 is turned on.
On the other hand, in the variable gain state 2, the operation state of the gain switching SW FET 3 need not be fixed to either the on state or the off state, and is arbitrary. Therefore, the bias voltage applied to the first bias application terminal 23 is arbitrary.
In this state, since the first and second signal amplification FETs 1 and 2 are in the off state, the high frequency input signal input to the variable gain low noise amplifier is the first and second signal amplification FETs 1. , 2, instead of passing through the bypass path constituted by the second DC cut capacitor 7, the amplifier bypass FET 4 and the third DC cut capacitor 8.

The gain in the variable gain state 2 is determined by the passage loss of the bypass path constituted by the second DC cut capacitor 7, the amplifier bypass FET 4 and the third DC cut capacitor 8. Therefore, the gain in the variable gain state 2 can be arbitrarily set to a desired value by optimizing the gate width of the amplifier bypass FET 4 and the capacitance values of the second and third DC cut capacitors 7 and 8. It has become a thing.
The variable gain state 2 is an operation state equivalent to that when the gain is variable in the conventional circuit (see FIG. 3).

In the conventional circuit, no matter what level the electric field of the input high-frequency input signal is, the gain state that can be selected is only a two-stage gain state for a weak electric field or a strong electric field. Is input, it is not possible to select an optimal gain that does not impair the reception performance of the wireless receiver. For example, during data communication, it may cause a decrease in throughput or a decrease in data rate. There was an inconvenience.
On the other hand, in the variable gain low noise amplifier according to the embodiment of the present invention, the gain can be switched in three stages as described above, so that the input high frequency input signal level is a weak electric field. When the high frequency input signal level is a strong electric field without changing the gain, the variable gain state 2 is selected. When the high frequency input signal level is the medium electric field, the variable gain state 1 is selected. Since the optimum gain can be selected according to the situation as selected, unlike the conventional circuit, it is possible to surely prevent the reception performance from being lowered during data communication of the wireless receiver.

  In the conventional circuit as well, the gain when the gain is variable is determined by the passage loss of the bypass path. Therefore, the gain is always a negative value, but the variable gain low noise amplifier according to the embodiment of the present invention. In the variable gain state 1 in FIG. 1, as described above, a desired gain can be arbitrarily set by changing the inductance of the gain adjusting inductor 9 provided on the source side of the first signal amplifying FET 1. Therefore, unlike the conventional circuit, not only a negative numerical gain but also a positive numerical gain can be arbitrarily set.

FIG. 2 is a characteristic diagram showing a gain change with respect to the high-frequency input signal level of the variable gain low noise amplifier according to the embodiment of the present invention. Hereinafter, similar characteristics in the conventional circuit shown in FIG. The gain characteristics with respect to the high-frequency input signal level of the variable gain low noise amplifier in the embodiment of the present invention will be described with reference to the characteristics.
2 and 4, the horizontal axis represents the level (dBm) of the high-frequency input signal, and the vertical axis represents the amplification gain (dB).
In the case of the conventional circuit, when the high-frequency input signal level is in the middle electric field region, the optimum gain cannot be selected, and the gain dynamic range Rdyn when the gain is switched is 24.7 dB (FIG. 4). reference).

In contrast, in the variable gain low noise amplifier according to the embodiment of the present invention, an optimum gain can be selected even when the high frequency input signal level is in the middle electric field region, and the gain is not varied. The gain dynamic range Rdyn when the gain is switched from the state to the variable gain state 1 is 12.2 dB (see FIG. 2), which is an improvement of 12.5 dB compared with the conventional circuit, and is clearly improved The effect can be confirmed. This can be said to be the effect of realizing a three-stage variable gain state as compared with the conventional circuit.
In the configuration example described above, the amplifier bypass FET 4 has a single-stage configuration. However, a configuration in which a plurality of stages are serially connected in series may be used as desired. By connecting a plurality of amplifier bypass FETs 4 in series, the capacity of the bypass path can be reduced and the characteristics can be improved when the gain is not varied.

It is a circuit diagram which shows the structural example of the variable gain low noise amplifier in embodiment of this invention. FIG. 2 is a characteristic diagram showing a gain change with respect to a high frequency input signal level in the variable gain low noise amplifier shown in FIG. 1. It is a circuit diagram which shows one structural example of a conventional circuit. FIG. 4 is a characteristic diagram showing a gain change with respect to a high frequency input signal level in the conventional variable gain low noise amplifier shown in FIG. 3.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... 1st signal amplification field effect transistor 2 ... 2nd signal amplification field effect transistor 3 ... Gain switching SW field effect transistor 4 ... Amplifier bypass field effect transistor 9 ... Gain adjustment inductor 10 ... Bias adjustment Resistor

Claims (4)

The first and second signal amplification field effect transistors are configured to amplify a high frequency signal, and the first and second signal amplification field effect transistors are bypassed between the input and output terminals. A variable gain low noise amplifier provided with a field effect transistor for amplifier bypass,
In the two signal amplification field effect transistors, the drain of the first signal amplification field effect transistor is connected to the source of the second signal amplification field effect transistor, and the first signal amplification field effect transistor Is provided so that a high frequency input signal can be applied to the gate thereof, and an amplified signal is provided on the drain side of the second signal amplification field effect transistor,
An operating current adjusting means for adjusting an operating current of the first signal amplifying field effect transistor is provided between the source of the first signal amplifying field effect transistor and the ground. Variable type low noise amplifier.   The operating current adjusting means includes a gain switching SW field effect transistor connected in series between a source of the first signal amplification field effect transistor and a ground, and the gain switching SW field effect transistor. 4. The variable gain low noise amplifier according to claim 3, further comprising a series circuit connected in parallel to each other and using at least a gain adjusting inductor.   The gate of the first signal amplifying field effect transistor allows a high frequency input signal to be applied through an input impedance matching circuit and a first DC cut capacitor, and the input impedance matching circuit and the first DC cut capacitor The connection point with the capacitor is connected to the source of the amplifier bypass field effect transistor via the second DC cut capacitor, and the drain of the second signal amplification field effect transistor is connected to the output impedance matching circuit and the second The amplified signal can be output to the outside via the DC cut capacitor 4 and the drain of the second signal amplification field effect transistor is connected to the field effect for the amplifier bypass via the third DC cut capacitor. A first field-effect transistor for signal amplification connected to a drain of the transistor; The first gate bias applying bias circuit is connected to the gate of the second signal amplifying field effector, and the second signal biasing field effect transistor is connected to the gate of the second signal amplifying field effect transistor via the second gate bias applying bias circuit. A bias voltage can be applied, and the gate of the second signal amplification field effect transistor is connected to the ground via a first bypass capacitor, and the source of the first signal amplification field effect transistor is 3. The variable gain low type circuit according to claim 2, wherein a drain of the gain switching SW field effect transistor is connected to a source, and a source of the gain switching SW field effect transistor is connected to a ground. Noise amplifier.   4. The variable gain low noise amplifier according to claim 3, wherein a plurality of the amplifier bypass field effect transistors are connected in series.

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