CN116314197A - 氧化物半导体三维集成的cascode增强型GaN功率器件及制作方法 - Google Patents
氧化物半导体三维集成的cascode增强型GaN功率器件及制作方法 Download PDFInfo
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Abstract
本发明提出氧化物半导体三维集成的cascode增强型GaN功率器件,包括GaN MIS‑HEMT和氧化物半导体FET两者进行金属互联形成的cascode级联结构;所述GaN MIS‑HEMT由硅基衬底上外延的GaN/AlGaN叠层、高k介质、源/漏/栅电极、钝化层以及场板结构组成;所述增强型氧化物半导体FET在钝化层上方制备;cascode级联结构中,氧化物半导体FET漏极和GaN MIS‑HEMT源极以第一金属层(17)互连,氧化物半导体FET源极和GaN MIS‑HEMT栅极以第二金属层(19)互连;第一金属层、第二金属层之间以以钝化层作为绝缘层;所述增强型GaN功率器件的阈值电压由氧化物半导体FET决定;本发明在实现增强型GaN MIS‑HEMT的同时,有效降低芯片面积及寄生参数,更有利于GaN功率器件的高频、集成化应用。
Description
技术领域
本发明涉及半导体技术领域,尤其是氧化物半导体三维集成的cascode增强型GaN功率器件及制作方法。
背景技术
从20世纪60年代开始,硅基CMOS工艺一直主导着半导体产业。近年来随着电力电子技术的不断发展,市场对大功率器件的需求不断扩大,同时对它的要求也越来越高。而由于硅材料本身物理特性的限制,性能提升的空间已经日益狭小,且同时带来了成本升高的弊端。以氮化镓(GaN)为代表的第三代宽禁带半导体因具有高临界击穿场强、高电子迁移率以及高热导系数等优势而在高频、高功率、高温、小型轻量化领域展现出巨大的潜力。
由于自发极化和压电极化会在GaN HEMT器件产生高浓度的二维电子气,沟道2DEG的存在使得器件处于导通状态。因此,常规GaN HEMT工作模式属于耗尽型,其驱动电压与常规驱动芯片的电平不兼容,造成驱动电路变复杂。除此之外,零偏压下器件会导通,也造成在电力电子应用中存在安全隐患。因此,产业界需要增强型的GaN功率器件。
传统cascode级联结构是共源共栅结构是将耗尽型GaN晶体管的源极和栅极分别与增强型Si晶体管的漏极和源极相连,由增强型Si MOSFET控制开关状态,可以实现较高的的阈值电压以及输出功率。当Si MOSFET栅极没有电压时,在GaN HEMT栅极和源极之间会产生负电压,使得GaN器件呈关闭状态。但是由于两个器件之间串联电阻较大,其性能主要受限于Si材料,GaN宽禁带半导体材料的性能优势未能得到很好得到体现。
发明内容
本发明提出氧化物半导体三维集成的cascode增强型GaN功率器件及制作方法,在实现增强型GaN MIS-HEMT的同时,有效降低芯片面积及寄生参数,更有利于GaN功率器件的高频、集成化应用。
本发明采用以下技术方案。
氧化物半导体三维集成的cascode增强型GaN功率器件,所述GaN功率器件包括GaNMIS-HEMT和氧化物半导体FET两者进行金属互联形成的cascode级联结构,为增强型功率器件,所述GaNMIS-HEMT由硅基衬底上外延的GaN/AlGaN叠层、高k介质、源/漏/栅电极、钝化层以及场板结构组成;所述增强型氧化物半导体FET在钝化层上方制备,自下而上分别为底栅电极、高k栅介质、氧化物半导体沟道、源/漏电极以及钝化层;
cascode级联结构中,氧化物半导体FET漏极和GaN MIS-HEMT源极以第一金属层(17)互连,氧化物半导体FET源极和GaNMIS-HEMT栅极以第二金属层(19)互连;第一金属层、第二金属层之间以以钝化层作为绝缘层;
所述增强型GaN功率器件的阈值电压由氧化物半导体FET决定,通过调节氧化物半导体的氧空位浓度及栅极金属功函数来实现增强性能,且阈值电压可调。
所述氧化物半导体FET元件与耗尽型GaN HEMT均设于GaN衬底的AlGaN势垒层(1)上;AlGaN势垒层下顺序设置GaN沟道层(2)、GaN缓冲层(3)、Si衬底(4)。
氧化物半导体三维集成的cascode增强型GaN功率器件的制作方法,用于制备以上所述的氧化物半导体三维集成的cascode增强型GaN功率器件,包括以下步骤;
步骤S1:将GaN衬底依次放在丙酮、异丙醇溶液中进行清洗,最后用氮气枪吹干;
步骤S2:在衬底上通过离子注入进行器件有源区隔离,隔绝器件与器件之间的电学干扰;
步骤S3:光刻定义出GaN MIS-HEMT的源极和漏极区域,在衬底上采用电子束蒸发连续沉积金属层作为GaN MIS-HEMT的源极(5)和GaN MIS-HEMT的漏极(6),剥离掉源漏电极之外区域的金属,之后退火形成合金欧姆接触;
步骤S4:在用原子层沉积工艺沉积高k介质层(7),即高k栅介质层;
步骤S5:在高k介质层上旋涂光刻胶并用电子束曝光将栅极图案化,采用物理气相沉积蒸镀金属层作为GaN MIS-HEMT的栅极(8),并剥离多余的金属;
步骤S6:采用增强型等离子化学气相沉积钝化层(9);
步骤S7:光刻定义出GaN MIS-HEMT的源极区域,对GaN MIS-HEMT源极区域的电极区域进行刻蚀开窗;采用光学光刻定义出源场板图形并沉积金属作为GaN MIS-HEMT的场板电极(10)与源电极相连;
步骤S8:旋涂光刻胶并用电子束曝光将氧化物半导体FET栅极图案化,使用PVD物理气相沉积在氧化物半导体FET有源区蒸镀作为氧化物半导体FET底部栅极(11);
步骤S9:用原子层沉积工艺沉积高k介质层作为氧化物半导体FET的栅极(12)的介质;
步骤S10:采用原子层沉积或磁控溅射制备氧化物半导体沟道材料,即氧化物半导体FET的栅极上的氧化物半导体薄膜(13);
步骤S11:在氧化物半导体薄膜上旋涂光刻胶后,以电子束曝光出氧化物半导体FET源极和漏极区域,利用PVD技术分别在氧化物半导体FET的源区和漏区蒸镀金属层作为氧化物半导体FET的源极(14)和漏极(15);
步骤S12:采用增强型等离子化学气相沉积在样品上淀积第一钝化层(16);
步骤S13:旋涂光刻胶后电子束曝光出氧化物半导体FET漏极区域以及GaN MIS-HEMT源极区域,开窗刻蚀形成接触通孔,完成氧化物半导体FET漏极和GaNMIS-HEMT源极的电极金属互联;
步骤S14:采用增强型等离子化学气相沉积在样品上淀积第二钝化层(18);
步骤S15:旋涂光刻胶后电子束曝光出氧化物半导体FET源极区域以及GaN MIS-HEMT栅极区域,开窗刻蚀形成接触通孔,完成氧化物半导体FET源极和GaNMIS-HEMT栅极的电极金属互联。
所述的GaN衬底结构包括625 mm的Si衬底,3.9mm GaN缓冲层,300 nm的无掺杂的本征GaN沟道层以及20 nm铝元素组份为25%的无掺杂的本征AlGaN势垒层。
所述高k介质层包括Al2O3、HfO2、ZrO2、La2O3、HfAlOx、HfSiOx、HfLaOx、HfZrOx、HfSiON的一种或多种
步骤S5所述的金属层为20/50 nm镍/金。
所述钝化层材料为SiN、SiO2、Al2O3中的一种或多种。
步骤S7、S8、S11、S13、S15所述的金属层为2镍/金。
步骤S10所述氧化物半导体沟道材料包括氧化锌ZnO、氧化铟In2O3、氧化锡SnO2、氧化镓Ga2O3、氧化铟镓锌IGZO、氧化铟锡ITO、氧化铟锌IZO的一种或多种。
增强型GaN功率器件以衬底上的片上三维堆叠结构来降低芯片面积及寄生参数。
本发明在实现增强型GaN MIS-HEMT的同时,有效降低芯片面积及寄生参数,提供一种与氧化物半导体三维集成的cascode增强型GaN功率器件及其制作方法,更有利于GaN功率器件的高频、集成化应用。
本发明提出的氧化物半导体FET级联的cascode增强型GaN功率器件,其阈值电压由氧化物半导体FET决定,可通过调节氧化物半导体的氧空位浓度及栅极金属功函数来实现增强型,且阈值电压可调。
本发明利用了氧化物半导体具有宽禁带、可低温沉积的优势;相比于传统的封装级联cascade增强型GaN器件,本发明提出的氧化物半导体FET级联的cascode增强型GaN功率器件通过片上三维堆叠,可以有效降低芯片面积及寄生参数,更有利于GaN功率器件的高频、集成化应用。可以充分发挥宽禁带半导体材料的优势,是新一代半导体器件的有力竞争者。
与现有技术相比,本发明具有以下优势:
(1) 所述cascode增强型GaN功率器件的阈值电压由氧化物半导体FET决定,可通过调节氧化物半导体的氧空位浓度及栅极金属功函数来实现增强型,且阈值电压可调;
(2) 所述氧化物半导体具有宽禁带、可低温沉积优势,相比于传统的封装级联cascade增强型GaN器件,本发明提出与氧化物半导体FET级联的cascode增强型GaN功率器件可实现片上三维堆叠,可有效降低芯片面积及寄生参数,更有利于GaN功率器件的高频、集成化应用;
附图说明
下面结合附图和具体实施方式对本发明进一步详细的说明:
附图1为本发明实施的与氧化物半导体三维集成的cascode增强型GaN功率器件电路符号示意图;
附图2为本发明实施的与氧化物半导体三维集成的cascode增强型GaN功率器件平面示意图;
附图3为本发明实施的与氧化物半导体三维集成的cascode增强型GaN功率器件结构三维示意图;
附图4到附图17顺序为本发明制备工艺各步流程示意图;其中:
附图4为本发明所采用的GaN外延片衬底结构示意图;
附图5为本发明在衬底上淀积GaN MIS-HEMT源漏金属后器件结构示意图(金属材料为钛铝镍金叠层金属),
附图6为本发明ALD沉积高k栅介质层后器件结构示意图;
附图7为本发明淀积GaN MIS-HEMT栅极金属后器件结构示意图;
附图8为本发明沉积300 nm钝化层后器件结构示意图;
附图9为本发明淀积GaN MIS-HEMT源场板电极后器件结构示意图;
附图10为本发明淀积氧化物半导体晶体管底栅电极后器件结构示意图;
附图11为本发明沉积高k栅介质作为氧化物半导体晶体管栅介质后器件结构示意图;
附图12为本发明ALD沉积氧化物半导体薄膜后器件结构示意图;
附图13为本发明淀积氧化物半导体晶体管源极和漏极后器件结构示意图(源级、漏极的金属材料均为镍金);
附图14为本发明沉积100 nm钝化层之后器件结构示意图;
附图15为本发明氧化物半导体晶体管漏极和GaN MIS-HEMT源极互连后器件结构示意图;
附图16为本发明沉积100 nm钝化层后器件结构示意图;
附图17为本发明氧化物半导体晶体管源极和GaN MIS-HEMT栅极互连后器件结构示意图;
附图18为增强型氧化物半导体FET转移特性曲线图
附图19为耗尽型GaN MIS-HEMT转移特性曲线图
图20为氧化物半导体三维集成的cascode增强型GaN功率器件转移特性曲线示意图;
图中:1-AlGaN势垒层;2-GaN沟道层;3-GaN缓冲层;4-Si衬底;5-GaN MIS-HEMT的源极;6-GaN MIS-HEMT的漏极;7-高k介质层(HfO2高k介质);8-GaN MIS-HEMT的栅极;9-SiN钝化层;10-GaN MIS-HEMT的场板电极;
11-氧化物半导体FET底部栅极;12-氧化物半导体FET的栅极(高k栅介质HfO2);13-氧化物半导体薄膜;14-氧化物半导体FET的源极;15-氧化物半导体FET的漏极;16-第一钝化层(SiN钝化层);17-第一金属层;18-第二钝化层(SiN钝化层);19-第二金属层。
具体实施方式
如图所示,氧化物半导体三维集成的cascode增强型GaN功率器件,所述GaN功率器件包括GaN MIS-HEMT和氧化物半导体FET两者进行金属互联形成的cascode级联结构,为增强型功率器件,所述GaNMIS-HEMT由硅基衬底上外延的GaN/AlGaN叠层、高k介质、源/漏/栅电极、钝化层以及场板结构组成;所述增强型氧化物半导体FET在钝化层上方制备,自下而上分别为底栅电极、高k栅介质、氧化物半导体沟道、源/漏电极以及钝化层;
cascode级联结构中,氧化物半导体FET漏极和GaN MIS-HEMT源极以第一金属层17互连,氧化物半导体FET源极和GaNMIS-HEMT栅极以第二金属层19互连;第一金属层、第二金属层之间以以钝化层作为绝缘层;
所述增强型GaN功率器件的阈值电压由氧化物半导体FET决定,通过调节氧化物半导体的氧空位浓度及栅极金属功函数来实现增强性能,且阈值电压可调。
所述氧化物半导体FET元件与耗尽型GaN HEMT均设于GaN衬底的AlGaN势垒层1上;AlGaN势垒层下顺序设置GaN沟道层2、GaN缓冲层3、Si衬底4。
氧化物半导体三维集成的cascode增强型GaN功率器件的制作方法,用于制备以上所述的氧化物半导体三维集成的cascode增强型GaN功率器件,包括以下步骤;
步骤S1:将GaN衬底依次放在丙酮、异丙醇溶液中进行清洗,最后用氮气枪吹干;
步骤S2:在衬底上通过离子注入进行器件有源区隔离,隔绝器件与器件之间的电学干扰;
步骤S3:光刻定义出GaN MIS-HEMT的源极和漏极区域,在衬底上采用电子束蒸发连续沉积金属层作为GaN MIS-HEMT的源极5和GaN MIS-HEMT的漏极6,剥离掉源漏电极之外区域的金属,之后退火形成合金欧姆接触;
步骤S4:在用原子层沉积工艺沉积高k介质层7,即高k栅介质层;
步骤S5:在高k介质层上旋涂光刻胶并用电子束曝光将栅极图案化,采用物理气相沉积蒸镀金属层作为GaN MIS-HEMT的栅极8,并剥离多余的金属;
步骤S6:采用增强型等离子化学气相沉积钝化层9;
步骤S7:光刻定义出GaN MIS-HEMT的源极区域,对GaN MIS-HEMT源极区域的电极区域进行刻蚀开窗;采用光学光刻定义出源场板图形并沉积金属作为GaN MIS-HEMT的场板电极10与源电极相连;
步骤S8:旋涂光刻胶并用电子束曝光将氧化物半导体FET栅极图案化,使用PVD物理气相沉积在氧化物半导体FET有源区蒸镀作为氧化物半导体FET底部栅极11;
步骤S9:用原子层沉积工艺沉积高k介质层作为氧化物半导体FET的栅极12的介质;
步骤S10:采用原子层沉积或磁控溅射制备氧化物半导体沟道材料,即氧化物半导体FET的栅极上的氧化物半导体薄膜13;
步骤S11:在氧化物半导体薄膜上旋涂光刻胶后,以电子束曝光出氧化物半导体FET源极和漏极区域,利用PVD技术分别在氧化物半导体FET的源区和漏区蒸镀金属层作为氧化物半导体FET的源极14和漏极15;
步骤S12:采用增强型等离子化学气相沉积在样品上淀积第一钝化层16;
步骤S13:旋涂光刻胶后电子束曝光出氧化物半导体FET漏极区域以及GaN MIS-HEMT源极区域,开窗刻蚀形成接触通孔,完成氧化物半导体FET漏极和GaNMIS-HEMT源极的电极金属互联;
步骤S14:采用增强型等离子化学气相沉积在样品上淀积第二钝化层18;
步骤S15:旋涂光刻胶后电子束曝光出氧化物半导体FET源极区域以及GaN MIS-HEMT栅极区域,开窗刻蚀形成接触通孔,完成氧化物半导体FET源极和GaNMIS-HEMT栅极的电极金属互联。
所述的GaN衬底结构包括625 mm的Si衬底,3.9mm GaN缓冲层,300 nm的无掺杂的本征GaN沟道层以及20 nm铝元素组份为25%的无掺杂的本征AlGaN势垒层。
所述高k介质层包括Al2O3、HfO2、ZrO2、La2O3、HfAlOx、HfSiOx、HfLaOx、HfZrOx、HfSiON的一种或多种
步骤S5所述的金属层为20/50 nm镍/金。
所述钝化层材料为SiN、SiO2、Al2O3中的一种或多种。
步骤S7、S8、S11、S13、S15所述的金属层为2镍/金。
步骤S10所述氧化物半导体沟道材料包括氧化锌ZnO、氧化铟In2O3、氧化锡SnO2、氧化镓Ga2O3、氧化铟镓锌IGZO、氧化铟锡ITO、氧化铟锌IZO的一种或多种。
增强型GaN功率器件以衬底上的片上三维堆叠结构来降低芯片面积及寄生参数。
实施例:
本例中的制备过程具体如下:
步骤1:将GaN衬底放在55 ℃的丙酮溶液浸泡半小时去除表面污染物,之后在异丙醇溶液中浸泡两分钟去掉残余丙酮溶液,最后用氮气枪吹干样品表面。所述GaN衬底购买自日本NTT公司,外延片的基本结构包括625 mm的Si衬底,3.9mm GaN缓冲层,300 nm的无掺杂的本征GaN沟道层以及20 nm铝元素组份为25%的无掺杂的本征AlGaN势垒层。
步骤2:采用离子注入进行器件隔离,通过能量和密度递减的氩离子破坏AlGaN和GaN的晶格结构以实现稳定的GaN MIS-HEMT有源区隔离。
步骤3:光刻定义出GaN MIS-HEMT的源极和漏极区域,采用电子束蒸发连续沉积20/150/40/80 nm钛/铝/镍/金金属叠层作为GaNMIS-HEMT的源极和漏极,采用丙酮溶液浸泡剥离掉源漏电极之外区域的金属,之后在氮气氛围中以870 ℃退火30 s形成合金欧姆接触。
步骤4:将清洗干净的GaN衬底放入无水无氧的手套箱中,通过进样台将GaN衬底放入原子层沉积系统腔室中,通过原子层沉积(ALD)技术沉积20 nm高k栅介质HfO2作为GaNMIS-HEMT的栅介质,沉积温度为300℃,前驱体为四(二甲胺基)铪,氧源为臭氧。
步骤5:旋涂光刻胶并用电子束曝光将栅极图案化,采用物理气相沉积蒸镀20/50nm镍/金金属层作为GaN MIS-HEMT的栅极,并用丙酮溶液剥离多余的金属。
步骤6:采用增强型等离子化学气相沉积在样品上淀积300 nm SiN作为钝化层和金属绝缘层。
步骤7:光刻定义出GaN MIS-HEMT的源极区域,对GaN MIS-HEMT源极区域的电极进行刻蚀开窗。采用光学光刻定义出源场板图形并沉积120/60nm镍/金金属层作为场板电极与源电极相连。
步骤8:旋涂光刻胶后曝光氧化物半导体晶体管栅极区域,沉积金属20/40 nm镍/金金属作为底栅电极,剥离去除栅极区域外的金属,去除残余光刻胶。
步骤9:将样品放入原子层沉积系统腔室中ALD沉积高k栅介质10nm HfO2,沉积温度为300 ℃,前驱体为四(二甲胺基)铪,氧源为臭氧。
步骤10:旋涂光刻胶后曝光氧化物半导体晶体管沟道区域,ALD沉积6 nm 氧化物半导体薄膜作为晶体管沟道,剥离去除沟道区域外的氧化物半导体薄膜,以氧化铟锡为例,反应前驱体分别为三甲基铟、四(二甲胺)锡和水,沉积温度为200℃,去除残余光刻胶。
步骤11:旋涂光刻胶后曝光氧化物半导体晶体管源漏区域,ALD沉积金属Ni/Au:20/40 nm作为源漏电极,剥离去除源漏区域外的多余金属,去除残余光刻胶,之后在氮气氛围中以870 ℃退火30 s形成合金欧姆接触。
步骤12:采用增强型等离子化学气相沉积在样品上淀积100 nm SiN钝化层。
步骤13:旋涂光刻胶后曝光出氧化物半导体晶体管漏极区域以及GaN MIS-HEMT源极区域,刻蚀形成对应电极接触通孔,去除残余光刻胶,实现氧化物半导体晶体管漏极和GaN MIS-HEMT源极的电极金属互联。
步骤14:采用增强型等离子化学气相沉积在样品上淀积100 nm钝化层SiN。
步骤15:与步骤14类似,旋涂光刻胶后曝光出氧化物半导体晶体管源极区域以及GaN MIS-HEMT栅极区域,刻蚀钝化层形成接触通孔,去除残余光刻胶,进行氧化物半导体晶体管源极和GaN MIS-HEMT栅极的电极金属互联。
本专利不局限于上述最佳实施方式,凡依本发明申请专利范围所做的均等变化与修饰,皆应属本发明的涵盖范围。
Claims (10)
1.氧化物半导体三维集成的cascode增强型GaN功率器件,其特征在于:所述GaN功率器件包括GaN MIS-HEMT和氧化物半导体FET两者进行金属互联形成的cascode级联结构,为增强型功率器件,所述GaN MIS-HEMT由硅基衬底上外延的GaN/AlGaN叠层、高k介质、源/漏/栅电极、钝化层以及场板结构组成;所述增强型氧化物半导体FET在钝化层上方制备,自下而上分别为底栅电极、高k栅介质、氧化物半导体沟道、源/漏电极以及钝化层;
cascode级联结构中,氧化物半导体FET漏极和GaN MIS-HEMT源极以第一金属层(17)互连,氧化物半导体FET源极和GaN MIS-HEMT栅极以第二金属层(19)互连;第一金属层、第二金属层之间以以钝化层作为绝缘层;
所述增强型GaN功率器件的阈值电压由氧化物半导体FET决定,通过调节氧化物半导体的氧空位浓度及栅极金属功函数来实现增强性能,且阈值电压可调。
2.根据权利要求1所述的氧化物半导体三维集成的cascode增强型GaN功率器件,其特征在于:所述氧化物半导体FET元件与耗尽型GaN HEMT均设于GaN衬底的AlGaN势垒层(1)上;AlGaN势垒层下顺序设置GaN沟道层(2)、GaN缓冲层(3)、Si衬底(4)。
3.氧化物半导体三维集成的cascode增强型GaN功率器件的制作方法,用于制备权利要求1所述的氧化物半导体三维集成的cascode增强型GaN功率器件,其特征在于:包括以下步骤;
步骤S1:将GaN衬底依次放在丙酮、异丙醇溶液中进行清洗,最后用氮气枪吹干;
步骤S2:在衬底上通过离子注入进行器件有源区隔离,隔绝器件与器件之间的电学干扰;
步骤S3:光刻定义出GaN MIS-HEMT的源极和漏极区域,在衬底上采用电子束蒸发连续沉积金属层作为GaN MIS-HEMT的源极(5)和GaN MIS-HEMT的漏极(6),剥离掉源漏电极之外区域的金属,之后退火形成合金欧姆接触;
步骤S4:在用原子层沉积工艺沉积高k介质层(7),即高k栅介质层;
步骤S5:在高k介质层上旋涂光刻胶并用电子束曝光将栅极图案化,采用物理气相沉积蒸镀金属层作为GaN MIS-HEMT的栅极(8),并剥离多余的金属;
步骤S6:采用增强型等离子化学气相沉积钝化层(9);
步骤S7:光刻定义出GaN MIS-HEMT的源极区域,对GaN MIS-HEMT源极区域的电极区域进行刻蚀开窗;采用光学光刻定义出源场板图形并沉积金属作为GaN MIS-HEMT的场板电极(10)与源电极相连;
步骤S8:旋涂光刻胶并用电子束曝光将氧化物半导体FET栅极图案化,使用PVD物理气相沉积在氧化物半导体FET有源区蒸镀作为氧化物半导体FET底部栅极(11);
步骤S9:用原子层沉积工艺沉积高k介质层作为氧化物半导体FET的栅极(12)的介质;
步骤S10:采用原子层沉积或磁控溅射制备氧化物半导体沟道材料,即氧化物半导体FET的栅极上的氧化物半导体薄膜(13);
步骤S11:在氧化物半导体薄膜上旋涂光刻胶后,以电子束曝光出氧化物半导体FET源极和漏极区域,利用PVD技术分别在氧化物半导体FET的源区和漏区蒸镀金属层作为氧化物半导体FET的源极(14)和漏极(15);
步骤S12:采用增强型等离子化学气相沉积在样品上淀积第一钝化层(16);
步骤S13:旋涂光刻胶后电子束曝光出氧化物半导体FET漏极区域以及GaN MIS-HEMT源极区域,开窗刻蚀形成接触通孔,完成氧化物半导体FET漏极和GaN MIS-HEMT源极的电极金属互联;
步骤S14:采用增强型等离子化学气相沉积在样品上淀积第二钝化层(18);
步骤S15:旋涂光刻胶后电子束曝光出氧化物半导体FET源极区域以及GaN MIS-HEMT栅极区域,开窗刻蚀形成接触通孔,完成氧化物半导体FET源极和GaN MIS-HEMT栅极的电极金属互联。
4.根据权利要求3所述的氧化物半导体三维集成的cascode增强型GaN功率器件的制作方法,其特征在于:所述的GaN衬底结构包括625 mm的Si衬底,3.9 mm GaN缓冲层,300 nm的无掺杂的本征GaN沟道层以及20 nm铝元素组份为25%的无掺杂的本征AlGaN势垒层。
5.根据权利要求3所述的氧化物半导体三维集成的cascode增强型GaN功率器件的制作方法,其特征在于:所述高k介质层包括Al2O3、HfO2、ZrO2、La2O3、HfAlOx、HfSiOx、HfLaOx、HfZrOx、HfSiON的一种或多种。
6.根据权利要求3所述的氧化物半导体三维集成的cascode增强型GaN功率器件的制作方法,其特征在于:步骤S5所述的金属层为20/50 nm镍/金。
7.根据权利要求3所述的氧化物半导体三维集成的cascode增强型GaN功率器件的制作方法,其特征在于:所述钝化层材料为SiN、SiO2、Al2O3中的一种或多种。
8.根据权利要求3所述的氧化物半导体三维集成的cascode增强型GaN功率器件的制作方法,其特征在于:步骤S7、S8、S11、S13、S15所述的金属层为2镍/金。
9.根据权利要求3所述的氧化物半导体三维集成的cascode增强型GaN功率器件的制作方法,其特征在于:步骤S10所述氧化物半导体沟道材料包括氧化锌ZnO、氧化铟In2O3、氧化锡SnO2、氧化镓Ga2O3、氧化铟镓锌IGZO、氧化铟锡ITO、氧化铟锌IZO的一种或多种。
10.根据权利要求3所述的氧化物半导体三维集成的cascode增强型GaN功率器件的制作方法,其特征在于:增强型GaN功率器件以衬底上的片上三维堆叠结构来降低芯片面积及寄生参数。
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