CN115461875A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN115461875A
CN115461875A CN202180029686.5A CN202180029686A CN115461875A CN 115461875 A CN115461875 A CN 115461875A CN 202180029686 A CN202180029686 A CN 202180029686A CN 115461875 A CN115461875 A CN 115461875A
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China
Prior art keywords
layer
gate
mosfet
semiconductor device
ciss
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CN202180029686.5A
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English (en)
Inventor
河野宪司
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Denso Corp
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Denso Corp
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Publication of CN115461875A publication Critical patent/CN115461875A/zh
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
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  • Junction Field-Effect Transistors (AREA)
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Abstract

具备：JFET(10)，具有源极电极(11)、漏极电极(12)、栅极电极(13)；以及MOSFET(20)，具有源极电极(21)、漏极电极(22)、栅极电极(23)；JFET(10)的源极电极(11)和MOSFET(20)的漏极电极(22)被电连接从而JFET(10)和MOSFET(20)被级联连接。并且，将JFET(10)的栅极电压的漏极电压依存性设为栅极电压依存性，调整栅极电压依存性以使得能够减小开关损耗。

Description

半导体装置
关联申请的相互参照
本申请基于2020年4月22日提出的日本专利申请第2020－76335号，这里通过参照而引用其记载内容。
技术领域
本发明涉及将结型FET(Field Effect Transistor：以下简称作JFET)和MOSFET(Metal Oxide Semiconductor Field Effect Transistor的简称)级联连接的半导体装置。
背景技术
以往，提出了将常导通型(normally on)的JFET和常断开(normally off)型的MOSFET级联连接的半导体装置。另外，JFET例如使用碳化硅衬底或氮化镓衬底等构成，MOSFET例如使用硅衬底构成。并且，在JFET中，为了使浪涌耐受性提高而形成了体二极管(body diode)。
现有技术文献
专利文献
专利文献1：日本特开2019－29997号公报
发明内容
此外，近年来，在这样的级联连接的半导体装置中，希望减小开关损耗。
鉴于以上，本发明的目的在于，提供能够减小开关损耗的半导体装置。
根据本发明的一技术方案，半导体装置，具备：JFET，具有源极电极、漏极电极、栅极电极；以及MOSFET，具有源极电极、漏极电极、栅极电极；JFET的源极电极和MOSFET的漏极电极被电连接从而JFET和MOSFET被级联连接；将JFET的栅极电压的漏极电压依存性设为栅极电压依存性而设为ΔVgJ，将电流变化率设为dI/dt，将电压变化率设为dV/dt，将电源电压设为Vd，将动作电流设为Id，将JFET的延迟时间设为ΔtmJ，将MOSFET的镜像电容设为Cgd，将MOSFET的输入电容设为Ciss，将MOSFET的栅极镜像电位设为Vm，将MOSFET的栅极阈值设为Vth，将Id/(Vm-Vth)设为g，则栅极电压依存性被设为下述数式1以上且数式2以下。
[数式1]
ΔVgJ＝(Vd×Id-ΔtmJ×Id×dV/dt)/g/(Cgd/Ciss)/(Vd-ΔtmJ×dV/dt)
[数式2]
ΔVgJ＝Vd/g/(Cgd/Ciss)×{(dI/dt/dV/dt)-ΔtmJ/g/(Cgd/Ciss)×dI/dt
由此，栅极电压依存性为数式1以上且数式2以下，所以能够实现开关损耗的减小。
此外，根据本发明的另一技术方案，半导体装置，具备：JFET，具有源极电极、漏极电极、栅极电极；以及MOSFET，具有源极电极、漏极电极、栅极电极；JFET的源极电极和MOSFET的漏极电极被电连接从而JFET和MOSFET被级联连接；将JFET的栅极电压的漏极电压依存性设为栅极电压依存性而设为ΔVgJ，将电流变化率设为dI/dt，将电压变化率设为dV/dt，将电源电压设为Vd，将动作电流设为Id，将JFET的延迟时间设为ΔtmJ，将MOSFET的镜像电容设为Cgd，将MOSFET的输入电容设为Ciss，将MOSFET的栅极镜像电位设为Vm，将MOSFET的栅极阈值设为Vth，将Id/(Vm-Vth)设为g，将镜像电容相对于输入电容的电容比设为Cgd/Ciss，则电容比被设为下述数式3以上且数式4以下。
[数式3]
Cgd/Ciss＝Id/g/ΔVgJ
[数式4]
Cgd/Ciss＝(Vd/ΔVgJ)×dI/dt/(g× dV/dt)-ΔtmJ/ΔVgJ/(g×dI/dt)
由此，电容比为数式3以上且数式4以下，所以能够实现开关损耗的减小。
另外，对各构成要素等赋予的带括号的标号表示该构成要素等与后述实施方式中记载的具体构成要素等的对应关系的一例。
附图说明
图1是第1实施方式的半导体装置的电路图。
图2是形成JFET的第1半导体芯片的平面图。
图3是图2中的区域III的放大图。
图4是沿着图3中的IV－IV线的剖视图。
图5是沿着图3中的V－V线的剖视图。
图6是沿着图3中的VI－VI线的剖视图。
图7是形成MOSFET的第2半导体芯片的平面图。
图8是沿着图7中的VIII－VIII线的剖视图。
图9是沿着图7中的IX－IX线的剖视图。
图10是表示关于栅极电压依存性与开关损耗之间的关系的模拟结果的图。
图11是表示关于构成调整区域的剂量与栅极电压依存性之间的关系的模拟结果的图。
图12是表示关于调整区域的长度与栅极电压依存性之间的关系的模拟结果的图。
图13是第2实施方式的第1半导体芯片的剖视图。
图14是表示关于外缘部的杂质浓度与栅极电压依存性之间的关系的模拟结果的图。
图15是第4实施方式的半导体装置的电路图。
图16是利用图15所示的半导体装置构成的逆变器(inverter)的电路图。
图17是图16中的U层的电路图。
具体实施方式
以下，基于附图对本发明的实施方式进行说明。另外，在以下各实施方式中，对于彼此相同或等同的部分赋予相同的标号而进行说明。
(第1实施方式)
参照附图对第1实施方式进行说明。首先，对本实施方式的半导体装置的电路结构进行说明。如图1所示，本实施方式的半导体装置，具有常导通(normally on)型的结型FET10和常截止(normally off)型的MOSFET20，将JFET10和MOSFET20级联连接而构成。另外，在本实施方式中，JFET10及MOSFET20分别为N沟道型。
JFET10具有源极电极11、漏极电极12、栅极层(即栅极电极)13，具体结构后述。MOSFET20具有源极电极21、漏极电极22及栅极电极23，具体结构后述。
并且，JFET10及MOSFET20中，JFET10的源极电极11和MOSFET20的漏极电极22电连接。此外，JFET10的漏极电极12与第1端子31连接，MOSFET20的源极电极21与第2端子32连接。
MOSFET20的栅极电极23经由栅极焊盘24及调整电阻41而与栅极驱动电路50连接。JFET10的栅极层13经由栅极焊盘14而与MOSFET20的源极电极21电连接。
此外，在本实施方式中，在JFET10的漏极电极12与源极电极11之间连接着二极管15。在本实施方式中，JFET10如图4所示那样在N型的沟道层114内形成有P型的体(body)层115，具体后述。并且，二极管15包括该体层115而构成。该二极管15成为阴极与漏极电极12电连接、阳极与源极电极11电连接的状态。
此外，在MOSFET20的漏极电极22与源极电极21之间连接着二极管25。该二极管25是在MOSFET20的结构上形成的寄生二极管，阴极与漏极电极22电连接，阳极与源极电极21电连接。
以上是本实施方式的半导体装置的电路结构。并且，这样的半导体装置如以下那样使用，即：第1端子31与从电源60施加电压Vcc的电源线61连接，第2端子32与地线62连接。
接着，对JFET10及MOSFET20的具体结构进行说明。首先，对JFET10的结构进行说明。JFET10如图2所示，形成于第1半导体芯片100。
第1半导体芯片100如图2及图3所示那样，平面形状为矩形，具有单元区域101以及将单元区域101包围的外周区域102，所述单元区域101具有内缘单元区域101a和将内缘单元区域101a包围的外缘单元区域101b。并且，JFET10形成在单元区域101。
具体而言，第1半导体芯片100如图4～图6所示，具备半导体衬底110，该半导体衬底110具有由N++型的碳化硅(以下称作SiC)衬底构成的漏极层111。并且，漏极层111上配置有杂质浓度比漏极层111低的N+型的缓冲层112，在缓冲层112上配置有杂质浓度比缓冲层112低的N－型的漂移层113。另外，缓冲层112及漂移层113通过在构成漏极层111的SiC衬底上使SiC的外延膜成长而构成。
并且，在单元区域101，在半导体衬底110的一面110a侧形成有沟道层114、栅极层13、体层115及源极层116。具体而言，在单元区域101，在漂移层113上配置有杂质浓度比漂移层113高的N型的沟道层114。另外，沟道层114例如通过使SiC的外延膜成长而构成。并且，半导体衬底110的一面110a包括沟道层114的表面而构成。
在沟道层114中，形成有杂质浓度比沟道层114高的P+型的栅极层13及P+型的体层115。在本实施方式中，栅极层13及体层115杂质浓度彼此相等，并且从半导体衬底110的一面110a(即，沟道层114的表面)沿着深度方向形成。但是，在本实施方式中，体层115比栅极层13形成得更深。即，体层115是比栅极层13更向漏极层111侧突出的结构。
此外，栅极层13及体层115沿着半导体衬底110的面方向上的一个方向延伸设置，在该面方向上的与延伸设置方向正交的方向上交替地配置。即，在图4中，栅极层13及体层115沿着纸面垂直方向延伸设置，在沿着纸面左右方向相互离开的状态下交替地配置。另外，半导体衬底110的深度方向换言之也可以说是漏极层111、漂移层113、沟道层114的层叠方向。此外，栅极层13及体层115例如通过离子注入或使SiC的埋入外延膜成长而构成。
在本实施方式中，如图3、图5、图6所示，栅极层13从内缘单元区域101a延伸设置到外缘单元区域101b。并且，栅极层13通过使位于外缘单元区域101b中的延伸设置方向的两端部环绕而被做成环状构造，被做成环状构造的部分被相互连接。因此，图4中的体层115也可以说配置在被做成环状构造的栅极层13的内缘侧的区域。
另外，体层115还形成在外缘单元区域101b，如后述那样，与形成于外周区域102的多个保护环121中的1个连接。
此外，如图4所示，在沟道层114的表层部，以与体层115相接的方式形成有杂质浓度比沟道层114高的N+型的源极层116。进而，在本实施方式的沟道层114中，在栅极层13与体层115之间形成有N型的调整区域117。关于该调整区域117的功能，具体地在后面叙述。另外，源极层116及调整区域117例如通过离子注入而构成。
并且，如图2、图5及图6所示，在半导体衬底110上，在外缘单元区域101b中形成有栅极焊盘14和与该栅极焊盘14及栅极层13电连接的栅极布线118。另外，在第1半导体芯片100，虽然没有特别图示，但还形成有温度感测部或电流感测部等。并且，在外缘单元区域101b，还形成有与这些各种感测部电连接的焊盘16及未图示的布线。
此外，如图4～图6所示，在半导体衬底110的一面110a上，以将栅极布线118覆盖的方式形成有层间绝缘膜119。另外，层间绝缘膜119形成在单元区域101及外周区域102。并且，在层间绝缘膜119，在单元区域101中形成有使沟道层114、体层115及源极层116露出的接触孔119a。在层间绝缘膜119上，形成有经由接触孔119a而与源极层116及体层115电连接的源极电极11。
在半导体衬底110的另一面110b侧，形成有与漏极层111电连接的漏极电极12。
外周区域102如图5及图6所示，通过形成将相当于单元区域101的沟道层114的部分除去的凹部120而被做成台面(mesa)构造。并且，在外周区域102，形成有将单元区域101包围的被做成多重环构造的多个保护环121。另外，在本实施方式中，多个保护环121中的最靠单元区域101侧的1个与形成在外缘单元区域101b中的体层115电连接，但也可以不电连接。
以上是本实施方式的第1半导体芯片100的结构。另外，在本实施方式的第1半导体芯片100中，N－型、N型、N+型、N++型相当于第1导电型，P型、P+型相当于第2导电型。此外，在本实施方式中，如上述那样，包含漏极层111、缓冲层112、漂移层113、沟道层114、体层115、源极层116、调整区域117、栅极层13而构成半导体衬底110。并且，在本实施方式中，如上述那样，漏极层111由SiC衬底构成，缓冲层112、漂移层113、沟道层114等通过使SiC的外延膜成长而构成。因此，本实施方式的第1半导体芯片100也可以说是SiC半导体装置。此外，在本实施方式中，第1半导体芯片100形成有P型的体层115。并且，图1中的二极管15起因于体层115而构成。
接着，对MOSFET20的结构进行说明。MOSFET20如图7所示，形成于第2半导体芯片200。
第2半导体芯片200，平面形状为矩形，具有单元区域201及将单元区域201包围的外周区域202。并且，MOSFET20形成在单元区域201。
具体而言，第2半导体芯片200如图8及图9所示，具备半导体衬底210，该半导体衬底210具有由N+型的硅(以下称作Si)衬底构成的漏极层211。在漏极层211上，配置有杂质浓度比漏极层211低的N型的漂移层212。并且，在单元区域201中，在漂移层212上配置有杂质浓度比漂移层212高的P型的沟道层213。
此外，在半导体衬底210，以将沟道层213贯通而达到漂移层212的方式形成有多个沟槽214，通过该沟槽214将沟道层213分离为多个。在本实施方式中，多个沟槽214沿着半导体衬底210的一面210a的面方向中的一个方向(即，图8中纸面进深方向)以等间隔形成为条状。另外，也可以将多个沟槽214通过将前端部环绕而做成环状构造。
此外，各沟槽214内被以将各沟槽214的壁面覆盖的方式形成的栅极绝缘膜215和形成在该栅极绝缘膜215之上的由多晶硅等构成的栅极电极23填埋。由此，构成沟槽栅构造。
并且，在沟道层213中，形成有N+型的源极层216和被源极层216夹着的P+型的接触层217。源极层216杂质浓度比漂移层212高，在沟道层213内终止，并且以与沟槽214的侧面相接的方式形成。接触层217杂质浓度比沟道层213高，与源极层216同样，以在沟道层213内终止的方式形成。
更详细地讲，源极层216在沟槽214间的区域沿着沟槽214的长度方向以与沟槽214的侧面相接的方式以棒状延伸设置，成为在沟槽214的前端的内侧终止的构造。此外，接触层217被2个源极层216夹着而沿着沟槽214的长度方向(即源极层216)以棒状延伸设置。另外，本实施方式的接触层217以半导体衬底210的一面210a为基准形成得比源极层216深。
在沟道层213(即，半导体衬底210的一面210a)上，形成有层间绝缘膜218。另外，该层间绝缘膜218如图9所示也形成在外周区域202。在层间绝缘膜218，形成有使源极层216的一部分及接触层217露出的接触孔218a。在层间绝缘膜218上，形成有经由接触孔218a而与源极层216及接触层217电连接的源极电极21。
在半导体衬底210的另一面210b侧，形成有与漏极层211电连接的漏极电极22。
此外，在外周区域202，如图7所示，形成有栅极焊盘24及未图示的栅极布线等。并且，栅极布线在与图8及图9不同的截面中适当地与栅极电极23电连接。另外，在第2半导体芯片200，虽然没有特别图示，但还形成有温度感测部及电流感测部等。并且，在外周区域202，还形成有与这些各种感测部电连接的焊盘26及未图示的布线。
进而，在外周区域202，为了实现耐压提高，在单元区域201侧的内缘部形成有P型的深层220，并且，在比深层220靠外缘部侧，作为多重环构造而形成有多个P型的保护环221。另外，本实施方式的深层220与沟道层213相连，并且形成至比沟道层213深的位置。此外，在外周区域202，形成有将层间绝缘膜218覆盖的保护膜222，在保护膜222，形成有使源极电极21露出的开口部222a。
以上是本实施方式的第2半导体芯片200的结构。另外，在本实施方式的第2半导体芯片200中，N型、N－型、N+型、N++型相当于第1导电型，P型、P+型相当于第2导电型。此外，在本实施方式中，如上述那样，包括漏极层211、漂移层212、沟道层213、源极层216及接触层217而构成半导体衬底210。进而，在本实施方式中，如上述那样使用Si衬底构成第2半导体芯片200。因此，第2半导体芯片200也可以说是Si半导体装置。
并且，虽然没有特别图示，将这些形成于第1半导体芯片100的JFET10与形成于第2半导体芯片200的MOSFET20以级联连接的方式电连接而构成本实施方式的半导体装置。
接着，对上述半导体装置的基本动作进行说明。另外，本实施方式的半导体装置由于具有常截止的MOSFET20，所以整体为常截止而进行动作。
首先，为了使半导体装置进行开关导通(switching on)动作而成为导通状态，从栅极驱动电路50对MOSFET20的栅极电极23施加阈值电压以上的栅极电压。由此，常截止型的MOSFET20成为导通状态。此外，JFET10的栅极层13与第2端子32连接。因此，关于常导通型的JFET10，栅极层13与源极电极11的电位差大致为零，成为导通状态。因而，在第1端子31与第2端子32之间流过电流，半导体装置最终成为导通状态。
接着，为了使半导体装置进行开关断开(switching off)动作而成为截止状态，使施加在MOSFET20的栅极电极23上的栅极电压比阈值电压小(例如设为0V)。由此，常截止型的MOSFET20成为截止状态。此外，由于MOSFET20成为截止状态，MOSFET20的漏极电极22和与其连接的JFET10的源极电极11的电压上升，在该源极电极11与连接于第2端子32的JFET10的栅极层13之间产生电位差。并且，源极电极11与栅极层13之间的电位差达到阈值，从而沟道消失，JFET10成为截止状态。由此，在第1端子31与第2端子32之间不再流过电流，半导体装置最终成为截止状态。
并且，本发明的发明人为了对上述半导体装置减小开关损耗而进行了专门研究，得到了以下的结果。即，本发明的发明人发现，通过调整JFET10的栅极电压的漏极电压依存性ΔVgJ，能够调整开关损耗，得到了图10所示的结果。另外，以下，将JFET10的栅极电压的漏极电压依存性ΔVgJ也简称作栅极电压依存性ΔVgJ。
具体而言，本发明的发明人研究了栅极电压依存性ΔVgJ与由电流变化率dI/dt(以下也简称作dI/dt)规定的开关损耗Et(dI/dt)之间的关系。此外，本发明的发明人研究了栅极电压依存性ΔVgJ与由电压变化率dV/dt(以下也简称作dV/dt)规定的开关损耗Et(dV/dt)之间的关系。进而，本发明的发明人研究了栅极电压依存性ΔVgJ与作为开关损耗Et(dI/dt)和开关损耗Et(dV/dt)之和的总开关损耗Esum(即，Et(dI/dt)+Et(dV/dt))之间的关系。
另外，dI/dt与自浪涌有关，dV/dt相当于在构成了逆变器等系统时可能发生的马达浪涌(motor surge)等系统浪涌(system surge)。此外，图10中的Et(dI/dt)是5kA/μs下的模拟结果，Et(dV/dt)是30kV/μs下的模拟结果。
以下，对于栅极电压依存性ΔVgJ和各开关损耗具体地进行说明。另外，以下，将从在半导体装置中流过电流的状态将该电流截断也称作截止时，将从在半导体装置中不流过电流的状态设为流过电流的状态也称作导通时。此外，以下，将使半导体装置截止时的开关损耗设为Eoff，将使半导体装置导通时的开关损耗设为Eon，设电源电压为Vd，设动作电流为Id，设截止时间为toff，设导通时间为ton，设镜像(mirror)时间为tm。此外，以下，设MOSFET20的栅极电阻为Rg，设MOSFET20的镜像电容为Cgd，设MOSFET20的输入电容为Ciss，设MOSFET20的栅极镜像电位为Vm，设MOSFET20的栅极驱动电压为Vg，设MOSFET20的栅极阈值为Vth(Vth＞0)。此外，以下，设JFET10的延迟时间为ΔtmJ，设JEET10的栅极-源极间电容为CgsJ，设JFET10的栅极阈值(栅极阈值＜0)为VthJ，设JFET10的栅极-漏极间电容为CgdJ，设JFET10的栅极电位为VgJ，设JFET10的寄生栅极电阻为RJ。
首先，半导体装置截止时的开关断开损耗Eoff由下述数式5表示。
[数式5]
Eoff＝Vd×Id/{2×(tm+toff)}
数式5中的tm由下述数式6表示。
[数式6]
tm＝(Rg×Cgd×ΔVgJ)/Vm+ΔtmJ
数式6中的ΔtmJ由下述数式7表示。
[数式7]
ΔtmJ＝(CgsJ×|VthJ|+CgdJxVd)/(VgJ/RJ)
此外，数式5中的toff由下述数式8表示。
[数式8]
toff＝Rg×Ciss×in(Vm/Vth)
并且，在开关断开时，dV/dt由下述数式9表示，dI/dt由下述数式10表示。
[数式9]
dV/dt＝Vd/tm
[数式10]
dI/dt＝Id/toff
此外，使半导体装置导通时的开关导通损耗Eon由下述数式11表示。
[数式11]
Eon＝Vd×Id/{2×(tm+ton)}
数式11中的tm由下述数式12表示。
[数式12]
tm＝{Rg×Cgd×ΔVgJ)/(Vg-Vm)}+ΔtmJ
数式12中的ΔtmJ由下述数式13表示。另外，数式13与上述数式7是同样的。
[数式13]
ΔtmJ＝(CgsJ×|VthJ|+CgdJxVd)/(VgJ/RJ)
此外，数式11中的ton由下述数式14表示。
[数式14]
ton＝Rg×Ciss×In{(Vg-Vth)/(Vg-Vm)}
并且，在开关导通时，dV/dt由下述数式15表示，dI/dt由下述数式16表示。
[数式15]
dV/dt＝Vd/tm
[数式16]
dI/dt＝Id/ton
该情况下，由dI/dt规定的开关损耗Et(dI/dt)由下述数式17表示。
[数式17]
Et(dI/dt)＝Eon+Eoff+Err
并且，开关损耗Et(dI/dt)中的Eoff及Eon由下述数式18及数式19表示。
[数式18]
Eoff＝Vd×Id2/2×[1+{Cgd×ΔVgJ/(Vm×Ciss)/In(Vm/Vth)}+dI/dt/(Id×ΔtmJ)]/dI/dt
[数式19]
Eon＝Vd×Id2/2×[1+ΔVgJ×Cgd)/{(Vg-Vm)×Ciss}/In{(Vg-Vth)/(Vg-Vm)}+dI/dt/(Id×ΔtmJ)]/dI/dt
另外，恢复损耗Err通常相对于Eon、Eoff充分小，所以在数式18及数式19中忽视。同样，由dV/dt规定的开关损耗Et(dV/dt)由下述数式20表示。
[数式20]
Et(dV/dt)＝Eon+Eoff+Err
此外，开关损耗Et(dV/dt)中的Eoff及Eon由下述数式21及数式22表示。
[数式21]
Eoff＝Vd2×Id/2×[1+(1-ΔtmJ×dV/dt/Vd)×(Vm/Cgd/{ΔVgJ×Ciss×In(Vm/Vth)}]/dv/dt
[数式22]
Eon＝Vd2×Id/2×[1+{1-dV/dt/(Vd×ΔtmJ)}×Ciss×In{(Vg-Vth)/(Vg-Vm)}×(Vg-Vm)/Cgd/ΔVgv]/dV/dt
另外，恢复损耗Err通常相对于Eon、Eoff充分小，所以在数式21及数式22中忽视。
并且，如图10所示，确认到：栅极电压依存性ΔVgJ越大则开关损耗Et(dV/dt)越小，栅极电压依存性ΔVgJ越大则开关损耗Et(dI/dt)越大。即，开关损耗Et(dV/dt)和开关损耗(dI/dt)的与栅极电压依存性ΔVgJ对应的关系是相反的。并且，半导体装置优选以开关损耗Et(dV/dt)及开关损耗Et(dI/dt)都变小的方式构成。即，半导体装置优选以总开关损耗Esum变小的方式构成。因此，本实施方式的半导体装置如以下这样构成。
首先，设开关损耗Et(dI/dt)中的斜率的大小(即绝对值)最小的部分的切线为切线SI1，设斜率的大小最大的部分的切线为切线SI2。同样，设开关损耗Et(dV/dt)中的斜率的大小最小的部分的切线为切线SV1，设斜率的大小最大的部分的切线为切线SV2。该情况下，切线SI1、SI2及切线SV1、SV2分别在栅极电压依存性ΔVgJ为x1时交叉。即，开关损耗Et(dI/dt)及开关损耗Et(dV/dt)在交点x1处急剧地变化。并且，交点x1处的栅极电压依存性ΔVgJ基于上述数式5～22而由下述数式23表示。
[数式23]
×1＝ΔVgJ＝(Vd×Id-ΔtmJ×Id×dV/dt)/g/(Cgd/Ciss)/(Vd-ΔtmJ×dV/dt)
另外，在数式23中，g是Id/(Vm-Vth)，表示MOSFET20的电导。此外，后述的以下的式中的g也是同样的。
此外，开关损耗Et(dI/dt)和开关损耗Et(dV/dt)的交点x2为Et(dI/dt)＝Et(dV/dt)。因此，该交点x2处的栅极电压依存性ΔVgJ基于上述数式5～22而由下述数式24表示。
[数式24]
×2＝ΔVgJ＝Vd/g/(Cgd/Ciss)×{(dI/dt/dV/dt)-ΔtmJ/g/(Cgd/Ciss)×dI/dt
此外，总开关损耗Esum的最小值x3的栅极电压依存性基于上述数式5～22而由下述数式25表示。
[数式25]
×3＝ΔVgJ＝1/g/(Cgd/Ciss)×[(Vd×Id×dI/dt/dV/dt)×(1-(ΔtmJ/Vd)×dV/dt)}1/2
因而，本实施方式的半导体装置构成为，JFET10的栅极电压依存性ΔVgJ为上述数式23以上且上述数式24以下。该情况下，半导体装置通过以使栅极电压依存性ΔVgJ满足上述数式25的方式构成，能够使总开关损耗Esum最小。另外，通常，JFET的寄生栅极电阻RJ极小，所以如上述数式7所示那样，由栅极电阻RJ规定的ΔtmJ可以忽视。即，可以将ΔtmJ设为0。
这里，在本实施方式的JFET10中，如上述那样，在沟道层114中形成有调整区域117。并且，如图11所示，确认到：栅极电压依存性ΔVgJ能够通过改变构成调整区域117的剂量而容易地变更。具体而言，确认到：栅极电压依存性ΔVgJ通过将构成调整区域117的剂量增多而变大。
因此，在本实施方式中，对调整区域117的剂量进行了调整，以成为上述数式23以上且上述数式24以下的栅极电压依存性ΔVgJ。另外，图11的ΔVgJ示出了在半导体装置中流过40A的电流时、设电源电压为400V时的JFET10的栅极电位与设电源电压为0.5V时的JFET10的栅极电位之差。
根据以上说明的本实施方式，JFET10的栅极电压依存性ΔVgJ被设为上述数式23以上且上述数式24以下。因此，能够实现开关损耗的减小。该情况下，特别是，通过将JFET10的栅极电压依存性ΔVgJ设为上述数式25，能够使开关损耗最小。
此外，JFET10在沟道层114中形成有调整区域117。因此，通过将构成调整区域117的剂量变更，能够容易地调整JFET10的栅极电压依存性ΔVgJ。即，根据本实施方式，能够在抑制结构复杂化的同时减小开关损耗。
进而，在本实施方式中，体层115比栅极层13深。因此，关于电场强度，在体层115的底部侧容易比栅极层13的底部侧变高。因而，当发生了浪涌时，在体层115的底部侧的区域容易发生击穿，浪涌电流容易向体层115流入。由此，栅极布线118熔断从而还能够抑制半导体装置的损坏，能够实现浪涌耐受性的提高。
(第1实施方式的变形例)
对上述第1实施方式的变形例进行说明。在上述第1实施方式中，说明了通过变更构成JFET10的调整区域117的剂量来变更栅极电压依存性ΔVgJ的例子。但是，在变更JFET10的栅极电压依存性ΔVgJ的情况下，也可以如以下这样进行。例如，如果如图4所示那样设调整区域117的沿着深度方向的长度为长度L，则如图12所示，栅极电压依存性ΔVgJ即使将长度L变更也会变化。具体而言，如果使调整区域117的长度L变长，则栅极电压依存性ΔVgJ变大。因此，对于调整区域117而言，也可以将调整区域117的长度L进行调整，以使得成为上述数式23以上且上述数式24以下的栅极电压依存性ΔVgJ。
此外，虽然没有特别图示，但栅极电压依存性ΔVgJ也可以通过改变调整区域117的沿着半导体衬底110的面方向的宽度、调整区域117的形成深度等来调整。另外，这里的调整区域117的宽度，是沿着栅极层13和体层115的排列方向的长度。
(第2实施方式)
对第2实施方式进行说明。本实施方式相对于第1实施方式而言，没有形成调整区域117。其他与第1实施方式是同样的，所以这里省略说明。
在本实施方式中，如图13所示，在沟道层114中没有形成调整区域117。并且，栅极层13具有构成沟道层114侧的侧面的外缘部13a、和比外缘部13a靠内缘侧的内缘部13b。同样，体层115具有构成沟道层114侧的侧面的外缘部115a、和比外缘部115a靠内缘侧的内缘部115b。即，栅极层13及体层115被做成具有相互对置的外缘部13a、115a和位于外缘部13a、115a之间的内缘部13b、115b的结构。
并且，栅极层13的外缘部13a和内缘部13b被设为不同的杂质浓度。同样，体层115的外缘部115a和内缘部115b被设为不同的杂质浓度。另外，在本实施方式中，栅极层13的外缘部13a和体层115的外缘部115a被设为相同的杂质浓度。此外，栅极层13的内缘部13b和体层115的内缘部115b被设为相同的杂质浓度。
并且，如图14所示，外缘部13a、115a的杂质浓度越高，JFET10的栅极电压依存性ΔVgJ越低。因此，在本实施方式中，对栅极层13的外缘部13a及体层115的外缘部115a的杂质浓度进行调整，以使得成为上述数式23以上且上述数式24以下的栅极电压依存性ΔVgJ。另外，图14是将内缘部13b、115b的杂质浓度设为1.0×1018cm－3的情况下的模拟结果。
如以上说明的那样，也可以通过对栅极层13的外缘部13a及体层115的外缘部115a的杂质浓度进行调整，从而使得JFET10的栅极电压依存性ΔVgJ成为上述数式23以上且数式24以下。通过这样的结构，也能够得到与上述第1实施方式同样的效果。
(第2实施方式的变形例)
对上述第2实施方式的变形例进行说明。在上述第2实施方式中，说明了在栅极层13及体层115中通过使外缘部13a、115a和内缘部13b、115b的杂质浓度不同来调整JFET10的栅极电压依存性ΔVgJ的例子。但是，在上述第2实施方式中，只要JFET10的栅极电压依存性ΔVgJ为上述数式23以上且数式24以下，也可以做成以下这样的结构。例如，也可以使得仅栅极层13的外缘部13a和内缘部13b的杂质浓度不同，使得体层115的外缘部115a和内缘部115b成为相同的杂质浓度。此外，在上述第2实施方式中，只要JFET10的栅极电压依存性ΔVgJ为上述数式23以上且数式24以下，栅极层13的外缘部13a和体层115的外缘部115a也可以杂质浓度不同。
(第3实施方式)
对第3实施方式进行说明。本实施方式相对于第1实施方式而言规定了MOSFET20的电容比。其他与第1实施方式是同样的，所以这里省略说明。
本实施方式的半导体装置的结构与上述第1实施方式是同样的。另外，本实施方式的JFET10既可以形成有调整区域117也可以不形成调整区域117。
这里，在上述第1实施方式中，对调整JFET10的栅极电压依存性ΔVgJ来减小开关损耗的结构进行了说明，但也可以如以下这样减小开关损耗。具体而言，如果设MOSFET20的镜像电容Cgd相对于输入电容Ciss的比为电容比Cgd/Ciss，则在将JFET10与MOSFET20级联连接的上述半导体装置中，以下的关系成立。即，电容比Cgd/Ciss和JFET10的栅极电压依存性ΔVgJ为反比例的关系。因此，上述数式23也由下述数式26表示。上述数式24也由下述数式27表示。上述数式25也由下述数式28表示。另外，通常，JFET的寄生栅极电阻RJ较小，所以如上述数式7所示那样，由栅极电阻RJ规定的ΔtmJ可以忽视。即，可以将ΔtmJ设为0。
[数式26]
×1＝Cgd/Ciss＝Id/g/ΔVgJ
[数式27]
×2＝Cgd/Ciss＝(Vd/ΔVgJ)×dI/dt/(g×dV/dt)-ΔtmJ/ΔVgJ/(g×dI/dt)
[数式28]
×3＝Cgd/Ciss＝(1/g/ΔVgJ)×{(Id×Vd)/(dI/dt/dV/dt)×{1-(ΔtmJ/Vd)×dV/dt}1/2
因而，本实施方式的半导体装置构成为，MOSFET20的电容比Cgd/Ciss为上述数式26以上且上述数式27以下。该情况下，半导体装置通过构成为使电容比Cgd/Ciss满足上述数式28，能够使总开关损耗Esum最小。
另外，MOSFET20的电容比Cgd/Ciss例如通过调整接触层217的深度而容易地变更。此外，MOSFET20的电容比Cgd/Ciss例如还通过在栅极电极23与漏极电极22之间形成p型的杂质层而能够容易地变更。
如以上说明的那样，也可以通过调整MOSFET20的电容比Cgd/Ciss来减小开关损耗。
(第4实施方式)
对第4实施方式进行说明。本实施方式使用第1实施方式的半导体装置构成了逆变器。其他与第1实施方式是同样的，所以这里省略说明。
在本实施方式中，如图15所示，将调整电阻41做成以下结构。即，调整电阻41具有串联连接了第1二极管411a和第1电阻411b的第1电阻电路411、以及串联连接了第2二极管412a和第2电阻412b的第2电阻电路412。并且，第1电阻电路411及第2电阻电路412并联地配置，以使得将第1二极管411a的阴极及第2二极管412a的阳极分别与MOSFET20的栅极电极23连接。
在本实施方式中，MOSFET20的栅极电极23和栅极驱动电路50经由这样的调整电阻41而连接。因此，MOSFET20在进行开关导通动作的情况和进行开关断开动作的情况下，通过不同的电阻电路来调整开关速度。
具体而言，MOSFET20的栅极电极23在进行开关导通动作时成为经由第1电阻电路411而与栅极驱动电路50连接的状态。即，第1电阻电路411作为MOSFET20的开关导通动作用的速度调整电阻发挥功能。此外，MOSFET20的栅极电极23在进行开关断开动作时成为经由第2电阻电路412而与栅极驱动电路50连接的状态。即，第2电阻电路412作为MOSFET20的开关断开动作用的速度调整电阻发挥功能。因此，通过调整各电阻电路411、412的电阻值，能够适当调整MOSFET20的开关速度。
以上是本实施方式的半导体装置的结构。这样的半导体装置例如如图16所示，被用作将三相马达驱动的逆变器的开关元件。
即，如图16所示，逆变器成为以下结构：在被施加来自电源600的电压Vcc的电源线610与接地的地线620之间具备U相、V相、W相的3电路。并且，各层分别与栅极驱动电路50及三相马达M连接。以下，参照图17对U层的详细结构进行说明。另外，V层、W层的详细结构与U层相同，所以省略。
如图17所示，U层为具备两个图15所示的半导体装置的结构。并且，U层的上侧臂UA中的JFET10的漏极电极12经由第1端子31而与电源线610连接。U层的下侧臂LA中的MOSFET20的源极电极21经由第2端子32而与地线620连接。此外，上侧臂UA中的MOSFET20的源极电极21与下侧臂LA中的JFET10的漏极电极12电连接。即，上侧臂UA的第2端子32与下侧臂LA的第1端子31电连接。并且，上侧臂UA的第2端子32和下侧臂LA的第1端子31之间与三相马达M连接。此外，关于上侧臂UA及下侧臂LA中的各MOSFET20，各个MOSFET20中的栅极电极23与栅极驱动电路50连接。
这样，还能够将本实施方式的半导体装置用作逆变器的开关元件。
(其他实施方式)
对本发明依据实施方式进行了记述，但应理解的是本发明并不限定于该实施方式及构造。本发明也包含各种各样的变形例及等价范围内的变形。除此以外，各种各样的组合及形态、进而在它们中仅包含一要素、其以上或其以下的其他组合及形态也落入在本发明的范畴及思想范围中。
例如，在上述各实施方式中，也可以将第1导电型设为P型，将第2导电型设为N型。即，也可以将JFET10及MOSFET20做成P沟道型。
此外，在上述各实施方式中，也可以将栅极层13及体层115设为相同的深度。此外，使体层115的底部侧相比于栅极层13的底部侧而言电场强度变高的结构能够适当变更。例如，也可以通过将体层115的底部做成尖细形状、或使体层115的宽度比栅极层13的宽度窄，做成体层115的底部侧相比于栅极层13的底部侧而言电场强度容易变高的结构。
并且，在上述各实施方式中，JFET10也可以使用硅衬底构成，也可以使用其他化合物半导体衬底等构成。同样，MOSFET20也可以使用SiC衬底构成，也可以使用其他化合物半导体衬底构成。
进而，在上述各实施方式中，MOSFET20也可以不是沟槽栅型，而是做成将栅极电极23配置在半导体衬底210的一面210a上的平面栅极型。
并且，也可以将上述各实施方式适当组合。例如，也可以将上述第1实施方式与上述第2实施方式组合，做成形成调整区域117并且栅极层13及体层115具有外缘部13a、115a的结构。此外，也可以将上述第1、第2实施方式与第3实施方式组合，调整栅极电压依存性ΔVgJ并且调整MOSFET20的电容比Cgd/Ciss。并且，也可以将组合了上述各实施方式的形态彼此进一步组合。

Claims (9)

1.一种半导体装置，级联连接了结型FET(10)和MOSFET(20)，其特征在于，
具备：
上述结型FET，具有源极电极(11)、漏极电极(12)、栅极电极(13)；以及
上述MOSFET，具有源极电极(21)、漏极电极(22)、栅极电极(23)；
上述结型FET的源极电极与上述MOSFET的漏极电极被电连接从而上述结型FET和上述MOSFET被级联连接；
将上述结型FET的栅极电压的漏极电压依存性设为栅极电压依存性而设为ΔVgJ，将电流变化率设为dI/dt，将电压变化率设为dV/dt，将电源电压设为Vd，将动作电流设为Id，将上述结型FET的延迟时间设为ΔtmJ，将上述MOSFET的镜像电容设为Cgd，将上述MOSFET的输入电容设为Ciss，将上述MOSFET的栅极镜像电位设为Vm，将上述MOSFET的栅极阈值设为Vth，将Id/(Vm-Vth)设为g，则上述栅极电压依存性被设为下述数式1以上且数式2以下
[数式1]
ΔVgJ＝(Vd×Id-ΔtmJ×Id×dV/dt)/g/(Cgd/Ciss)/(Vd-ΔtmJ×dV/dt)
[数式2]
ΔVgJ＝Vd/g/(Cgd/Ciss)×{(dI/dt/dV/dt)-ΔtmJ/g/(Cgd/Ciss)×dI/dt。
2.如权利要求1所述的半导体装置，其特征在于，
上述栅极电压依存性被设为下述数式5
[数式5]
ΔVgJ＝1/g/(Cgd/Ciss)×{(Vd×Id×dI/dt/dV//dt)×(1-(ΔtmJ/Vd)×dV/dt)}1/2。
3.如权利要求1或2所述的半导体装置，其特征在于，
上述结型FET具有：
第1导电型的漂移层(113)；
第1导电型的沟道层(114)，配置在上述漂移层上；
第1导电型的源极层(116)，形成在上述沟道层的表层部，杂质浓度比上述沟道层高；
作为上述栅极电极的第2导电型的栅极层，在上述沟道层中形成至比上述源极层深的位置；
第2导电型的体层(115)，在上述沟道层中形成至比上述源极层深的位置，与上述栅极层分离；
第1导电型的漏极层(111)，隔着上述漂移层而配置在与上述源极层相反的一侧；
上述源极电极，与上述源极层及上述体层电连接；以及
上述漏极电极，与上述漏极层电连接。
4.如权利要求3所述的半导体装置，其特征在于，
在上述沟道层中，在位于上述栅极层与上述体层之间的部分，形成有第1导电型的调整区域(117)；
上述调整区域构成为，满足关于上述栅极电压依存性的数式。
5.如权利要求4所述的半导体装置，其特征在于，
上述调整区域的剂量被调整，以满足关于上述栅极电压依存性的数式。
6.如权利要求4所述的半导体装置，其特征在于，
上述调整区域的沿着上述漂移层和上述沟道层的层叠方向的长度(L)被调整，以满足关于上述栅极电压依存性的数式。
7.如权利要求3～6中任一项所述的半导体装置，其特征在于，
上述栅极层及上述体层的至少一方的、构成与上述沟道层相接的侧面的外缘部(13a、115b)的杂质浓度和比上述外缘部靠内缘侧的内缘部(13b、115b)的杂质浓度不同，以满足关于上述栅极电压依存性的数式。
8.一种半导体装置，级联连接了结型FET(10)和MOSFET(20)，其特征在于，
具备：
上述结型FET，具有源极电极(11)、漏极电极(12)、栅极电极(13)；以及
上述MOSFET，具有源极电极(21)、漏极电极(22)、栅极电极(23)；
上述结型FET的源极电极与上述MOSFET的漏极电极被电连接从而上述结型FET和上述MOSFET被级联连接；
将上述结型FET的栅极电压的漏极电压依存性设为栅极电压依存性而设为ΔVgJ，将电流变化率设为dI/dt，将电压变化率设为dV/dt，将电源电压设为Vd，将动作电流设为Id，将上述结型FET的延迟时间设为ΔtmJ，将上述MOSFET的镜像电容设为Cgd，将上述MOSFET的输入电容设为Ciss，将上述MOSFET的栅极镜像电位设为Vm，将上述MOSFET的栅极阈值设为Vth，将Id/(Vm-Vth)设为g，将上述镜像电容相对于上述输入电容的电容比设为Cgd/Ciss，则上述电容比被设为下述数式3以上且数式4以下
[数式3]
Cgd/Ciss＝Id/g/ΔVgJ
[数式4]
Cgd/Ciss＝(Vd/ΔVgJ)×dI/dt/(g×dV/dt)-ΔtmJ/ΔVgJ/(g×dI/dt)。
9.如权利要求8所述的半导体装置，其特征在于，
上述电容比被设为下述数式6
[数式6]
Cgd/Ciss＝(1/g/ΔVgJ)×{(Id×Vd)/(dI/dt/dV/dt)×{1-(ΔtmJ/Vd)×dV/dt}1/2。
CN202180029686.5A 2020-04-22 2021-04-20 半导体装置 Pending CN115461875A (zh)

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