CN115411018A - 优化寄生参数的功率半导体器件封装结构 - Google Patents

优化寄生参数的功率半导体器件封装结构 Download PDF

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Publication number
CN115411018A
CN115411018A CN202210365853.XA CN202210365853A CN115411018A CN 115411018 A CN115411018 A CN 115411018A CN 202210365853 A CN202210365853 A CN 202210365853A CN 115411018 A CN115411018 A CN 115411018A
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metal wiring
power
kelvin
semiconductor device
semiconductor chip
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CN202210365853.XA
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CN115411018B (zh
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龚伟
朱春林
姜克
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Anshi Semiconductor Technology Shanghai Co ltd
Nexperia BV
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Anshi Semiconductor Technology Shanghai Co ltd
Nexperia BV
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Priority to CN202210365853.XA priority Critical patent/CN115411018B/zh
Publication of CN115411018A publication Critical patent/CN115411018A/zh
Priority to US18/296,433 priority patent/US20230326907A1/en
Priority to EP23166906.0A priority patent/EP4258347A3/en
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

本发明公开了一种功率半导体器件封装结构，包括：衬板，位于衬板上的两个或多个半导体芯片，所述每个半导体芯片包括第一功率开关电极，第二功率开关电极以及栅极，所述衬板上还布置有栅极控制金属布线，第一功率端子以及第二功率端子，所述栅极控制金属布线通过绑定部件连接到所述每个半导体芯片上，其中，连接第一半导体芯片与所述栅极控制金属布线的绑定部件被夹在所述第一半导体芯片和与其相邻的第二半导体芯片的第二功率开关电极与所述衬板的第二功率端子连接形成的线路之间。

Description

优化寄生参数的功率半导体器件封装结构
技术领域
本发明涉及功率半导体器件封装结构。具体地，本发明涉及一种优化寄生参数的功率半导体器件封装结构。
背景技术
电动汽车逆变器功率模块或智能家电功率模块中对于电力控制的需求大幅增加。功率半导体器件MOSFET(Metal Oxide Semiconductor Field Effect Transistor,金属氧化物半导体场效应晶体管),HEMT(High Electron Mobility Transistor，高电子迁移率晶体管),IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管芯片)等是工业控制及自动化领域的核心元器件，其通过信号指令来调节电路中的电压、电流等以实现精准调控的目的，保障电子产品、电力设备正常运行，同时降低电压损耗，使设备节能高效。
将多个半导体芯片并联，可以使半导体器件的功率容量得以进一步扩展。但是，现有技术中对于并联功率半导体芯片具有不同的控制回路长度，导致不同的电阻抗(或寄生参数)，从而容易导致并联芯片上的开关不同步或电流不均衡的问题。其次，现有技术中的金属布线的位置占据了半导体衬板的大部分空间，使得半导体衬板的空间利用率不够高。此外，对于半导体芯片来说，越来越多地使用高频信号。然而，高频信号经常伴随着信号完整性和电磁波屏蔽的问题，现有技术中的抗电磁干扰(Electromagnetic Interference，EMI)特性需要提高。
图1公开了用于电力电子设备的现有技术的封装结构的俯视图。如图1所示，两个半导体芯片上的两个栅极32分别通过两条引线34与栅极控制金属布线24相连，另外，其中一条引线34与栅极端子20相连。栅极控制金属布线24位于半导体衬板下部并占据了几乎所有下部位置。图1的封装并联的芯片的控制回路具有不同的电阻抗。另外，栅极控制金属布线24的布置浪费了衬板上的空间。
图2公开了另一个现有技术中的封装结构的俯视图。如图2所示，两个半导体芯片54上的两个栅极60分别通过两个引线68与栅极控制金属布线50相连，两个开尔文电极62分别通过两个引线68与开尔文金属布线52相连，栅极控制金属布线50和开尔文金属布线52被分别设置为具有至少一个不平行于电源基板38边缘的边缘。此现有技术封装结构抗EMI特性可能不足并联芯片上的开关不同步或电流不均衡。另外，栅极控制金属布线50和开尔文金属布线52的如此布置使得衬板上的空间利用率较低。
发明内容
本发明公开了一种功率半导体器件封装结构，包括：衬板，位于所述衬板上的两个或多个半导体芯片，所述每个半导体芯片包括第一功率开关电极，第二功率开关电极以及栅极，所述衬板上还布置有栅极控制金属布线，第一功率端子以及第二功率端子，所述栅极控制金属布线通过绑定部件连接到所述每个半导体芯片上，其中，连接第一半导体芯片与所述栅极控制金属布线的绑定部件被夹在所述第一半导体芯片和与其相邻的第二半导体芯片的第二功率开关电极与所述衬板的第二功率端子连接形成的线路之间。
作为本发明的一个实施例，所述绑定部件是绑定线。
作为本发明的一个实施例，所述绑定部件是铜夹片。
作为本发明的一个实施例，所述衬板上布置有开尔文金属布线，并且连接第一半导体芯片与所述栅极控制金属布线和所述开尔文金属布线的绑定部件被夹在所述第一半导体芯片和与其相邻的第二半导体芯片的第二功率开关电极与所述衬板的第二功率端子连接形成的线路之间。
作为本发明的一个实施例，所述每个半导体芯片还包括开尔文电极，所述每个半导体芯片的栅极和开尔文电极分别连接至所述栅极控制金属布线和所述开尔文金属布线。
作为本发明的一个实施例，所述开尔文金属布线通过绑定部件与所述每个半导体芯片的第二功率开关电极连接。
作为本发明的一个实施例，所述栅极控制金属布线被所述开尔文金属布线包围设置或所述开尔文控制金属布线被所述栅极金属布线包围设置。
作为本发明的一个实施例，所述栅极控制金属布线位于所述半导体芯片与所述开尔文金属布线之间或所述开尔文金属布线位于所述半导体芯片与所述栅极控制金属布线之间。
作为本发明的一个实施例，所述衬板上布置有开尔文金属端子，其与所述第二功率端子为一个整体部件。
作为本发明的一个实施例，所述衬板上还布置有温度传感器，所述温度传感器与所述半导体芯片位于同一层。
作为本发明的一个实施例，当所述衬板上仅包括两个半导体芯片时，所述两个半导体芯片的栅极分别布置在所述两个半导体芯片的相邻两边的边缘处。
作为本发明的一个实施例，所述每个半导体芯片的第二功率开关电极与所述衬板的第二功率端子的连接方式包括绑定线连接或者金属接触。
作为本发明的一个实施例，所述第一功率开关电极为漏极或接收极，所述第二功率开关电极为源极或发射极。
作为本发明的一个实施例，所述第一功率端子为漏极端子，所述第二功率端子为源极端子。
本发明还公开了一种功率半导体器件封装结构，包括：衬板，位于所述衬板上的两个或多个半导体芯片，所述每个半导体芯片包括第一功率开关电极，第二功率开关电极以及栅极，所述衬板上还布置有栅极控制金属布线，开尔文金属布线，第一功率端子以及第二功率端子，其中，所述栅极控制金属布线被所述开尔文金属布线包围设置或所述开尔文控制金属布线被所述栅极金属布线包围设置。
作为本发明的一个实施例，所述衬板上还布置有温度传感器，所述温度传感器与所述半导体芯片位于同一层。
作为本发明的一个实施例，所述半导体芯片包括IGBT芯片、SiC芯片或GaN芯片。
附图说明
图1示出了电力电子设备的一个现有技术的封装结构的俯视图；
图2示出了电力电子设备的另一个现有技术的封装结构的俯视图；
图3示出了本发明的一个实施例的功率半导体器件封装结构的俯视图；
图4示出了本发明的另一个实施例的功率半导体器件封装结构的俯视图；
图5示出了本发明的另一个实施例的功率半导体器件封装结构的俯视图；
图6示出了本发明的另一个实施例的功率半导体器件封装结构的俯视图；
图7示出了本发明的另一个实施例的功率半导体器件封装结构的俯视图；
图8示出了本发明的另一个实施例的功率半导体器件封装结构的俯视图；
图9示出了本发明的另一个实施例的功率半导体器件封装结构的俯视图；
图10示出了本发明的另一个实施例的功率半导体器件封装结构的俯视图；
图11示出了本发明的另一个实施例的功率半导体器件封装结构的俯视图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，作为没有限定性的例子，下面结合附图对本发明提供的优化寄生参数的功率半导体器件封装结构进行详细描述。同时应当注意，为了在此说明这些示例性实施例，所述视图将示出本发明的示例性实施例的方法和器件的一般特征。然而，这些视图不是成比例的并且可能不是精确地反应任一给定实施例的特征，并且不应解释为界定或者限定本发明范围内示例性实施例的数值范围或者特性。
图3示出了本发明的一个功率半导体器件封装结构的俯视图，如图3所示，所述功率半导体器件封装结构包括：衬板1，位于衬板1上的两个半导体芯片2，每一个半导体芯片2包括第一功率开关电极7，第二功率开关电极8，栅极9和开尔文电极10；衬板1还包括功率开关金属布线18，栅极控制金属布线3和开尔文金属布线4，它们中的每一个通过绝缘材料的彼此隔开，使得功率开关金属布线18，栅极控制金属布线3和开尔文金属布线4彼此电绝缘。图3示出了两个半导体芯片2位于衬板1的功率开关金属布线18上，使得在每个半导体芯片2上的第一功率开关电极7电耦合到功率开关金属布线18上。衬板1还包括第一功率端子5和第二功率端子6，第一功率端子通过直接接触附接到功率开关金属布线18上，进而电耦合至第一功率开关电极7上，第二功率端子6通过直接接触附接到每一个半导体芯片2的第二功率开关电极8上；直接接触附接可以使用烧结金属(比如铜金属，银金属)或焊接等来完成。栅极控制金属布线3和开尔文金属布线4通过绑定部件分别连接到每个半导体芯片2的栅极9和开尔文电极10上。绑定部件可以为一个或多个绑定线或者一个或多个铜夹片(CopperClip)(附图未示出)。作为一个示例，图3示出的栅极控制金属布线3和开尔文金属布线4通过一个或多个绑定线11(一般是一个)、12连接到两个半导体芯片2中的每一个的栅极9和开尔文电极10上；每个半导体芯片2连接到栅极控制金属布线3和开尔文金属布线4的绑定部件被夹在两个半导体芯片2的第二功率开关电极8与第二个功率端子6的铜片之间；作为一个示例，图3示出每个半导体芯片2连接到栅极控制金属布线3和开尔文金属布线4的绑定线11、12被夹在两个半导体芯片2的第二功率开关电极8与第二个功率端子6的铜片之间。
当绑定部件采用铜夹片绑定时，所述铜夹片的两端对应放置在半导体芯片的栅极和栅极控制金属布线以及半导体芯片的开尔文电极和开尔文金属布线的相应位置处，并通过高温焊接或烧结，将芯片表面金属以及金属布线能够与焊接或烧结材料有效粘结。采用铜夹片绑定方式，可达到将半导体芯片与相应金属布线绑定连接的目的，同时还减少了连线上浮和焊点断裂的问题，提高产品的可靠性。
下文的实施例作为示例示出了绑定部件采用绑定线进行连接的情况。应当知晓的是，绑定线可以采用铜夹片进行替代。
图3示出的示例中，两个半导体芯片2的两个栅极9位于两个半导体芯片2的相邻两边的边缘处。
如图3所示，第二功率端子6的框结构将两个半导体芯片2上的两个第二功率开关电极8与第二功率端子6分别地耦合，形成了两条线路。每个半导体芯片2连接到栅极控制金属布线3和开尔文金属布线4的绑定线11、12被夹在每个半导体芯片2的第二功率开关电极8与第二功率端子6所形成的两条线路之间，使得两个并联半导体芯片具有基本相同的控制回路长度，使得并联芯片的电阻抗基本一致，从而进一步使得并联芯片上的开关/电流均衡。连接半导体芯片2至栅极控制金属布线3的绑定线11、12的长度可以根据电路需要设计成适合的长度。应当知晓的是，当绑定部件采用一个或多个夹片绑定时，所述夹片的尺寸也可根据电路需要设计成适合的尺寸。
上面“控制回路长度”是指，栅极信号端子14通过绑定部件连接至栅极控制金属布线3，栅极控制金属布线3通过绑定部件连接至栅极9，栅极9连接开尔文电极10，开尔文电极10通过绑定部件连接至开尔文金属布线4，开尔文金属布线4通过绑定部件连接至开尔文端子15的回路长度。
由于开尔文端子14和栅极端子15位于衬底的同侧，两个半导体芯片的栅极9和开尔文电极10距离较近可以使得两个半导体芯片在控制回路中的走线长度基本一致。
应当知晓的是，半导体芯片2可以是IGBT芯片、SiC芯片或GaN芯片；半导体芯片2的形状可以是方形或者矩形，但并不限定于此。
其中，第一功率开关电极7为漏极或集电极，第二功率开关电极8为源极或发射极，第一功率端子5为漏极或集电极端子，所述第二功率端子6为源极或发射极端子。
图3示出的开尔文金属布线4位于所述半导体芯片2与所述栅极控制金属布线3之间，开尔文金属布线4和栅极控制金属布线3基本平行，且开尔文金属布线4和栅极控制金属布线3与衬板1上的半导体芯片2基本平行。
图4示出了本发明的另一个功率半导体器件封装结构的俯视图，如图4所示，所述栅极控制金属布线3被所述开尔文金属布线4包围设置，其中，栅极控制金属布线3与开尔文金属布线4基本平行，且开尔文金属布线4和栅极控制金属布线3与衬板1上的半导体芯片2基本平行，开尔文金属布线4的这种包围布置可以使栅极控制金属布线3上的电磁干扰更少。尽管图4未示出，开尔文金属布线4也可以被栅极控制金属布线3包围布置，栅极控制金属布线3的这种包围布置可以使开尔文金属布线4上的电磁干扰更少。
当然并不局限于以上布置，所述栅极控制金属布线3也可以位于所述半导体芯片2与所述开尔文金属布线4之间(如图9所示)。如图9所示的布置方式，开尔文金属布线4和栅极控制金属布线3基本平行，且开尔文金属布线4和栅极控制金属布线3与衬板1上的半导体芯片2基本平行。
图5示出了本发明的另一个功率半导体器件封装结构的俯视图，如图5所示，功率半导体器件封装的栅极控制金属布线3被所述开尔文金属布线4包围设置，这种布局在衬板1上节省了空间，在衬板1的剩余部分区域，还布置有温度传感器13。由于芯片并联功率模块电流可达到或超过1200A，最高工作温度可达到250℃。因此，在衬板1上设置温度传感器13，可以监测器件的温度变化，使得器件能够快速散热，提高器件的使用寿命。温度传感器13可采用焊接或烧结工艺连接至衬板上，所述温度传感器与所述半导体芯片位于同一层，温度传感器13的两极通过绑定线连接至温度传感器的两个信号端子16。
可以采用NTC温度传感器或PTC温度传感器，热敏电阻器温度传感器的典型特点是对温度敏感，不同的温度下表现出不同的电阻值。正温度系数热敏电阻器在温度越高时电阻值越大，负温度系数热敏电阻器在温度越高时电阻值越低。利用热敏电阻在一定的测量功率下，电阻值产生变化这一特性，可将热敏电阻器温度传感器通过测量其电阻值来确定相应的温度，从而达到检测和控制温度的目的。
应当注意的是，温度传感器13并不仅仅布置于栅极控制金属布线3被所述开尔文金属布线4包围的衬板1上，当栅极控制金属布线3位于所述半导体芯片2与所述开尔文金属布线4之间，或开尔文金属布线4位于所述半导体芯片2与所述栅极控制金属布线3之间时，也可以在衬板1的剩余部分区域布置温度传感器13。
图6示出了本发明的另一个实施例的功率半导体器件封装结构的俯视图，如图6所示，该半导体器件封装具有三个功率半导体芯片2，从左至右为芯片A，芯片B，芯片C(图中未示出)，芯片A和芯片B连接至栅极控制金属布线3和开尔文金属布线4的绑定部件，例如，绑定线11、12，被夹在芯片A和芯片B的第二功率开关电极8与第二功率端子6所形成的线路之间，芯片A和芯片B的两个栅极9位于芯片A和芯片B的相邻两边的边缘处。芯片C连接至栅极控制金属布线3和开尔文金属布线4的绑定部件，例如，绑定线11、12，被夹在芯片B与芯片C的第二功率开关电极8与第二功率端子6所形成的线路之间。
图7示出了本发明的另一个实施例的功率半导体器件封装结构的俯视图，其中，第二功率端子6并不是直接附接到每个半导体芯片2的第二功率开关电极8上，而是通过绑定线与第二功率开关电极8连接。每个半导体芯片2连接到栅极控制金属布线3和开尔文金属布线4的绑定部件，例如绑定线11、12，被夹在两个半导体芯片2的第二功率开关电极8与第二个功率端子6的绑定线之间；且两个半导体芯片2的两个栅极9位于两个半导体芯片2的相邻两边的边缘处。
图8示出了本发明的另一个实施例的功率半导体器件封装结构的俯视图，如图8所示，衬板1上并未布置开尔文金属布线4，而是将第二功率端子6和开尔文端子15设计为一个整体，采用这种新型封装模式，简化了结构，降低了制造成本，进一步提高了器件性能。
在图8中，每个半导体芯片2连接到栅极控制金属布线3的绑定部件，例如绑定线11，被夹在两个半导体芯片2的第二功率开关电极8与第二个功率端子6的铜片之间；栅极9布置在两个半导体芯片2的相邻两边的边缘。应当注意的是，图8示出的半导体芯片2上并未布置开尔文电极10，因此，开尔文端子15与半导体芯片2上的第二功率开关电极8直接接触。
图9示出了本发明的另一个实施例的功率半导体器件封装结构的俯视图，其中，栅极控制金属布线3位于所述半导体芯片2与所述开尔文金属布线4之间。每个半导体芯片2连接到栅极控制金属布线3和开尔文金属布线4的绑定部件，例如绑定线11，被夹在两个半导体芯片2的第二功率开关电极8与第二个功率端子6的铜片之间；栅极9布置在半导体芯片2的相邻两边的边缘。在衬板1的剩余部分区域，还布置有温度传感器13。
本发明的一种优化寄生参数的功率半导体器件封装结构，还包括采用模塑封装或塑料外壳17封装。
图10示出了本发明的另一个功率半导体器件封装结构的俯视图，如图10所示，所述功率半导体器件封装结构包括：衬板1，位于衬板1上的两个半导体芯片2，每一个半导体芯片2包括第一功率开关电极7，第二功率开关电极8，栅极9和开尔文电极10；衬板1上有栅极控制金属布线3和开尔文金属布线4；第一功率端子5和第二功率端子6。其中，栅极控制金属布线3被开尔文金属布线4包围设置。开尔文金属布线4的这种包围布置可以使栅极控制金属布线3上的电磁干扰更少。
图11示出了本发明的另一个功率半导体器件封装结构的俯视图，与图10不同，图11所示的开尔文控制金属布线4被所述栅极金属布线3包围设置。栅极金属布线3的这种包围布置可以使开尔文控制金属布线4上的电磁干扰更少。
在图10和图11所示的功率半导体器件封装结构中，每个半导体芯片2连接到栅极控制金属布线3和开尔文金属布线4的绑定部件，例如绑定线11、12，并未被夹在每个半导体芯片2的第二功率开关电极8与第二功率端子6所形成的两条线路之间。两个半导体芯片2的两个栅极9并不位于两个半导体芯片2的相邻两边的边缘处。
在图10和图11所示的功率半导体器件封装结构中，所述衬板上的剩余部分区域可以布置有温度传感器(图10和图11中并未示出)，所述温度传感器与所述半导体芯片位于同一层。在衬板上设置温度传感器，可以监测器件的温度变化，使得器件能够快速散热，提高器件的使用寿命。
为了验证本发明的改进，通过建立3D模型，将现有技术中的半导体器件封装结构和采用本发明的半导体器件封装结构的寄生参数进行比较。控制回路的寄生电感和寄生电阻由Ansys Q3D Extractor提取，如下表1所示，其中，芯片1和芯片2表示每个3D模型中的左芯片(left-hand die)和右芯片(right-hand die)。现有技术1中功率回路和控制回路是耦合的，而在其他三个模块中，功率回路和控制回路并不是耦合的。从这个仿真中可以看出：与现有技术1或现有技术2相比，本发明方案1和本发明方案2在两个半导体芯片之间具有更好的寄生参数匹配。本发明方案2的寄生参数低于本发明方案1，低寄生参数可大幅增加开关速率，同时可抑制传导EMI。
Figure BDA0003586985160000111
表1现有技术和本发明的半导体器件封装结构的寄生参数的比较
本发明所提供的功率半导体器件封装结构，对于并联的功率半导体芯片来说具有近似的控制回路长度，带来近似的寄生参数/电阻抗，从而避免了并联芯片的开关/电流不均衡的问题。此外，由于栅极控制金属布线被开尔文金属布线包围布置或者开尔文金属布线被栅极控制金属布线包围布置，可以使得本发明具有更好的抗电磁干扰特性。此外，本发明的布局在衬板上可以进一步节省空间，使得衬板上可以额外布置温度传感器，以及时监控功率半导体器件的温度，提高器件的使用寿命。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换，例如从属权利要求的特征可以根据需要自由替换和/或组合；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。
参考标号列表：
部件 标号
衬板 1
半导体芯片 2
栅极控制金属布线 3
开尔文金属布线 4
第一功率端子 5
第二功率端子 6
第一功率开关电极 7
第二功率开关电极 8
栅极 9
开尔文电极 10
绑定线 11、12
温度传感器 13
栅极信号端子 14
开尔文信号端子 15
温度传感器信号端子 16
外壳 17
功率开关金属布线 18

Claims (18)

1.一种功率半导体器件封装结构，包括：
衬板，
位于所述衬板上的两个或多个半导体芯片，所述每个半导体芯片包括第一功率开关电极，第二功率开关电极以及栅极，
所述衬板上还布置有栅极控制金属布线，第一功率端子以及第二功率端子，
所述栅极控制金属布线通过绑定部件连接到所述每个半导体芯片上，其中，连接第一半导体芯片与所述栅极控制金属布线的绑定部件被夹在所述第一半导体芯片和与其相邻的第二半导体芯片的第二功率开关电极与所述衬板的第二功率端子连接形成的线路之间。
2.如权利要求1所述的功率半导体器件封装结构，其中，所述绑定部件是绑定线。
3.如权利要求1所述的功率半导体器件封装结构，其中，所述绑定部件是铜夹片。
4.如权利要求1所述的半导体器件封装结构，其中，所述衬板上布置有开尔文金属布线，并且连接第一半导体芯片与所述栅极控制金属布线和所述开尔文金属布线的绑定部件被夹在所述第一半导体芯片和与其相邻的第二半导体芯片的第二功率开关电极与所述衬板的第二功率端子连接形成的线路之间。
5.如权利要求4所述的半导体器件封装结构，其中，所述每个半导体芯片还包括开尔文电极，所述每个半导体芯片的栅极和开尔文电极分别连接至所述栅极控制金属布线和所述开尔文金属布线。
6.如权利要求4所述的半导体器件封装结构，其中，所述开尔文金属布线通过绑定部件与所述每个半导体芯片的第二功率开关电极连接。
7.如权利要求2至6任一项所述的半导体器件封装结构，其中，所述栅极控制金属布线被所述开尔文金属布线包围设置或所述开尔文控制金属布线被所述栅极金属布线包围设置。
8.如权利要求2至6任一项所述的半导体器件封装结构，其中，所述栅极控制金属布线位于所述半导体芯片与所述开尔文金属布线之间或所述开尔文金属布线位于所述半导体芯片与所述栅极控制金属布线之间。
9.如权利要求1所述的半导体器件封装结构，其中，所述衬板上布置有开尔文金属端子，其与所述第二功率端子为一个整体部件。
10.如权利要求7所述的半导体器件封装结构，其中，所述衬板上还布置有温度传感器，所述温度传感器与所述半导体芯片位于同一层。
11.如权利要求8所述的半导体器件封装结构，其中，所述衬板上还布置有温度传感器，所述温度传感器与所述半导体芯片位于同一层。
12.如权利要求1至6任一项所述的半导体器件封装结构，其中，当所述衬板上仅包括两个半导体芯片时，所述两个半导体芯片的栅极分别布置在所述两个半导体芯片的相邻两边的边缘处。
13.如权利要求1至6任一项所述的半导体器件封装结构，其中，所述每个半导体芯片的第二功率开关电极与所述衬板的第二功率端子的连接方式包括绑定线连接或者金属接触。
14.如权利要求1至6任一项所述的半导体器件，其中，所述第一功率开关电极为漏极或接收极，所述第二功率开关电极为源极或发射极。
15.如权利要求1至6任一项所述的功率半导体器件，其中，所述第一功率端子为漏极端子，所述第二功率端子为源极端子。
16.一种功率半导体器件封装结构，包括：
衬板，
位于所述衬板上的两个或多个半导体芯片，所述每个半导体芯片包括第一功率开关电极，第二功率开关电极以及栅极，
所述衬板上还布置有栅极控制金属布线，开尔文金属布线，第一功率端子以及第二功率端子，
其中，所述栅极控制金属布线被所述开尔文金属布线包围设置或所述开尔文控制金属布线被所述栅极金属布线包围设置。
17.如权利要求16所述的功率半导体器件封装结构，其中，所述衬板上还布置有温度传感器，所述温度传感器与所述半导体芯片位于同一层。
18.如权利要求1或16所述的功率半导体器件封装结构，所述半导体芯片包括IGBT芯片、SiC芯片或GaN芯片。
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