CN115188722A - Structure for packaging semiconductor chip - Google Patents
Structure for packaging semiconductor chip Download PDFInfo
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- CN115188722A CN115188722A CN202210839504.7A CN202210839504A CN115188722A CN 115188722 A CN115188722 A CN 115188722A CN 202210839504 A CN202210839504 A CN 202210839504A CN 115188722 A CN115188722 A CN 115188722A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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Abstract
The present application provides a structure for semiconductor chip packaging, comprising: a substrate; a groove is formed in the upper surface of the substrate, a chip carrier is arranged in the groove, and a semiconductor chip is arranged on the chip carrier; an insulating layer is further arranged on the upper surface of the substrate, a conducting layer is arranged on the surface of one side, away from the substrate, of the insulating layer, and the conducting layer is electrically connected with the semiconductor chip; the semiconductor chip packaging structure comprises a shell, a substrate and a plurality of insulating layers, wherein the shell covers the substrate and forms a cavity for accommodating a semiconductor chip, a chip carrying platform, an insulating layer and a conducting layer in the shell, and a plastic packaging material is filled in the cavity; and one end of the conductive terminal is connected with the conductive layer, and the other end of the conductive terminal is exposed outside the shell. According to the semiconductor chip, the number of the interfaces through which heat generated by the semiconductor chip passes in the process of outward transmission is reduced, the contact thermal resistance is reduced, and the heat dissipation effect is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor device packaging, in particular to a structure for packaging a semiconductor chip.
Background
An Insulated Gate Bipolar Transistor (IGBT) power device is a most representative product of the third revolution of the power electronic technology, and is a core component for energy conversion and transmission in the fields of industrial control and automation. Briefly, an IGBT is understood to be a "non-on/off" switch, which can invert a dc voltage into an ac power with adjustable frequency, and is mainly used for frequency conversion and inversion and other inverter circuits, and is called a "CPU" (Central Processing Unit) of a power electronic device. Because the IGBT plays an important role in electric energy conversion, the IGBT can provide higher efficiency and energy-saving effect for various high-voltage and high-current applications, and is widely applied to the fields of industrial control, variable-frequency household appliances, new energy automobiles, power transmission and distribution and the like. Due to the characteristics of high voltage, high reliability and the like of the power system, the power system has higher requirements on the parameters and performance indexes of the used IGBT.
The improvement of the performance of the IGBT power device depends on the improvement of heat dissipation, and the improvement of the heat dissipation of the IGBT power device in the current market mainly focuses on the improvement of a substrate and a packaging process. In the traditional structure, heat generated by the IGBT chip needs to pass through multiple layers of interfaces in the process of outward transmission, so that the contact thermal resistance of a device is larger, and the heat dissipation effect is greatly limited. For example, in a welding type IGBT power device, heat generated by an IGBT chip needs to be dissipated through two copper layers, a ceramic board layer, and a heat dissipation substrate; in a crimping type IGBT power device, heat generated by an IGBT chip is conducted to a shell copper layer and then dissipated after passing through a molybdenum sheet and a silver sheet in sequence, in the scheme, the heat needs to pass through multiple metal materials, and meanwhile, the contact surface of each metal material needs to ensure the electrical conductivity, so that the interface cannot be filled with conventional heat conducting media to reduce the contact resistance, and in addition, the heat conductivity of refractory metal materials such as molybdenum-based metal alloy and the like applied in the scheme is poor, and the heat dissipation capacity of the device is further influenced.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the defect of poor heat dissipation of the conventional power semiconductor due to more interfaces, and further to provide a structure for packaging a semiconductor chip.
The present invention provides a structure for semiconductor chip packaging, comprising: a substrate; a groove is formed in the upper surface of the substrate, a chip carrying platform is arranged in the groove, and a semiconductor chip is arranged on the chip carrying platform; an insulating layer is further arranged on the upper surface of the substrate, a conducting layer is arranged on the surface of one side, away from the substrate, of the insulating layer, and the conducting layer is electrically connected with the semiconductor chip; the semiconductor chip packaging structure comprises a shell, a substrate and a plurality of insulating layers, wherein the shell covers the substrate and forms a cavity for accommodating a semiconductor chip, a chip carrying platform, an insulating layer and a conducting layer in the shell, and a plastic packaging material is filled in the cavity; and one end of the conductive terminal is connected with the conductive layer, and the other end of the conductive terminal is exposed out of the shell.
Optionally, the chip carrier includes a base and a boss, the base is embedded in the groove, the boss is located on a side of the base away from the substrate, and the semiconductor chip is electrically connected to an upper surface of the boss.
Optionally, a limiting member is disposed between the chip carrier and the groove, the limiting member is clamped to the chip carrier, and the limiting member is made of a heat conductive material.
Optionally, the position-limiting element includes a first position-limiting element disposed around a sidewall of the base station and a second position-limiting element disposed at least partially on an upper surface of the base station.
Optionally, the boss is 0.5mm-2mm thick.
Optionally, the size of the upper surface of the boss is the same as the size of the semiconductor chip, or the size of the upper surface of the boss is larger than the size of the semiconductor chip.
Optionally, the substrate and the chip carrier are both made of a heat conductive material, and a difference ratio between a thermal expansion coefficient of the chip carrier and a thermal expansion coefficient of the semiconductor chip is smaller than a preset value.
Optionally, the chip carrier is made of a conductive material.
Optionally, the material of the chip carrier includes an aluminum diamond composite material.
Optionally, the substrate is made of a conductive material.
Optionally, the material of the substrate includes an aluminum-diamond composite material.
Optionally, the position-limiting member is made of a conductive material.
Optionally, the method further includes: and filling an interface layer between the bottom of the groove and the chip carrier.
Optionally, the interface layer is made of a heat conducting interface heat conducting insulating material.
Optionally, the method further includes: the substrate is provided with a detachable connecting piece, and the connecting piece is connected with the chip carrier and used for fixing the chip carrier.
Optionally, the insulating layer includes a first insulating layer and a second insulating layer, and the conductive layer includes a first conductive layer and a second conductive layer; a first conducting layer is arranged on the surface of one side, away from the substrate, of the first insulating layer, and the conducting terminals are arranged on the first conducting layer; and a second conducting layer is arranged on the surface of one side, which is far away from the substrate, of the second insulating layer, and a control electrode is arranged on the second conducting layer.
Optionally, at least one insertion groove is formed in the surface of the first conductive layer, the insertion groove is detachably connected with a conductive connecting piece, and the conductive connecting piece is electrically connected with the semiconductor chip; the surface of the second conducting layer is provided with at least one inserting groove, the inserting groove is detachably connected with the conducting connecting piece, and the conducting connecting piece is electrically connected with the semiconductor chip.
Optionally, the semiconductor chip includes an IGBT chip, a collector of the IGBT chip is connected to a surface of a side of the chip carrier, which is away from the substrate, an emitter of the IGBT chip is electrically connected to the conductive terminal after passing through the conductive connecting member and the first conductive layer in sequence, and a gate of the IGBT chip is electrically connected to the control electrode after passing through the conductive connecting member and the second conductive layer in sequence.
Optionally, the conductive connector includes a bonding wire or a bonding tape.
Optionally, at least one semiconductor chip is arranged on the chip carrier.
This application technical scheme has following advantage:
the utility model provides a be provided with the recess on the upper surface of base plate, be provided with semiconductor chip on the chip microscope carrier that sets up in the recess, through the interface quantity that the heat that reduces semiconductor chip production passes through at the in-process of outside transmission, reduced thermal contact resistance, improved the radiating effect.
Furthermore, the limiting part clamped with the chip carrier is arranged between the chip carrier and the groove, so that the chip carrier is fastened, the detachable function of the chip carrier is realized, and the semiconductor chip can be replaced in the using process.
Furthermore, an interface layer made of heat-conducting and insulating materials is filled between the groove and the chip carrier, so that the electric conductivity of the interface is improved, the contact thermal resistance is reduced, the heat diffusion is facilitated, and the reliability of the semiconductor chip is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a semiconductor chip package according to embodiment 1 of the present application;
fig. 2 is a schematic structural diagram of another semiconductor chip package in embodiment 1 of the present application;
FIG. 3 is a schematic view of the combination of the chip carrier, the limiting member and the semiconductor chip in FIG. 2;
fig. 4 is a schematic structural view of another semiconductor chip package in embodiment 1 of the present application;
FIG. 5 is a top view of the structure for the semiconductor chip package of FIG. 5;
FIG. 6 is a three-dimensional schematic diagram of the structure for the semiconductor chip package of FIG. 5;
fig. 7 is a schematic structural diagram of a semiconductor chip package according to embodiment 2 of the present application;
fig. 8 is a schematic structural view of a semiconductor chip package according to embodiment 3 of the present application;
fig. 9 is a schematic structural diagram of a semiconductor chip package according to embodiment 4 of the present application.
Description of the reference numerals:
1-a substrate; 2-chip carrying platform; 3-a semiconductor chip; 4-an insulating layer; 401 — a first insulating layer; 402-a second insulating layer; 5-a conductive layer; 501-a first conductive layer; 502-a second conductive layer; 601-a stop; 602-an interface layer; 603-a connector; 7-a conductive terminal; 8-a control electrode; 9-inserting groove.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in a specific case to those of ordinary skill in the art.
Furthermore, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
The present embodiment provides a structure for semiconductor chip packaging, as shown in fig. 1, including: the substrate 1, the said substrate 1 adopts the heat conduction material; a groove is formed in the upper surface of the substrate 1, a chip carrier 2 is arranged in the groove, and a semiconductor chip 3 is arranged on the chip carrier 2; the chip carrier 2 is made of heat conducting materials, and the difference ratio between the thermal expansion coefficient of the chip carrier 2 and the thermal expansion coefficient of the semiconductor chip 3 is smaller than a preset value; an insulating layer 4 is further arranged on the upper surface of the substrate 1, a conducting layer 5 is arranged on the surface of one side, away from the substrate 1, of the insulating layer, and the conducting layer is electrically connected with the semiconductor chip 3; the semiconductor chip packaging structure comprises a shell, a substrate 1 and a plurality of conducting layers, wherein the shell covers the substrate 1, a cavity for accommodating a semiconductor chip 3, a chip carrier 2, an insulating layer 4 and the conducting layers 5 is formed in the shell, and a plastic packaging material is filled in the cavity; and one end of the conductive terminal 7 is connected with the conductive layer 5, and the other end of the conductive terminal 7 is exposed out of the shell.
The upper surface of the substrate 1 of the embodiment is provided with the groove, the chip carrier 2 arranged in the groove is provided with the semiconductor chip 3, and the number of interfaces through which heat generated by the semiconductor chip 3 passes in the process of outward transmission is reduced, so that the thermal contact resistance is reduced, and the heat dissipation effect is improved. Furthermore, the difference between the thermal expansion coefficient of the chip carrier 2 and the thermal expansion coefficient of the semiconductor chip 3 is controlled within a preset value range, so that the stress at the interface between the chip carrier 2 and the semiconductor chip 3 under the working condition is reduced, the generation of micro cracks caused by warping is avoided, and further, the thermal conductivity of gas in the cracks is far smaller than that of solid, so that the heat dissipation performance of the packaging structure is remarkably reduced, and the stability of the semiconductor chip 3 is damaged.
In one embodiment, as shown in fig. 1, the chip carrier 2 includes a base and a bump, the base is embedded in the groove, the bump is located on a side of the base away from the substrate 1, and the semiconductor chip 3 is electrically connected to an upper surface of the bump.
Referring to fig. 2, a limiting member 601 is disposed between the chip carrier 2 and the groove, the limiting member 601 is clamped to the chip carrier 2, and the limiting member 601 is made of a heat conductive material. Through with locating part 601 and chip carrier 2 joint, fill the locating part 601 with the groove area between chip carrier 2 and the base plate 1 simultaneously, both can fix chip carrier 2, can realize the detachable purpose again. When the semiconductor chip 3 fails, replacement can be performed. The limiting member comprises a ring shape or other shapes. In an alternative embodiment, as shown in fig. 2 and fig. 3, the position-limiting member 601 includes a first position-limiting member disposed around a sidewall of the base platform and a second position-limiting member covering at least a portion of an upper surface of the base platform. In particular, the boss has a thickness of 0.5mm to 2mm, for example 0.5mm, 1mm, 1.5mm or 2mm. Preferably, the size of the upper surface of the boss is the same as the size of the semiconductor chip 3, or the size of the upper surface of the boss is larger than the size of the semiconductor chip 3. The semiconductor chip 3 is securely bonded to the upper surface of the bump.
In this embodiment, the substrate 1 and the chip carrier 2 are both made of a heat conductive material, and a difference ratio between a thermal expansion coefficient of the chip carrier 2 and a thermal expansion coefficient of the semiconductor chip 3 is smaller than a preset value. Preferably, said preset value is less than 60%. Illustratively, the coefficient of thermal expansion of the chip stage 2 may be close to that of the semiconductor chip 3. Assuming that the coefficient of thermal expansion of the chip stage 2 is C 1 The coefficient of thermal expansion of the semiconductor chip 3 is C 2 The difference ratio of the thermal expansion coefficients is expressed by | C 1 -C 2 |/C 1 Meaning, it can be less than about 60%, and even less than about 25%. Coefficient of thermal expansion C 1 And coefficient of thermal expansion C 2 May also be equal to each other.
In this embodiment, the chip carrier 2 is made of a conductive material. The chip stage 2 not only has a function of supporting the semiconductor chip 3 but also has an effect of one electrode of the semiconductor chip 3. In a specific embodiment, the material of the chip carrier 2 includes an aluminum diamond composite material, because the aluminum diamond composite material has both good thermal conductivity and electrical conductivity, and a thermal expansion coefficient matched with that of the semiconductor chip 3. Specifically, the thermal conductivity of the aluminum-diamond composite material is 550W/(m DEG C) -600W/(m DEG C), which is better than that of copper about 398W/(m DEG C). The thermal expansion coefficient of the aluminum diamond composite material is 6 multiplied by 10 -6 /K-7×10 -6 K, the coefficient of thermal expansion of the semiconductor chip 3, which is mainly silicon, is about 2.6 × 10 -6 K, sintering or reflow soldering semiconductor core by nano silverThe sheet 3 is joined with the aluminum diamond composite material. The difference ratio of the thermal expansion coefficients of the aluminum-diamond composite material and the silicon is about 60 percent and is less than that of the common copper 17.5 multiplied by 10 -6 The difference ratio of thermal expansion coefficients of/K and silicon.
In an alternative embodiment, the substrate 1 is a conductive material, and the material of the substrate 1 includes an aluminum diamond composite material. When the substrate 1 and the chip carrier 2 are made of the aluminum diamond composite material, the stress of the interface of the substrate 1 and the chip carrier 2 is small, and the heat conducting performance is good. Through experimental comparison, the thermal resistance of the substrate 1 made of the aluminum-diamond composite material is reduced by about 20% compared with that of the conventional molybdenum-copper material.
In this embodiment, as shown in fig. 1, two rows of grooves are oppositely disposed on the substrate 1. One or more grooves can be arranged in each column according to the requirement. Each groove is provided with a chip carrier 2 and a semiconductor chip 3 positioned on the chip carrier 2.
In one embodiment, one semiconductor chip 3 is disposed on the chip carrier 2. In another embodiment, a plurality of semiconductor chips 3 are disposed on the chip carrier 2. Further, the upper surface of the substrate 1 may be provided with one or more grooves for mounting the chip carrier 2.
In an alternative embodiment, the stopper 601 is a conductive material. Specifically, the material of the limiting member 601 includes copper. The coefficient of thermal expansion of copper is larger and reaches 17.8 multiplied by 10 -6 and/K, therefore, the stopper 601 made of copper is placed between the chip stage 2 and the groove at a low temperature, and when the temperature is raised back to room temperature, the chip stage 2 can be tightly bonded to the substrate 1 by the effect of thermal expansion.
In one embodiment, as shown in fig. 4, the insulating layer 4 includes a first insulating layer 401 and a second insulating layer 402, and the conductive layer 5 includes a first conductive layer 501 and a second conductive layer 502; a first conductive layer 501 is arranged on the surface of one side, away from the substrate 1, of the first insulating layer 401, and a conductive terminal 7 is arranged on the first conductive layer 501; a second conductive layer 502 is disposed on a side surface of the second insulating layer 402 facing away from the substrate 1, and a control electrode 8 is disposed on the second conductive layer 502. Specifically, referring to the cross-sectional view of fig. 4 and the top view of fig. 5, two first insulating layers 401 are respectively disposed on two sides of the second insulating layer 402, a first conductive layer 501 is respectively disposed on one side surface of the two first insulating layers 401 away from the substrate 1, a second conductive layer 502 is disposed on one side surface of the second insulating layer 402 away from the substrate 1, and a row of grooves is disposed between each first insulating layer 401 and each second insulating layer 402. Preferably, the two rows of recesses and the two first insulating layers 401 are symmetrically distributed with respect to the second insulating layer 402. The recess is provided with a chip stage 2 and a semiconductor chip 3 mounted on the chip stage 2.
Further, referring to the cross-sectional view of fig. 4 and the top view of fig. 5, at least one insertion groove 9 is disposed on the surface of the first conductive layer 501, the insertion groove 9 is detachably connected to a conductive connecting member, and the conductive connecting member is electrically connected to the semiconductor chip 3; the surface of the second conductive layer 502 is provided with at least one insertion groove, the insertion groove is detachably connected with a conductive connecting piece, and the conductive connecting piece is electrically connected with the semiconductor chip 3.
In an alternative embodiment, as shown in fig. 4, the semiconductor chip 3 includes an IGBT chip, a collector of the IGBT chip is connected to the chip carrier 2, an emitter of the IGBT chip is electrically connected to the conductive terminal 7 after passing through the conductive connecting member and the first conductive layer 501 in sequence, and a gate of the IGBT chip is electrically connected to the control electrode 8 after passing through the conductive connecting member and the second conductive layer 502 in sequence. Optionally, the conductive connector comprises a bonding wire or a bonding tape. The collector side adopts a copper ring structure design without welding, the emitter and the grid adopt a pluggable assembly mode, and the emitter and the grid can be flexibly disassembled by combining. The three-dimensional structure is shown in fig. 6.
During packaging, the semiconductor chip 3 is connected with the chip carrier through nano-silver sintering or reflow soldering process. Then, the limiting member made of copper is placed between the chip carrier and the groove at extremely low temperature, and because the coefficient of thermal expansion of copper is large, when the temperature rises back to the use temperature range of the semiconductor chip 3, especially under high temperature, the close combination of the substrate 1 and the chip carrier 2 can be ensured. After a first insulating layer 401, a first conducting layer 501, a second insulating layer 402 and a second conducting layer 502 are formed on the surface of the substrate 1, on one hand, the inserting groove 9 is inserted into the first conducting layer 501, the first conducting layer 501 is electrically connected with an emitter electrode of the semiconductor chip 3 through a bonding wire or a bonding tape, and a conductive terminal 7 is welded on the first conducting layer 501 and then led out from the upper section; on the other hand, the insertion groove 9 is inserted into the second conductive layer 502, the second conductive layer 502 is electrically connected to the gate of the semiconductor chip 3 by a bonding wire or a bonding tape, and the control electrode 8 is soldered to the second conductive layer 502. Finally, the shell is subjected to plastic package and is solidified at high temperature, so that the insulation protection effect is achieved.
Example 2
In this embodiment, as shown in fig. 7, the structure for packaging a semiconductor chip further includes: a detachable connecting member 603 is provided on the substrate 1, and the connecting member 603 is connected to the chip stage 2 or the limiting member 601 and is used to fix the chip stage 2. In another embodiment, the detachable connection 603 is provided on the substrate 1 while an interface layer 602 is filled between the bottom of the recess and the chip carrier 2.
Example 3
In this embodiment, referring to fig. 8, on the basis of embodiment 1, the structure for packaging a semiconductor chip further includes: an interface layer 602 is filled between the groove and the chip carrier 2. Specifically, the Interface layer 602 is made of a Thermal Interface Material (TIM), such as silicone grease, which is a paste-like Thermal Interface Material with good Thermal conductivity, and can fill the pores at the Interface portion, replace air with low Thermal conductivity, reduce Thermal resistance, improve the heat dissipation capability of the package structure, and enhance the fixation of the semiconductor chip 3.
Example 4
In this embodiment, referring to fig. 9, on the basis of embodiment 2, the structure for packaging a semiconductor chip further includes: an interface layer 602 is filled between the groove and the chip carrier 2. Specifically, the Interface layer 602 is made of a Thermal Interface Material (TIM).
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (20)
1. A structure for semiconductor chip packaging, comprising:
a substrate (1);
a groove is formed in the upper surface of the substrate (1), a chip carrier (2) is arranged in the groove, and a semiconductor chip (3) is arranged on the chip carrier (2);
an insulating layer (4) is further arranged on the upper surface of the substrate (1), a conducting layer (5) is arranged on the surface of one side, away from the substrate (1), of the insulating layer, and the conducting layer is electrically connected with the semiconductor chip (3);
the semiconductor packaging structure comprises a shell, a substrate and a plurality of conducting layers, wherein the shell covers the substrate (1), a cavity for accommodating a semiconductor chip (3), a chip carrying platform (2), an insulating layer (4) and the conducting layers (5) is formed in the shell, and a plastic packaging material is filled in the cavity;
and one end of the conductive terminal (7) is connected with the conductive layer (5), and the other end of the conductive terminal (7) is exposed out of the shell.
2. The structure for packaging a semiconductor chip according to claim 1, wherein the chip carrier (2) comprises a base and a boss which are integrally formed, the base is embedded in the groove, the boss is located on one side of the base away from the substrate (1), and the semiconductor chip (3) is electrically connected with the upper surface of the boss.
3. The structure for packaging a semiconductor chip according to claim 2, wherein a limiting member (601) is disposed between the chip carrier (2) and the groove, the limiting member (601) is clamped with the chip carrier (2), and the limiting member (601) is made of a heat conductive material.
4. The structure for packaging a semiconductor chip according to claim 3, wherein the position-limiting member (601) comprises a first position-limiting member disposed around the side wall of the base and a second position-limiting member covering at least a part of the upper surface of the base.
5. The structure for semiconductor chip packaging according to claim 2, wherein the boss has a thickness of 0.5mm to 2mm.
6. The structure for semiconductor chip packaging according to claim 2, characterized in that the size of the upper surface of the boss is the same as the size of the semiconductor chip (3) or the size of the upper surface of the boss is larger than the size of the semiconductor chip (3).
7. The structure for semiconductor chip packaging according to claim 1, wherein the substrate (1) and the die stage (2) are both made of a thermally conductive material, and a difference ratio between a thermal expansion coefficient of the die stage (2) and a thermal expansion coefficient of the semiconductor chip (3) is smaller than a predetermined value.
8. The structure for semiconductor chip packaging according to claim 1 or 7, characterized in that the chip carrier (2) is of an electrically conductive material.
9. The structure for semiconductor chip packaging according to claim 8, wherein the material of the chip carrier (2) comprises an aluminum-diamond composite.
10. The structure for semiconductor chip packaging according to claim 1 or 7, characterized in that the substrate (1) is a conductive material.
11. The structure for semiconductor chip packaging according to claim 10, characterized in that the material of the substrate (1) comprises an aluminum diamond composite.
12. The structure for a semiconductor chip package according to claim 3, wherein the stopper (601) is a conductive material.
13. The structure for semiconductor chip packaging according to claim 1, further comprising: an interface layer (602) is filled between the bottom of the recess and the chip carrier (2).
14. The structure for semiconductor chip packaging according to claim 13, wherein the interface layer (602) is made of a thermally conductive and insulating material.
15. The structure for semiconductor chip packaging according to any one of claims 13 or 14, further comprising: the substrate (1) is provided with a detachable connecting piece (603), and the connecting piece (603) is connected with the chip carrier (2) and used for fixing the chip carrier (2).
16. The structure for semiconductor chip packaging according to claim 1, wherein the insulating layer (4) comprises a first insulating layer (401) and a second insulating layer (402), and the conductive layer (5) comprises a first conductive layer (501) and a second conductive layer (502);
a first conducting layer (501) is arranged on the surface of one side, away from the substrate (1), of the first insulating layer (401), and the conducting terminals (7) are arranged on the first conducting layer (501);
and a second conducting layer (502) is arranged on one side surface of the second insulating layer (402) departing from the substrate (1), and a control electrode (8) is arranged on the second conducting layer (502).
17. The structure for semiconductor chip packaging according to claim 16, wherein the surface of the first conductive layer is provided with at least one insertion groove (9), the insertion groove (9) is detachably connected with a conductive connecting member, and the conductive connecting member is electrically connected with the semiconductor chip (3);
the surface of the second conducting layer is provided with at least one inserting groove, the inserting groove is detachably connected with a conductive connecting piece, and the conductive connecting piece is electrically connected with the semiconductor chip (3).
18. The structure for packaging the semiconductor chip according to any one of claims 16 and 17, wherein the semiconductor chip (3) comprises an IGBT chip, a collector of the IGBT chip is connected to the chip carrier (2), an emitter of the IGBT chip is electrically connected to the conductive terminal (7) after passing through the conductive connecting member and the first conductive layer (501) in sequence, and a gate of the IGBT chip is electrically connected to the control electrode (8) after passing through the conductive connecting member and the second conductive layer (502) in sequence.
19. The structure for semiconductor chip packaging of claim 17, wherein the conductive connection comprises a bond wire or a bond ribbon.
20. The structure for semiconductor chip packaging according to claim 1, wherein at least one of the semiconductor chips (3) is provided on the chip carrier (2).
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| CN202210839504.7A CN115188722A (en) | 2022-07-15 | 2022-07-15 | Structure for packaging semiconductor chip |
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| CN116314072A (en) * | 2023-03-27 | 2023-06-23 | 珠海市浩威达电子科技有限公司 | Package structure of rectifying module and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116314072A (en) * | 2023-03-27 | 2023-06-23 | 珠海市浩威达电子科技有限公司 | Package structure of rectifying module and manufacturing method thereof |
| CN116314072B (en) * | 2023-03-27 | 2023-12-05 | 珠海市浩威达电子科技有限公司 | Package structure of rectifying module and manufacturing method thereof |
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