CN1150559C - 集成半导体电路内连接线上补偿不同电压的电路装置 - Google Patents
集成半导体电路内连接线上补偿不同电压的电路装置 Download PDFInfo
- Publication number
- CN1150559C CN1150559C CNB011217146A CN01121714A CN1150559C CN 1150559 C CN1150559 C CN 1150559C CN B011217146 A CNB011217146 A CN B011217146A CN 01121714 A CN01121714 A CN 01121714A CN 1150559 C CN1150559 C CN 1150559C
- Authority
- CN
- China
- Prior art keywords
- voltage
- plateline
- circuit arrangement
- test pattern
- bit line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
Description
Claims (5)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10031947A DE10031947B4 (de) | 2000-06-30 | 2000-06-30 | Schaltungsanordnung zum Ausgleich unterschiedlicher Spannungen auf Leitungszügen in integrierten Halbleiterschaltungen |
DE10031947.5 | 2000-06-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1331471A CN1331471A (zh) | 2002-01-16 |
CN1150559C true CN1150559C (zh) | 2004-05-19 |
Family
ID=7647384
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB011217146A Expired - Fee Related CN1150559C (zh) | 2000-06-30 | 2001-06-29 | 集成半导体电路内连接线上补偿不同电压的电路装置 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6574132B2 (zh) |
EP (1) | EP1168356A1 (zh) |
JP (1) | JP3781986B2 (zh) |
KR (1) | KR20020002316A (zh) |
CN (1) | CN1150559C (zh) |
DE (1) | DE10031947B4 (zh) |
TW (1) | TW512362B (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101010766B1 (ko) * | 2002-05-16 | 2011-01-25 | 콘티넨탈 오토모티브 게엠베하 | 전력 공급 회로 |
KR20120010052A (ko) * | 2010-07-23 | 2012-02-02 | 삼성전자주식회사 | 이퀄라이징 기능을 갖는 저항성 메모리 및 이를 포함하는 3차원 반도체 장치 |
US9804650B2 (en) * | 2014-09-04 | 2017-10-31 | Qualcomm Incorporated | Supply voltage node coupling using a switch |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2652672B1 (fr) * | 1989-10-02 | 1991-12-20 | Sgs Thomson Microelectronics | Memoire a temps de lecture ameliore. |
US5070385A (en) * | 1989-10-20 | 1991-12-03 | Radiant Technologies | Ferroelectric non-volatile variable resistive element |
JP2573392B2 (ja) * | 1990-03-30 | 1997-01-22 | 株式会社東芝 | 半導体記憶装置 |
JP2829135B2 (ja) * | 1990-12-27 | 1998-11-25 | 株式会社東芝 | 半導体記憶装置 |
US5737260A (en) * | 1996-03-27 | 1998-04-07 | Sharp Kabushiki Kaisha | Dual mode ferroelectric memory reference scheme |
KR100268875B1 (ko) * | 1998-05-13 | 2000-10-16 | 김영환 | 비휘발성 강유전체 메모리소자의 구동회로 |
JP2000123578A (ja) * | 1998-10-13 | 2000-04-28 | Sharp Corp | 半導体メモリ装置 |
KR100308188B1 (ko) * | 1999-04-27 | 2001-10-29 | 윤종용 | 안정된 감지 마진을 가지는 강유전체 랜덤 액세스 메모리 |
JP3377762B2 (ja) * | 1999-05-19 | 2003-02-17 | 株式会社半導体理工学研究センター | 強誘電体不揮発性メモリ |
JP3884193B2 (ja) * | 1999-09-14 | 2007-02-21 | 株式会社東芝 | 半導体記憶装置及びその試験方法 |
DE19944036C2 (de) * | 1999-09-14 | 2003-04-17 | Infineon Technologies Ag | Integrierter Speicher mit wenigstens zwei Plattensegmenten |
DE19952311B4 (de) * | 1999-10-29 | 2006-07-13 | Infineon Technologies Ag | Integrierter Speicher mit Speicherzellen vom 2-Transistor/2-Kondensator-Typ |
-
2000
- 2000-06-30 DE DE10031947A patent/DE10031947B4/de not_active Expired - Fee Related
-
2001
- 2001-06-11 EP EP01114211A patent/EP1168356A1/de not_active Withdrawn
- 2001-06-27 JP JP2001195517A patent/JP3781986B2/ja not_active Expired - Fee Related
- 2001-06-28 TW TW090115737A patent/TW512362B/zh not_active IP Right Cessation
- 2001-06-29 KR KR1020010038163A patent/KR20020002316A/ko not_active IP Right Cessation
- 2001-06-29 CN CNB011217146A patent/CN1150559C/zh not_active Expired - Fee Related
- 2001-07-02 US US09/897,280 patent/US6574132B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
TW512362B (en) | 2002-12-01 |
US6574132B2 (en) | 2003-06-03 |
US20020007480A1 (en) | 2002-01-17 |
EP1168356A1 (de) | 2002-01-02 |
CN1331471A (zh) | 2002-01-16 |
JP3781986B2 (ja) | 2006-06-07 |
KR20020002316A (ko) | 2002-01-09 |
JP2002025248A (ja) | 2002-01-25 |
DE10031947A1 (de) | 2002-01-24 |
DE10031947B4 (de) | 2006-06-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C41 | Transfer of patent application or patent right or utility model | ||
C56 | Change in the name or address of the patentee |
Owner name: INFINEON TECHNOLOGIES AG Free format text: FORMER NAME: INFENNIAN TECHNOLOGIES AG |
|
CP01 | Change in the name or title of a patent holder |
Address after: Munich, Germany Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: INFINEON TECHNOLOGIES AG |
|
TR01 | Transfer of patent right |
Effective date of registration: 20130703 Address after: Munich, Germany Patentee after: QIMONDA AG Address before: Munich, Germany Patentee before: Infineon Technologies AG |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20160113 Address after: German Berg, Laura Ibiza Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: QIMONDA AG |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040519 Termination date: 20160629 |
|
CF01 | Termination of patent right due to non-payment of annual fee |