CN1331471A - 集成半导体电路内连接线上补偿不同电压的电路装置 - Google Patents

集成半导体电路内连接线上补偿不同电压的电路装置 Download PDF

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CN1331471A
CN1331471A CN01121714A CN01121714A CN1331471A CN 1331471 A CN1331471 A CN 1331471A CN 01121714 A CN01121714 A CN 01121714A CN 01121714 A CN01121714 A CN 01121714A CN 1331471 A CN1331471 A CN 1331471A
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voltage
plateline
bit line
circuit arrangement
circuit
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CN1150559C (zh
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R·埃斯特尔
Z·曼约基
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Infineon Technologies AG
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

本发明涉及用于补偿在集成半导体电路内在连接线上不同电压的电路装置,其中在位线和板极线之间提供一只电压补偿晶体管,该晶体管在半导体电路正常运行时通过控制信号是可以低欧姆连接的,以便补偿在线上不同的电压。

Description

集成半导体电路内连接线上补偿不同电压的电路装置
本发明涉及用于补偿在铁电RAM存储器位线上高电平位线电压和铁电RAM存储器的板极线上高电平板极线电压之间电压差的电路装置。
迄今在铁电RAM存储器的板极线和位线上的读和写电压以相等分量对板极线和位线供电的发生器系统产生。
如果这种电压发生器产生一个唯一的输出电压，则可能以较高概率出现：经分离的位线和板极线到多个存储器单元或存储器段分配的电压，在某些点在存储器电路某些运行状态下具有区别的电平，它例如可以用测试模式检测。
DE 691 19679 T2描述了半导体存储器读出放大器的输出电路。这时半导体存储器的输出信号短时稳定地保持在一固定电平，也就是说即使出现补偿脉冲，即出现信号不精确性时。
为此目的，在已知的输出电路中，在两反相输出信号线之间连接一传输门电路，它在短时间内导通。已知输出电路的上述两根输出信号线通常原理上总是存在相反的电位，该电位由两互补连接的差分放大器产生。因此在已知的输出电路应当补偿的并非可能具有一定差异的、名义上相等的两电压电平，而是短时地在两反相输出信号之间产生一平均电位。
本发明的任务是，如此提供用于补偿在集成半导体电路内连接线上不同电压、尤其是补偿铁电RAM-存储器的高电平位线电压和高电平板极线电压，使得在标准运行时补偿各种电压(尤其是读、写电压)，此外可以用测试模式彼此独立地评价。
本任务根据发明通过在位线和板极线间提供电压补偿晶体管解决，该晶体管在半导体电路正常运行时，在位线和板极线上写或读电压都具有高电平时，为了补偿在位线和板极线之间的电压差通过一控制信号是可以低欧姆连接的。
电压补偿晶体管补偿在铁电RAM存储器板极线和位线上不同电压电平并能在测试模式高欧姆连接，因此独立的检测板极线和位线电压是可能的。
最好电压补偿晶体管是一只MOS晶体管，它以其源极接头和漏极接头各自与位线和板极线连接，并且控制信号，即在正常运行时反转测试模式信号，是可加在其栅极接头上。
按照这种方式电压补偿晶体管在测试模式是可以高欧姆连接的，因此在测试模式可达到板极线电压和位线电压分开。因此在铁电RAM存储器情况下，铁电存储单元更佳的描述特性是可能的。
本发明的电路装置的实施例依靠一个唯一附图详细说明如下。
该图示出-部分作为方框图-在集成铁电RAM存储器10内提供的本发明的电路装置。由VBL_H发生器3和与其分开的VPL发生器4分别产生应经位线1分配的高电平VBL_H位线电压和应经板极线2分配的高电平VPL_H板极线电压。VBL_H发生器3和VPL发生器4由外电压Vext7和8馈电。
根据本发明提供一只电压补偿晶体管5，该晶体管在正常运行时在位线1和板极线2之间形成低欧姆桥，并且它是可以在测试模式通过其控制极接头6输入的信号TESTMODE高欧姆连接的，使得在测试模式板极线电压和位线电压是分开的。因此板极线电压和位线电压可以分开检测并因此与位线和板极线连接的铁电存储单元(在图内未示出)可更佳描述特性。
在实施例内，电压补偿晶体管是一只MOS晶体管5，它以图中描述的方式以其源极接头和漏极接头分别在位线1和板极线2上连接。MOS晶体管5在其栅极接头上在正常运行时得到反转的测试模式信号TESTMODE-C，并因此以低欧姆连接。
参考符号表1  位线，2  板极线，3  VBL H发生器，4  VPL发生器，5  电压补偿晶体管，6  控制信号TESTMODE-C，7，8  外电压Vext，10  铁电RAM存储器，VBL_H高电平位线电压，VPL_H高电平板极线电压。

Claims (4)

1.用于补偿在电铁RAM-存储器(10)的位线(1)上高电平位线电压(VBL_H)和板极线(2)上高电平板极线电压(VPL_H)之间电压差的电路装置，
其特征为：
在位线(1)和板极线(2)之间提供一只电压补偿晶体管(5)，它在半导体电路正常运行时，在位线(1)和板极线(2)上写或读电压一起具有高电平期间，通过控制信号(6)是可以低欧姆连接的，以便补偿在位线(1)和板极线(2)之间的电压差。
2.根据权利要求1所述的电路装置，
其特征为：
电压补偿晶体管(5)是一只MOS晶体管，它以其源极接头和漏极接头各自在位线(1)和板极线(2)上连接，并且控制信号(6)是可以加在其栅极接头上的。
3.根据权利要求1或2所述的电路装置，
其特征为：
在铁电RAM存储器的情况下，控制信号(6)是反转的测试模式信号(TESTMODE-C)。
4.根据前述权利要求之一所述的电路装置，
其特征为：
如果存在非正常运行，则在测试模式中电压补偿晶体管(5)通过正确的测试模式信号是可以高欧姆连接的。
CNB011217146A 2000-06-30 2001-06-29 集成半导体电路内连接线上补偿不同电压的电路装置 Expired - Fee Related CN1150559C (zh)

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DE10031947A DE10031947B4 (de) 2000-06-30 2000-06-30 Schaltungsanordnung zum Ausgleich unterschiedlicher Spannungen auf Leitungszügen in integrierten Halbleiterschaltungen
DE10031947.5 2000-06-30

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1653401B (zh) * 2002-05-16 2010-05-12 西门子公司 供电电路
CN106662903A (zh) * 2014-09-04 2017-05-10 高通股份有限公司 使用开关的供电电压节点耦合

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KR20120010052A (ko) * 2010-07-23 2012-02-02 삼성전자주식회사 이퀄라이징 기능을 갖는 저항성 메모리 및 이를 포함하는 3차원 반도체 장치

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US5070385A (en) * 1989-10-20 1991-12-03 Radiant Technologies Ferroelectric non-volatile variable resistive element
JP2573392B2 (ja) * 1990-03-30 1997-01-22 株式会社東芝 半導体記憶装置
JP2829135B2 (ja) * 1990-12-27 1998-11-25 株式会社東芝 半導体記憶装置
US5737260A (en) * 1996-03-27 1998-04-07 Sharp Kabushiki Kaisha Dual mode ferroelectric memory reference scheme
KR100268875B1 (ko) * 1998-05-13 2000-10-16 김영환 비휘발성 강유전체 메모리소자의 구동회로
JP2000123578A (ja) * 1998-10-13 2000-04-28 Sharp Corp 半導体メモリ装置
KR100308188B1 (ko) * 1999-04-27 2001-10-29 윤종용 안정된 감지 마진을 가지는 강유전체 랜덤 액세스 메모리
JP3377762B2 (ja) * 1999-05-19 2003-02-17 株式会社半導体理工学研究センター 強誘電体不揮発性メモリ
JP3884193B2 (ja) * 1999-09-14 2007-02-21 株式会社東芝 半導体記憶装置及びその試験方法
DE19944036C2 (de) * 1999-09-14 2003-04-17 Infineon Technologies Ag Integrierter Speicher mit wenigstens zwei Plattensegmenten
DE19952311B4 (de) * 1999-10-29 2006-07-13 Infineon Technologies Ag Integrierter Speicher mit Speicherzellen vom 2-Transistor/2-Kondensator-Typ

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1653401B (zh) * 2002-05-16 2010-05-12 西门子公司 供电电路
CN106662903A (zh) * 2014-09-04 2017-05-10 高通股份有限公司 使用开关的供电电压节点耦合
CN106662903B (zh) * 2014-09-04 2019-07-23 高通股份有限公司 使用开关的供电电压节点耦合

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DE10031947A1 (de) 2002-01-24
KR20020002316A (ko) 2002-01-09
CN1150559C (zh) 2004-05-19
DE10031947B4 (de) 2006-06-14
JP3781986B2 (ja) 2006-06-07
JP2002025248A (ja) 2002-01-25
US6574132B2 (en) 2003-06-03
TW512362B (en) 2002-12-01
US20020007480A1 (en) 2002-01-17
EP1168356A1 (de) 2002-01-02

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