CN115023791A - 半导体芯片封装件和组装方法 - Google Patents
半导体芯片封装件和组装方法 Download PDFInfo
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Abstract
一种半导体器件衬底组件可以包括第一衬底,该第一衬底包括:第一绝缘板;以及设置在第一绝缘板上的第一图案化金属层,其中第一绝缘板包括第一材料和第一厚度。该组件可以包括第二衬底,该第二衬底包括:第二绝缘板;以及设置在第二绝缘板上的第二图案化金属层,其中第二绝缘板包括第一材料和第一厚度。该组件还可以包括设置在第一衬底和第二衬底之间的第三衬底,该第三衬底包括:第三绝缘板;以及设置在第三绝缘板上的第三图案化金属层,其中第三绝缘板包括第二材料和第二厚度,其中第二材料和第二厚度中的至少一个分别不同于第一材料和第一厚度。
Description
相关申请的交叉应用
本申请要求于2020年1月28日提交的名称为“半导体芯片封装件和组装方法(Semiconductor Chip Package and Method of Assembly)”的美国临时专利申请62/966,951的优先权,其全部内容通过引用结合于此。
技术领域
实施例涉及半导体器件领域,并且尤其是用于功率半导体芯片的封装件。
背景技术
当前的功率半导体模块,包括绝缘栅双极型晶体管(IGBT)或二极管功率模块(例如3.3kV、4.5kV或6.5kV;1500A或1200A)可以包括彼此类似的多个衬底,比如2、4或6个衬底。具有导线和电阻器的每个衬底保持IGBT和二极管芯片以及母线,其中母线用作到功率半导体模块的电源连接件。反过来,衬底可以固定到基板上,以形成排列在公共支撑结构(比如铝碳化硅)上的衬底组件。
功率半导体衬底可以包括两个金属片(例如,Cu或Al)的夹层,它们中的一个被图案化为图案化金属层,并结合到设置在图案化金属片之间的陶瓷。衬底(例如Al2O3、AlN或Si3N4)被仔细地选择,考虑各种要求,包括:1.)需要顶部侧到底部的高度电绝缘(对于高功率模块,通常最小为6kV或10.2kV),2.)需要高竖直导热性,尤其是在半导体芯片下方,以用于最佳可能的冷却;3.)在制造、组装和操作期间,需要可靠的机械稳定性,尤其是在母线附接过程期间,例如,对母线附接过程的机械应力更加稳健;4.)需要顶部金属层的高横向导电性,以使电阻和相应的传导损失最小,以及良好的横向散热;5.)为了确保良好的制造产量和器件质量,需要在组装之前对衬底进行全面的电气测试;6.)材料、工艺和废料的成本需要保持合理的低水平;以及7.)设计必须在某种程度上对称,以确保每组芯片的对称阻抗。
将母线(通常由镀镍铜或纯铜制成)附接到衬底的典型方法包括钎焊、超声波焊接或激光焊接或Ag烧结。在钎焊的情况下,接头本身可能无足够的机械强度。因此,需要额外努力将母线保持在适当位置(例如,用环氧树脂灌封模块)。这种方法不仅需要附加工艺步骤,而且导致长期可靠性和附加重量的进一步问题。最近开发的超声波焊接或激光焊接可以提供无需后续的环氧树脂灌封的非常坚固的连接。因此,原则上期望使用这些后续过程。在成功实施稳健的焊接工艺之前,仍存在几个问题,包括焊接工艺过程中的微粒生成、由于损坏陶瓷衬底的危险而导致的有限的工艺窗口以及焊接工具的有限可接近性。
鉴于上述情况,提供了本实施例。
发明内容
本发明公开了半导体器件衬底组件和封装件,以及相关方法。在一个实施例中,半导体器件衬底组件可以包括第一衬底,该第一衬底包括:第一绝缘板;以及设置在第一绝缘板上的第一图案化金属层,其中第一绝缘板包括第一材料和第一厚度。半导体器件衬底组件可以包括第二衬底,该第二衬底包括:第二绝缘板;以及设置在第二绝缘板上的第二图案化金属层,其中第二绝缘板包括所述第一材料和第一厚度。半导体器件衬底组件还可以包括设置在第一衬底和第二衬底之间的第三衬底,该第三衬底包括:第三绝缘板;以及设置在第三绝缘板上的第三图案化金属层,其中第三绝缘板包括第二材料和第二厚度,其中第二材料和第二厚度中的至少一个分别不同于第一材料和第一厚度。
在另一个实施例中,半导体器件封装件可以包括第一衬底,其中第一衬底包括第一绝缘板;和设置在第一绝缘板上的第一图案化金属层;以及设置在第一图案化金属层上的第一组半导体管芯。该半导体器件封装件可以包括:第二衬底,该第二衬底包括第二绝缘板;设置在第二绝缘板上的第二图案化金属层;以及设置在第二图案化金属层上的第二组半导体管芯。半导体器件封装件可以包括设置在第一衬底和第二衬底之间的第三衬底,其中第三衬底包括第三绝缘板;和设置在第三绝缘板上的第三图案化金属层;以及连接到第三图案化金属层的一组母线。
在另一实施例中,提供了一种形成半导体封装件的方法。该方法可以包括将第一衬底固定在基板上,该第一衬底包括第一绝缘材料和第一图案化金属层。该方法可以包括将第二衬底固定在基板上,第二衬底包括第一绝缘体材料和第二图案化金属层,以及在第一衬底和第二衬底之间将第三衬底固定在基板上,第三衬底包括不同于第一材料的第二绝缘体材料,并且还包括第三图案化金属层。
附图说明
图1A示出了根据本公开的各种实施例的半导体器件封装件的俯视图;
图1B示出了图1A的半导体器件封装件的顶部透视图;
图2示出了根据本公开的一些实施例的图1A的实施例的变型;
图3A示出了根据本公开的实施例的半导体器件封装架构的俯视图;
图3B示出了根据本公开的其它实施例的另一个半导体器件封装的俯视图;以及
图4描绘了根据本公开的实施例的工艺流程。
具体实施方式
下文将参考附图更全面地描述本实施例,附图中示出了示例性实施例。这些实施例不应被解释为限于本文阐述的实施例。相反,提供这些实施例是为了使本公开将是彻底的和完整的,并将其范围充分地传达给本领域技术人员。在附图中,相同的数字始终指代相同的元件。
在以下描述和/或权利要求中,术语“在……上”、“覆盖”、“设置在”和“上方”可以用在以下描述和权利要求中。“在……上”、“覆盖”、“设置在”和“上方”可以用来表示两个或更多个元件彼此直接物理接触。此外,术语“在……上”、“覆盖”、“设置在”和“上方”可以表示两个或更多个元件彼此不直接接触。例如,“上方”可以表示一个元件在另一个元件上方,但彼此不接触,并且在两个元件之间可以有另一个或多个元件。此外,尽管要求保护的主题的范围在这方面不受限制,术语“和/或”可以表示“和”,可以表示“或”,可以表示“异或”,可以表示“一个”,可以表示“一些,但不是全部”,可以表示“两者都不是”,和/或可以表示“两者”。
在各种实施例中,为功率半导体器件提供了半导体器件封装和组装技术。
转向图1A,示出了根据本公开的各种实施例的半导体器件封装件100的俯视图。图1B示出了半导体器件封装件100的变型的顶部透视图。半导体器件封装件100包括布置在基板101上的第一衬底102、第二衬底104和第三衬底106。基板101可以是用于功率半导体器件封装的已知材料,包括陶瓷材料,比如铝碳化硅。实施例不限于本文。在图1的配置中,根据一些实施例,第一衬底102和第二衬底104可以相似或相同,在材料、部件、架构和尺寸方面相同或相似。如下文所述,第三衬底106可以与第一衬底102和第二衬底104基本不同。
作为示例,第一衬底102可以包括第一绝缘板112和设置在第一绝缘板112上的第一图案化金属层122。在各种非限制性实施例中,第一绝缘板112可以由已知的陶瓷材料形成,比如氧化铝、氮化硅或氮化铝。在某些实施例中,第一绝缘板112可以由氮化铝、氮化硅或类似材料形成,具有比如1mm、0.6mm的厚度或类似厚度。因此,第一绝缘板112可以向基板101提供高导热路径。如图所示,第一图案化金属层122可以被图案化成不同区域。应当注意,图案化金属层可以由薄片形成,比如铜片。尽管未示出,但第一衬底102可以在与支撑第一图案化金属层122的一侧相对的一侧上包括金属片,从而形成夹置在两个金属片之间的绝缘板的堆叠,如在已知器件封装中一样。
半导体器件封装件100可以包括设置在第一图案化金属层122上的第一组半导体管芯,示出为半导体管芯132。半导体管芯132可以表示一组功率器件,包括二极管、IGBT等。
类似于第一衬底102,第二衬底104可以包括第二绝缘板114和设置在第二绝缘板114上的第二图案化金属层124。在各种非限制性实施例中,第二绝缘板114可以由已知的陶瓷材料形成,比如氧化铝、氮化硅或氮化铝。在某些实施例中,第二绝缘板114可以由氮化铝形成,其具有比如1mm、0.5mm的厚度或类似厚度。因此,第二绝缘板114可以向基板101提供高导热路径。如图所示,第二图案化金属层124可以被图案化为不同区域。应当注意,第二图案化金属层124可以由薄片形成,比如铜片。尽管未示出,但第二衬底104可以在与支撑第二图案化金属层124的一侧相对的一侧上包括金属片,从而形成夹置在两个金属片之间的绝缘板的堆叠,如在已知器件封装中一样。
同样,半导体器件封装件100可以包括设置在第二图案化金属层124上的第二组半导体管芯,示出为半导体管芯134。半导体管芯134可以表示一组功率器件,包括二极管、IGBT等。
如在已知功率半导体器件封装件中,第一衬底102和第二衬底104可以配置为相同,包括第一绝缘板112和第二绝缘板114的厚度。然而,在一些实施例中,第二绝缘板114的厚度无需匹配第一绝缘板的厚度。在半导体管芯132和半导体管芯134为功率半导体芯片的实施例中,为了产生大电流,第一绝缘板112和第二绝缘板114可以设计为用于消散过多的热量,在其中高的热导率和低厚度是期望的。因此,在特定实施例中,第一绝缘板112和第二绝缘板114可以各自由氮化铝、氮化硅或类似材料形成,具有比如1mm,比如0.6mm的厚度,或其他合适厚度。
如图1A和图1B所示,半导体器件封装件100还可以包括设置在第一衬底102和第二衬底104之间的第三衬底106。第三衬底106可以包括第三绝缘板116和设置在第三绝缘板116上的第三图案化金属层126。如图所示,第三图案化金属层126可以形成在不同部段中。因此,第三图案化金属层126可以由多个图案化结构形成,以容纳设置在其上的母线组件。
如图1A和图1B所示,半导体器件封装件100还可以包括在多个不同部段中连接到第三图案化金属层126的母线组件。母线组件显示为母线140,其中母线140可以由相对较厚的金属形成,比如铜,并且可以在基板101的平面上方延伸,如图所示。
应当注意,尽管第一绝缘板112和第二绝缘板114可以由第一材料(比如氮化硅)制成,但第三绝缘板116可以由第二材料(比如氮化铝或氧化铝)制成。另外,根据各种实施例,第三绝缘板116的厚度可以不同于第一绝缘板112和第二绝缘板114的厚度。例如,第三绝缘板116可以由比第一绝缘板和第二绝缘板更厚的绝缘材料形成。第三绝缘板116的材料和厚度的选择可以考虑将母线140附接到第三绝缘板116上的第三图案化金属层126的工艺。更有效的附接工艺(比如超声波焊接)可能要求针对第三绝缘板116的相对更大的厚度和相对更坚韧的材料。
半导体器件封装件100还可以包括将第三图案化金属层126电连接到第一图案化金属层122的第一组电连接器(示出为连接器128),以及将第三图案化金属层126电连接到第二图案化金属层124的第二组连接器(示出为连接器129)。因此,半导体器件封装件100提供了对一组半导体管芯进行电气和热管理的组件,其中半导体管芯被支撑在与支撑母线的第三衬底分开的一对绝缘衬底上。有利地,这种布置有助于从母线与半导体管芯电联接的区域裁剪用于半导体管芯热管理的绝缘体衬底区域的能力,如下文所述。
特别转向图1B,如透视图所示,母线140(其具有比连接器128和连接器129相对更大厚度)可以通过超声波焊接或其他焊接工艺更好地附接到第三图案化金属层126,这提供了比连接器128和连接器129所需的更稳固的连接,而不会损坏衬底陶瓷(比如第三绝缘板116)。同时,可以独立地选择衬底陶瓷(参见第一绝缘板112和第二绝缘板114),使得它们提供功率半导体芯片组所需的电隔离和高的热导率的最佳特性。作为示例,连接器128可以通过钎焊工艺附接到第一图案化金属层122和第三图案化金属层126。连接器129同样可以通过钎焊工艺附接到第二图案化金属层124和第三图案化金属层126。由于母线140附接到第三衬底106,而不是附接到包括半导体管芯的衬底,比如第一衬底102或第二衬底104,因此在图1A和图1B的布置中提供了多个优点。由于第三绝缘板116可以由比第一绝缘板112和第二绝缘板114更坚韧和更厚的材料制成,因此除了选择更稳固的附接工艺的灵活性之外,该架构允许母线140的附接工艺避免干扰或损坏较不坚韧、更薄的衬底,即第一衬底102和第二衬底104。
现在转向表格I,示出了根据本公开的一些实施例的用于组装半导体器件封装件的一组示例性操作。如图所示,在组装之前,半导体管芯可以经受一组测试。在DCB操作中,一对铜片可以固定至陶瓷衬底,比如氧化铝、氮化铝或氮化硅。这些片可以图案化为适于形成用于半导体管芯衬底的图案化金属层,该半导体管芯衬底是指支撑半导体管芯的衬底。单独地,铜片可以附接至“母线衬底”以用于支撑母线,与半导体管芯衬底分离。应当注意,如上所述,母线衬底的陶瓷在厚度以及材料上可以不同于半导体管芯衬底。单独地,母线可以冲压、成形和退火为预定形状。
根据本实施例,在组装期间,半导体管芯衬底可以与母线衬底单独地组装。根据已知技术,半导体管芯(芯片)可以被钎焊到相应的半导体管芯衬底。根据本实施例,如上所述,半导体管芯衬底可以选择为具有针对电隔离和导热性而优化的厚度和材料的绝缘体材料。可以执行X射线分析以检测缺陷,随后引线键合到半导体管芯的端子,并且在半导体管芯被固定并有线连接到半导体管芯衬底(比如,如上所述的第一衬底102和第二衬底104)后对电路进行电气检测。
为了组装母线衬底,可以使用超声波焊接将母线附接至图案化金属层,该图案化金属层固定到绝缘板,比如氧化铝或氮化铝。如上所述,用于母线衬底的绝缘板可以由更坚固的材料形成,并且可以比半导体管芯衬底更厚。因此,由于母线衬底的更大稳健性,超声波焊接操作可以以高产率执行。
有利地,根据一些实施例,用于母线附接的超声波焊接可以与模块组装分开并远离半导体芯片执行,因此防止在该焊接过程中半导体芯片的颗粒污染,并且使得能够在模块的外部检查或检测母线附接。
为了完成组装,各种半导体衬底以及母线衬底固定至基板,比如通过焊接。各种衬底的布置可以如图1A所示,其中母线衬底(第三衬底106)设置在相对的半导体管芯衬底(第一衬底102和第二衬底104)之间。
接下来,电连接器(夹具)(参见连接器128和连接器129)可以钎焊在半导体衬底和母线衬底之间。特别地,连接器被钎焊到设置在相应半导体衬底上的图案化金属层(参见第一衬底102和第二衬底104)。钎焊操作经由母线衬底上的图案化金属层和已焊接到图案化金属层的母线,在设置在半导体管芯衬底上的半导体芯片与半导体器件封装件外部的部件之间建立电气连接。
可选地,在进一步的实施例中,半导体衬底和母线衬底的这些连接可以通过引线键合或其他方式来创建,其中最后进行母线的超声波键合。在这些进一步的实施例中,半导体衬底的材料仍然可以不同于母线衬底的材料,从而提供更灵活的方法。
随后,可以根据已知操作进行组装,包括将塑料盖粘合至基板,填充凝胶,添加塑料插入件和螺钉,并执行最终测试。
表格I
转到图2,示出了半导体器件封装件100的变型的俯视图,其示出为半导体器件封装件200。在这种情况下,半导体器件封装件200可以包括半导体器件封装件100的上述部件,其中类似部件被标记为相同。应当注意,布线204示出以说明将半导体管芯132连接至第一图案化金属层122以及将半导体管芯134连接至第二图案化金属层124的示例性导线图案。
尽管上述实施例已描述了具有两个相对的半导体管芯衬底的半导体器件封装件,但在其他实施例中,半导体器件封装件可以包括四个半导体管芯衬底、六个半导体管芯衬底等。在这些附加实施例中,如上所述,母线衬底单独地设置在相对的半导体衬底之间,以支撑直接焊接到母线衬底的母线。图3A描绘了一个此类实施例,其中半导体器件封装件144包括两对半导体管芯衬底,每一对由母线衬底(示出为第三衬底106)分开,所有衬底固定至基板101,其中所示衬底已在上文中进行了描述。
在本公开的另一个实施例中,多对衬底可以联接到保持母线的一个中心衬底。图3B描绘了根据本公开的附加实施例的半导体器件衬底组件150,其中包含半导体功率芯片的衬底对连接至中心母线衬底156。设置在中心母线衬底156的一侧上的衬底102A和衬底102B可以与上述第一衬底102基本相同。设置在中心母线衬底156的第二侧上的衬底104A和衬底104B可以与上述第二衬底104基本相同,并且在一些实施例中可以与衬底102A和衬底104A相同。在这种配置中,对于给定数量的衬底和给定数量的半导体芯片,减少了部件的数量,并且能够避免在单独母线衬底之间使用互连件。特别地,栅极连接可以在中心母线衬底156上运行,以及发射极和集电极感测连接。这种配置避免在钎焊之后进行引线键合的任何必要性,因此能够在将衬底钎焊到基板之前进行母线焊接。
根据本公开的附加实施例,在半导体芯片衬底上提供的图案化金属层厚度(比如铜层厚度)可以不同于在母线衬底上提供的图案化金属层厚度。应当注意,使用相对较厚的铜可能有利于母线附接,同时增加了在半导体芯片衬底上的图案化金属层结构中的图案化精细图案的难度。
可选地,在半导体芯片下方增加铜厚度可以增加更好的热性能和横向导电性,同时保持母线下方的铜厚度允许焊接参数保持相同。在任一情况下,母线衬底与半导体衬底的分离允许独立地选择图案化铜金属层厚度,从而可以优化衬底器件组件的其他方面。图4描绘了根据本公开的实施例的工艺流程400。在框402,第一衬底固定至基板,其中第一衬底包括第一绝缘板、设置在第一绝缘板上的第一图案化金属层、以及设置在第一图案化金属层上的第一组半导体管芯。
在框404,将与第一衬底分离的第二衬底固定到基板,其中第二衬底包括第二绝缘板、设置在第二绝缘板上的第二图案化金属层和设置在第二图案化金属层上的第二组半导体管芯。在各种实施例中,第一衬底可以与第二衬底类似或衬底类型相同。作为示例,第一绝缘板和第二绝缘板可以具有相同尺寸,并且可以由相同的材料形成。第一图案化金属层可以具有与第一图案化金属层相同的形状和总体尺寸,可以由相同的材料形成等。第一组半导体管芯与第二组半导体管芯在各个管芯对于每组是相同的、布置是相同的等方面相同。
在框406,第三衬底固定至基板并位于第一衬底和第二衬底之间,并且包括第三绝缘板。在一些实施例中,与第一绝缘板和第二绝缘板相比,第三衬底可以具有不同的厚度、不同的材料组成或两者。在其他实施例中,第三绝缘板可以具有与第一绝缘板和第二绝缘板相同的厚度。作为示例,第一绝缘板和第二绝缘板可以由高导热性的薄电绝缘体形成,比如氮化硅,而第三绝缘板由氧化铝或氮化铝制成的较厚板形成。实施例不限于本文。因此,衬底的组装允许在稳健的焊接工艺中直接在第三衬底上形成母线,同时不会干扰第一衬底和第二衬底。
应当注意,在不同实施例中,框402、404和406的操作可以以任何顺序执行,并且通常不同的衬底可以在相同的一般操作中“同时”固定至基板。
在工艺流程的另一个变型中,所有衬底的衬底材料都相同。在工艺流程中,在将衬底钎焊到基板之前,母线可以附接到母线衬底(第三衬底)。
尽管已参考某些实施例公开了本实施例,但在不脱离如所附权利要求中限定的本公开的领域和范围的情况下,可以对所描述的实施例进行许多修改、变更和改变。因此,本实施例不限于所描述的实施例,并且可以具有由所附权利要求及其等同物的语言定义的全部范围。
Claims (20)
1.一种半导体器件衬底组件,包括:
第一衬底,所述第一衬底包括:
第一绝缘板;以及
第一图案化金属层,所述第一图案化金属层设置在所述第一绝缘板上,其中,所述第一绝缘板包括第一材料和第一厚度;
第二衬底,所述第二衬底包括:
第二绝缘板;以及
第二图案化金属层,所述第二图案化金属层设置在所述第二绝缘板上,其中,所述第二绝缘板包括所述第一材料和第一厚度;以及
第三衬底,所述第三衬底设置在所述第一衬底和第二衬底之间,包括:
第三绝缘板;以及
第三图案化金属层,所述第三图案化金属层设置在所述第三绝缘板上,其中,所述第三绝缘板包括第二材料和第二厚度,其中所述第二材料和第二厚度中的至少一个分别不同于所述第一材料和第一厚度。
2.根据权利要求1所述的半导体器件衬底组件,所述第一绝缘板和第二绝缘板包括具有第一热导率的第一绝缘体材料,并且所述第三绝缘板包括具有小于所述第一热导率的第二热导率的第二绝缘体材料,同时具有抵抗母线附接工艺的机械应力的更稳固的机械性能。
3.根据权利要求2所述的半导体器件衬底组件,所述第一绝缘体材料包括氮化硅或氮化铝,且所述第二绝缘体材料包括氮化铝或氧化铝。
4.根据权利要求1所述的半导体器件衬底组件,其中,所述第二厚度大于所述第一厚度。
5.根据权利要求1所述的半导体器件衬底组件,其中,所述第一图案化金属层和所述第二图案化金属层包括第一层厚度,并且其中所述第三图案化金属层包括不同于所述第一层厚度的第二层厚度。
6.根据权利要求1所述的半导体器件衬底组件,所述第一图案化金属层和所述第二图案化金属层成形为容纳设置在其上的多个半导体管芯,并且所述第三图案化金属层包括多个图案化结构以容纳设置在其上的母线组件。
7.根据权利要求1所述的半导体器件衬底组件,还包括基板,其中,所述第一衬底、第二衬底和第三衬底设置在所述基板上。
8.根据权利要求1所述的半导体器件衬底组件,进一步包括:
第四衬底,所述第四衬底邻近所述第一衬底设置在所述第三衬底的第一侧上;以及
第五衬底,所述第五衬底邻近所述第二衬底设置在所述第三衬底的第二侧上。
9.一种半导体器件封装件,包括:
第一衬底,所述第一衬底包括:
第一绝缘板;和
第一图案化金属层,所述第一图案化金属层设置在所述第一绝缘板上;以及
第一组半导体管芯,所述第一组半导体管芯设置在所述第一图案化金属层上;
第二衬底,所述第二衬底包括:
第二绝缘板;
第二图案化金属层,所述第二图案化金属层设置在所述第二绝缘板上;以及
第二组半导体管芯,所述第二组半导体管芯设置在所述第二图案化金属层上;
第三衬底,所述第三衬底设置在所述第一衬底和第二衬底之间,包括:
第三绝缘板;以及
第三图案化金属层,所述第三图案化金属层设置在所述第三绝缘板上;以及
一组母线,所述组母线连接至所述第三图案化金属层。
10.根据权利要求9所述的半导体器件封装件,所述第一绝缘板和所述第二绝缘板包括具有第一厚度的第一绝缘体材料,并且所述第三绝缘板包括具有第二厚度的第二绝缘体材料,所述第二厚度大于所述第一厚度。
11.根据权利要求10所述的半导体器件封装件,所述第一绝缘体材料包括氮化硅、氮化铝或氧化铝,且所述第二绝缘体材料包括氮化铝或氧化铝。
12.根据权利要求9所述的半导体器件封装件,进一步包括:
第一组半导体管芯,所述第一组半导体管芯设置在所述第一图案化金属层上;
第二组半导体管芯,所述第二组半导体管芯设置在所述第二图案化金属层上;
一组母线,所述组母线连接至所述第三图案化金属层;以及
第一组连接器和第二组连接器,所述第一组连接器将所述第三图案化金属层电连接到所述第一图案化金属层,所述第二组连接器将所述第三图案化金属层电连接到所述第二图案化金属层。
13.根据权利要求12所述的半导体器件封装件,其中,所述第一组半导体管芯和第二组半导体管芯包括一组功率半导体器件。
14.根据权利要求9所述的半导体器件封装件,进一步包括基板,其中所述第一衬底、第二衬底和第三衬底设置在所述基板上。
15.根据权利要求10所述的半导体器件封装件,所述第一绝缘体材料包括氮化硅或氮化铝,且所述第二绝缘体材料包括氮化铝或氧化铝。
16.根据权利要求9所述的半导体器件封装件,所述第一绝缘板和第二绝缘板包括具有第一热导率的第一绝缘体材料,且所述第三绝缘板包括具有第二热导率的第二绝缘体材料,所述第二热导率小于所述第一热导率。
17.一种形成半导体封装件的方法,包括:
将第一衬底固定在基板上,所述第一衬底包括第一绝缘体材料,以及第一图案化金属层;
将第二衬底固定在所述基板上,所述第二衬底包括所述第一绝缘体材料,以及第二图案化金属层;并且
在所述第一衬底和第二衬底之间,将第三衬底固定在所述基板上,所述第三衬底包括不同于所述第一绝缘体材料的第二绝缘体材料,并且还包括第三图案化金属层。
18.根据权利要求17所述的方法,进一步包括:
将第一多个半导体芯片固定在所述第一图案化金属层上;以及
将第二多个半导体芯片固定在所述第二图案化金属层上。
19.根据权利要求17所述的方法,还包括:将母线连接到所述第三图案化金属层。
20.根据权利要求19所述的方法,其中,将母线连接到所述第三图案化金属层包括在将所述第三衬底固定到所述基板之前将所述母线焊接至所述第三图案化金属层。
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