CN114999415A - Liquid crystal display device and mainboard thereof - Google Patents
Liquid crystal display device and mainboard thereof Download PDFInfo
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- CN114999415A CN114999415A CN202210560764.0A CN202210560764A CN114999415A CN 114999415 A CN114999415 A CN 114999415A CN 202210560764 A CN202210560764 A CN 202210560764A CN 114999415 A CN114999415 A CN 114999415A
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 67
- 238000001514 detection method Methods 0.000 claims abstract description 23
- 230000002265 prevention Effects 0.000 claims abstract description 17
- 238000004891 communication Methods 0.000 claims abstract description 16
- 238000006243 chemical reaction Methods 0.000 claims description 15
- 102100029361 Aromatase Human genes 0.000 claims description 12
- 101000919395 Homo sapiens Aromatase Proteins 0.000 claims description 12
- 238000012360 testing method Methods 0.000 claims description 10
- 241001649012 Cypselea humifusa Species 0.000 claims description 8
- HOMBCMTVOCZMMX-UHFFFAOYSA-N panal Natural products CC1CC(=O)C(C2C=C(CC(O)C12)C(=O)O)C(=C)C=O HOMBCMTVOCZMMX-UHFFFAOYSA-N 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 3
- 238000013461 design Methods 0.000 description 10
- 230000002093 peripheral effect Effects 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 5
- 101000805729 Homo sapiens V-type proton ATPase 116 kDa subunit a 1 Proteins 0.000 description 4
- 101000854879 Homo sapiens V-type proton ATPase 116 kDa subunit a 2 Proteins 0.000 description 4
- 101000854873 Homo sapiens V-type proton ATPase 116 kDa subunit a 4 Proteins 0.000 description 4
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- 238000010586 diagram Methods 0.000 description 3
- -1 CPV2 Proteins 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G3/2096—Details of the interface to the display terminal specific for a flat panel
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Abstract
The invention discloses a liquid crystal display device and a mainboard thereof, wherein the liquid crystal display device comprises: the system comprises a main board, a logic adapter board connected with the main board and a liquid crystal display screen connected with the logic adapter board; the mainboard comprises a first interface and a second interface; the logic adapter plate is provided with a third interface, a fourth interface and a fifth interface; the logic adapter board is connected with the first interface or the second interface through the third interface so as to be connected with the main board, and is connected with the liquid crystal display screen through the fourth interface and the fifth interface; the first interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area, a display data area and a data communication area; the second interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area and a display data area. The invention is generally used for various liquid crystal display screens and reduces the interface cost.
Description
Technical Field
The invention relates to the technical field of display, in particular to a liquid crystal display device and a mainboard thereof.
Background
The existing TV ultra-high definition display screen driving circuit mainly comprises three modes: A. the independent Tcon board mode adopts a V-BY-ONE standard interface for input, and a screen manufacturer self-defines screen interface output; B. in an Open Cell mode, a Tcon IC is integrated in a main Chip (System On Chip, SOC), and is integrated On a main board together with a peripheral PM/GAMMA/LEVEL SHIFT circuit (level conversion unit), and then is matched with a screen interface to output an access screen; C. the mode of the TCONLESS adapter board is that Tconic is integrated in SOC, a peripheral PM/GAMMA/LEVEL SHIFT circuit of TCON is integrated on the adapter board, the main board and the adapter board are connected through a special interface, and the adapter board is output through a custom screen interface of a screen manufacturer.
Aiming at a TCONLESS adapter plate mode, a unified design scheme which can be compatible with interface definitions of various screen interfaces and has complete function requirements does not exist in the existing market so as to solve the problem of universality of an integrated circuit board.
Accordingly, the prior art is yet to be improved and developed.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, an object of the present invention is to provide a liquid crystal display device and a main board thereof, so as to solve the problem that there is no unified design scheme compatible with interface definitions of various screen interfaces and complete functional requirements in the TCONLESS adapter board mode, so that the integrated circuit board cannot be used universally.
The technical scheme of the invention is as follows:
a liquid crystal display device, comprising: the system comprises a main board, a logic adapter board connected with the main board and a liquid crystal display screen connected with the logic adapter board; wherein the content of the first and second substances,
the mainboard comprises a first interface and a second interface;
the logic adapter plate is provided with a third interface, a fourth interface and a fifth interface;
the logic adapter board is connected with the first interface or the second interface through the third interface so as to be connected with the mainboard, and is connected with the liquid crystal display screen through the fourth interface and the fifth interface;
the first interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area, a display data area and a data communication area;
the second interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area and a display data area.
In a further configuration of the present invention, the first pin to the eighth pin of the first interface are defined as VCC; a ninth pin of the first interface is defined as NC; the tenth pin to the twelfth pin of the first interface are defined as GND; the thirteenth pin and the fourteenth pin of the first interface are defined as P _ SDA and P _ SCL respectively; a fifteenth pin and a sixteenth pin of the first interface are respectively defined as TEST _ IO and VB1_ HPN; a seventeenth leg of the first interface is defined as Panal _ EN; the eighteenth pin to the twenty-third pin of the first interface are respectively defined as TCON _2, TCON _1, TCON _ CPV2, TCON _ CPV1, TCON _ STV2 and TCON _ STV 1; a twenty-fourth pin of the first interface is defined as LOCKOUT; twenty-fifth to sixty-sixth pins of the first interface are respectively defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, DATA +, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+, GND; the sixty-eight pins of the first interface are defined as FLASH _ WP, FLASH _ DO, FLASH _ CS, FLASH _ DI, GND, FLASH _ CLK and GND respectively.
In a further configuration of the present invention, the first pin to the seventh pin of the second interface are defined as VCC; an eighth pin of the first interface is defined as NC; the ninth pin to the eleventh pin of the first interface are defined as GND; a twelfth leg and a thirteenth leg of the first interface are respectively defined as P _ SDA and P _ SCL; a fourteenth pin and a fifteenth pin of the first interface are respectively defined as TEST _ IO and VB1_ HPN; a sixteenth pin of the first interface is defined as Panal _ EN; the seventeenth pin to the twenty-second pin of the first interface are respectively defined as TCON _2, TCON _1, TCON _ CPV2, TCON _ CPV1, TCON _ STV2 and TCON _ STV 1; a twenty-third pin of the first interface is defined as LOCKOUT; the twenty-fourth to sixty pins of the first interface are defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, DATA +, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+, and GND, respectively.
According to a further arrangement of the present invention, a flexible flat cable is used for connecting the third interface and the first interface or the second interface; and the liquid crystal display screen is connected with the fourth interface and the fifth interface by adopting flexible flat cables.
In a further aspect of the present invention, the main board further includes: and the VBO interface is respectively connected with the first interface and the second interface.
In a further aspect of the present invention, the main board further includes: and the main chip is respectively connected with the first interface and the second interface.
In a further aspect of the present invention, the logic adapter board further comprises: the display device comprises a power management unit, a display parameter unit and a power conversion unit, wherein the power management unit, the display parameter unit and the output end of the power conversion unit are connected with the liquid crystal display screen.
In a further configuration of the present invention, the first interface and the second interface are disposed on the motherboard in an overlapping manner.
A liquid crystal display mainboard comprises a first interface and a second interface, wherein the first interface and the second interface are arranged on the liquid crystal display mainboard in an overlapping mode; wherein, the first and the second end of the pipe are connected with each other,
the first interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area, a display data area and a data communication area;
the second interface is provided with a power supply area, a short-circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area and a display data area.
In a further configuration of the present invention, the first pin to the eighth pin of the first interface are defined as VCC; a ninth pin of the first interface is defined as NC; the tenth to twelfth pins of the first interface are defined as GND; the thirteenth pin and the fourteenth pin of the first interface are defined as P _ SDA and P _ SCL respectively; a fifteenth pin and a sixteenth pin of the first interface are respectively defined as TEST _ IO and VB1_ HPN; a seventeenth leg of the first interface is defined as Panal _ EN; the eighteenth pin to the twenty-third pin of the first interface are respectively defined as TCON _2, TCON _1, TCON _ CPV2, TCON _ CPV1, TCON _ STV2 and TCON _ STV 1; a twenty-fourth pin of the first interface is defined as LOCKOUT; the twenty-fifth to sixteenth pins of the first interface are defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, DATA +, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+, GND, respectively; the sixteenth pin to the sixteenth pin of the first interface are respectively defined as FLASH _ WP, FLASH _ DO, FLASH _ CS, FLASH _ DI, GND, FLASH _ CLK and GND;
the first pin to the seventh pin of the second interface are defined as VCC; an eighth pin of the first interface is defined as NC; the ninth pin to the eleventh pin of the first interface are defined as GND; a twelfth leg and a thirteenth leg of the first interface are defined as P _ SDA and P _ SCL, respectively; a fourteenth pin and a fifteenth pin of the first interface are respectively defined as TEST _ IO and VB1_ HPN; a sixteenth pin of the first interface is defined as Panal _ EN; the seventeenth pin to the twenty-second pin of the first interface are respectively defined as TCON _2, TCON _1, TCON _ CPV2, TCON _ CPV1, TCON _ STV2 and TCON _ STV 1; a twenty-third pin of the first interface is defined as LOCKOUT; the twenty-fourth pin to the sixteenth pin of the first interface are respectively defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, DATA +, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+ and GND.
The invention provides a liquid crystal display device and a mainboard thereof, wherein the liquid crystal display device comprises: the system comprises a main board, a logic adapter board connected with the main board and a liquid crystal display screen connected with the logic adapter board; the mainboard comprises a first interface and a second interface; the logic adapter plate is provided with a third interface, a fourth interface and a fifth interface; the logic adapter board is connected with the first interface or the second interface through the third interface so as to be connected with the mainboard, and is connected with the liquid crystal display screen through the fourth interface and the fifth interface; the first interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area, a display data area and a data communication area; the second interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area and a display data area. The invention can be compatible with the interface definition of each liquid crystal display screen by defining the pins of the first interface and the second interface on the mainboard, so that the mainboard is universal for each liquid crystal display screen. In addition, the mainboard can select first interface or second interface according to liquid crystal display's interface demand, and the mainboard end can remain unchanged, only needs to correspond the requirement that different logic control panels of change can satisfy different liquid crystal display interfaces, and has reduced the interface cost.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic view of a liquid crystal display device according to the present invention.
Fig. 2 is a pin diagram of the first interface of the present invention.
Fig. 3 is a pin diagram of a second interface of the present invention.
Fig. 4 is a schematic structural diagram of the first interface and the second interface layout on the PCB according to the present invention.
The various symbols in the drawings: 100. a main board; 101. a first interface; 102. a second interface; 103. a main chip; 104. a VBO interface; 200. a logic patch panel; 201. a third interface; 202. a fourth interface; 203. a fifth interface; 204. a power management unit; 205. a display parameter unit; 206. a power conversion unit; 300. a liquid crystal display screen; 400. a flexible flat cable.
Detailed Description
The invention provides a liquid crystal display device and a mainboard thereof, wherein the liquid crystal display device can be a device with a liquid crystal display screen such as a television, a display and the like, and is particularly suitable for the application of a 4K ultra-high definition display screen in the television.
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the embodiments and claims, the articles "a", "an", "the" and "the" may include plural forms as well, unless the context specifically dictates otherwise. If there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature.
It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The inventor researches and discovers that various custom interface modes of the screen input end exist at present, such as EPI, CEDS, CHPI, USI-T, CSPI and other protocols. Because display screen glass manufacturers at home and abroad do not form a uniform standard for the interface of the screen input end, the realization scheme interfaces of the driving circuit are different, and the integrated circuit board signal processing and screen driving mode is adopted, so that circuits with different interfaces need to be developed, the problems of low development efficiency, poor universality of the integrated circuit board and the like are caused, and the development cost is overhigh.
Aiming at a TCONLESS adapter plate mode, a unified design scheme which can be compatible with interface definitions of various screen interfaces and has complete function requirements does not exist in the existing market so as to solve the problem of universality of an integrated circuit board. The existing interface definition is redundant, the practical application is not simplified, the circuit design is complex, and the cost is wasted to a certain extent.
In view of the above technical problems, the present invention provides a liquid crystal display device and a motherboard thereof, which can be compatible with interface definitions of various liquid crystal displays by defining pins of a first interface and a second interface on the motherboard, so that the motherboard is generally used for various liquid crystal displays. In addition, the mainboard can select first interface or second interface according to liquid crystal display's interface demand, and the mainboard end can remain unchanged, only needs to correspond the requirement that different logic control panels of changing can satisfy different liquid crystal display interfaces for the circuit of interface is simpler, and has reduced the interface cost.
Referring to fig. 1 to fig. 3, the present invention provides a preferred embodiment of a liquid crystal display device.
As shown in fig. 1 to 3, the present invention provides a liquid crystal display device, which includes: the display device comprises a main board 100, a logic adapter board 200 connected with the main board 100 and a liquid crystal display screen 300 connected with the logic adapter board 200; the motherboard 100 includes a first interface 101 and a second interface 102; the logic adapter board 200 is provided with a third interface 201, a fourth interface 202 and a fifth interface 203; the logic adapter board 200 is connected to the first interface 101 or the second interface 102 through the third interface 201 to be connected to the motherboard 100, and is connected to the liquid crystal display 300 through the fourth interface 202 and the fifth interface 203; the first interface 101 is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area, a display data area and a data communication area; the second interface 102 has a power supply area, a short-circuit prevention area, a ground area, a data burning area, an interface detection area, an enable control area, a driving control area, a locking area, and a display data area.
Specifically, the utility model provides a liquid crystal display device adopts the TCONLESS keysets modular, adopts logic keysets (TCONLESS BOARD)200 promptly, logic keysets 200 passes through third interface 201 with first interface 101 or second interface 102 on the mainboard 100 are connected to the realization is connected with mainboard 100, wherein the pin of third interface 201 with the pin of first interface 101 correspond or with the pin of second interface 102 corresponds. The first interface 101 and the second interface 102 are provided with a power supply area, a short-circuit prevention area, a ground area, a data burning area, an interface detection area, an enable control area, a drive control area, a locking area and a display data area, and the first interface 101 is further provided with a data communication area. It can be seen that the interface of the motherboard 100 covers the communication control function and Demura (image non-uniformity elimination) function required by the lcd 300, and can support the data signal, clk signal, driving control signal and power supply line required by the interfaces such as EPI, CEDS, CHPI, USI-T, CSPI, etc., so that the interface definition of each lcd 300 can be compatible, and the motherboard 100 can be commonly used for each lcd.
Wherein, first interface 101 has 68 pins, and second interface 102 has 60 pins, in practical application, can be according to liquid crystal display 300's interface demand selects first interface 101 or second interface 102 (if liquid crystal display 300 needs to do the Demura function, then selects first interface 101, otherwise selects second interface 102), mainboard 100 end can remain unchanged, only needs to correspond the different logic control board 200 of change, and the screen parameter that the software adaptation corresponds reaches the control signal chronogenesis, can satisfy the requirement of different liquid crystal display interfaces to realize the drive of many liquid crystal display 300 and show, simplified circuit design and interface definition, and reduced interface cost. The first interface 101 and the second interface 102 may be compatible with 43 inch-75 inch 4K ultra-high-definition liquid crystal display applications.
Referring to fig. 1, in some embodiments, a main chip 103 is disposed on the main board 100, and the main chip 103 is connected to the first interface 101 and the second interface 102 respectively.
Referring to fig. 1, the logic adapter board 200 further includes: the display device comprises a power management unit 204, a display parameter unit 205 and a power conversion unit 206, wherein the output ends of the power management unit 204, the display parameter unit 205 and the power conversion unit 206 are connected with the liquid crystal display screen 400.
The main chip 103 may perform data burning on a peripheral Power Management Unit (PMU)204, a peripheral display parameter unit (Gamma)205, and a peripheral power conversion unit (Level fix) 206 by using I2C communication, so as to provide a burning use.
Referring to fig. 1, in some embodiments, the main board 100 further includes: the VBO (V-BY-ONE) interface, the VBO interface 104 is connected to the first interface 101 and the second interface 102, and through cooperation of software setting, data can be converted into data of the existing VBO interface 104 for transmission, so that signal detection using the motherboard 100 is realized.
Referring to fig. 1 and fig. 2, in some embodiments, the first pin to the eighth pin (i.e., the power supply area) of the first interface 101 are defined as VCC, and the power supply of the circuit design satisfies 8 current paths of 4A;
the ninth pin (i.e., the short-circuit prevention area) of the first interface 101 is defined as NC, and can be used for preventing the VCC12V or the ground terminal GND from being short-circuited. The tenth pin to the twelfth pin (ground area) of the first interface 101 are defined as GND;
the thirteenth pin and the fourteenth pin (i.e., the data burning area) of the first interface 101 are communication signal pins defined as P _ SDA and P _ SCL, respectively, the main chip 103 can perform data burning on the peripheral power management unit 204, the display parameter unit 205, and the power conversion unit 206 by using I2C communication to provide burning use, and the pull-up 3.3V can be reserved by the main chip 103 or the logic adapter board 200;
a fifteenth pin and a sixteenth pin (i.e., interface detection areas) of the first interface 101 are respectively defined as TEST _ IO and VB1_ HPN, and are reserved as interface detection pins of the motherboard 100, and different screen driving data is converted into existing standard V-BY-ONE interface data through an external module, so as to perform circuit detection;
a seventeenth pin (enabling control area) of the first interface 101 is defined as pal _ EN, and is connected to an EN pin of the power management unit 204, and is used for enabling control of the power management unit 204;
eighteenth pin to twenty-third pin (driving control area) of the first interface 101 are respectively defined as TCON _2, TCON _1, TCON _ CPV2, TCON _ CPV1, TCON _ STV2, and TCON _ STV1, and are used for controlling IO ports for 6ch control signals required by the panel driving power conversion unit 206, and 6 main chips 103 need to be connected to control the IO ports, corresponding to STV1, STV2/TE/CLR, CPV1, CPV2, LC1, LC2/RST/CLR, where STV2 can be multiplexed with TE and CLR of the panel, and LC2 can be multiplexed with RST and CLR of the panel;
the twenty-fourth pin (locking region) of the first interface 101 is a LOCKOUT signal pin, defined as LOCKOUT, transmitted from the LCD 300 end back to the main chip 103, and used as a LOCK signal during VBO conversion;
twenty-fifth to sixty-sixth pins (display DATA areas) of the first interface 101 are respectively defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, DATA +, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+, GND, display DATA signal pins and signal ground GND for the liquid crystal display 300, and all 12 sets of DATA pairs required by screen interfaces such as EPI, cepi, uspi-T, CSPI are compatible, and can support transmission rates of 1.5Gbps, 3.0Gbps and 4.0 Gbps;
the sixteenth pin to the sixteenth pin (data communication area) of the first interface 101 are respectively defined as FLASH _ WP, FLASH _ DO, FLASH _ CS, FLASH _ DI, GND, FLASH _ CLK and GND, and are used by the liquid crystal display 300 with the Demura function, where the FLASH _ DO corresponds to the SPI _ DO of the main chip 103 and the SPI _ DI of the liquid crystal display end, and the FLASH _ DI corresponds to the SPI _ DI of the main chip 103 and the SPI _ DO of the liquid crystal display end.
Referring to fig. 1 and fig. 3, in some embodiments, the first pin to the seventh pin (i.e., the power supply area) of the second interface 102 are defined as VCC, and the circuit design power supply satisfies 8 current paths of 3.5A;
the eighth pin of the first interface 101 is defined as NC (i.e., short-circuit prevention area), and can be used to prevent VCC12V or ground GND from short-circuit. The tenth pin to the twelfth pin (ground area) of the first interface 101 are defined as GND;
the ninth pin to the eleventh pin (ground region) of the first interface 101 are defined as GND;
the twelfth pin and the thirteenth pin (i.e., the data burning area) of the first interface 101 are communication signal pins respectively defined as P _ SDA and P _ SCL, the main chip 103 can use I2C for communication to burn peripheral circuits, the main chip 103 can use I2C for communication to burn data to the peripheral power management unit 204, the display parameter unit 205 and the power conversion unit 206 for use, and the pull-up 3.3V can be reserved by the main chip 103 or the logic adapter board 200;
a fourteenth pin and a fifteenth pin (i.e., interface detection areas) of the first interface 101 are respectively defined as TEST _ IO and VB1_ HPN, and are reserved as interface detection pins of the motherboard 100, and different screen driving data is converted into existing standard V-BY-ONE interface data through an external module, so as to perform circuit detection;
a sixteenth pin (enabling control area) of the first interface 101 is defined as pal _ EN, and is connected with an EN pin of the power management unit 204, and is used for enabling control of the power management unit 204;
the seventeenth pin to the twenty second pin (driving control area) of the first interface 101 are respectively defined as TCON _2, TCON _1, TCON _ CPV2, TCON _ CPV1, TCON _ STV2, and TCON _ STV1, and are used for controlling 6ch control signals required by the panel driving power conversion unit 206, and 6 main chips 103 need to be connected to control IO ports, and correspond to STV1, STV2/TE/CLR, CPV1, CPV2, LC1, and LC2/RST/CLR, where STV2 can be multiplexed with TE and CLR of a panel to do work and select one from three, and LC2 can be multiplexed with RST and CLR of a panel to do work and select one from three;
the twenty-third pin (locking region) of the first interface 101 is a LOCKOUT signal pin, defined as LOCKOUT, transmitted from the end of the liquid crystal display 300 back to the main chip 103, and used as a LOCK signal during VBO conversion;
the twenty-fourth to sixteenth pins (display DATA areas) of the first interface 101 are respectively defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, DATA +, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+, and GND, and all 12 sets of DATA required for the screen interfaces of the liquid crystal display DATA signal pin and signal ground GND, compatible with EPI, CEDS, CHPI, USI-T, CSPI, etc., and can support 1.5Gbps, 3.0Gbps, 4.0Gbps transmission rate.
Referring to fig. 1, in a further implementation manner of an embodiment, a Flexible Flat Cable (FFC) 400 is used to connect between the third interface 201 and the first interface 101 or between the third interface 201 and the second interface 102; the liquid crystal display 300 is connected with the fourth interface 202 and the fifth interface 203 by a flexible flat cable 400.
Specifically, the first interface 101, the second interface 102, the third interface 201, the fourth interface 202, and the fifth interface 203 are flexible flat cable interfaces (FFC interfaces), the flexible flat cable 400 is used for connecting between the third interface 201 and the first interface 101 or between the third interface 201 and the second interface 102, when the third interface 201 is connected to the first interface 101, a 68pin flexible flat cable is used, and when the third interface 201 is connected to the second interface 102, a 60pin flexible flat cable is used. The liquid crystal display 300 is connected with the fourth interface 202 and the fifth interface 203 by a flexible flat cable 400.
Referring to fig. 1 and fig. 4, in a further implementation manner of an embodiment, the first interface 101 and the second interface 102 are disposed on the motherboard 100 in an overlapping manner.
Specifically, when the first interface 101 and the second interface 102 are applied, the packages of the two interfaces may adopt the same type specification, and the interfaces may be stacked by pcslayout at the end of the motherboard 100, so as to reduce the PCB area and the material cost of the motherboard 100.
In summary, the liquid crystal display device provided by the invention has the following beneficial effects:
the invention is used as a brand-new multifunctional interface definition, can be designed jointly with screen manufacturers and becomes a new unified standard in the industry;
the new interface definition is compatible with all data transmission signal pairs required BY the existing screen drive, has a Demura function, is regulated and controlled BY I2C, can be completely adapted to 4K ultra-high-definition liquid crystal display screens of different manufacturers at home and abroad, can support 43-75-inch 4K ultra-high-definition liquid crystal displays of mainstream manufacturers at home and abroad, is matched with software setting, and can also convert data into the existing V-BY-ONE interface data transmission and use mainboard signal detection;
the design of the invention solves the problem that the mainboard uses different display screens to drive display compatibility, and when the screen is selected and matched, an interface circuit is not required to be changed. The practical application circuit design is nimble, can select 68pin or 60pin interface according to different screen demands, and 68pin +60 pin's interface can be compatible to be placed on PCBlayout, saves circuit design area and material cost, is applicable to that any Tconless keysets display screen circuit scheme can all use, for example the screen display drive of smart television product.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (10)
1. A liquid crystal display device, comprising: the system comprises a main board, a logic adapter board connected with the main board and a liquid crystal display screen connected with the logic adapter board; wherein the content of the first and second substances,
the mainboard comprises a first interface and a second interface;
the logic adapter plate is provided with a third interface, a fourth interface and a fifth interface;
the logic adapter board is connected with the first interface or the second interface through the third interface so as to be connected with the mainboard, and is connected with the liquid crystal display screen through the fourth interface and the fifth interface;
the first interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area, a display data area and a data communication area;
the second interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area and a display data area.
2. The LCD device of claim 1, wherein the first pin to the eighth pin of the first interface are defined as VCC; a ninth pin of the first interface is defined as NC; the tenth pin to the twelfth pin of the first interface are defined as GND; the thirteenth pin and the fourteenth pin of the first interface are respectively defined as P _ SDA and P _ SCL; the fifteenth pin and the sixteenth pin of the first interface are respectively defined as TEST _ IO and VB1_ HPN; a seventeenth leg of the first interface is defined as Panal _ EN; the eighteenth to twenty-third pins of the first interface are respectively defined as TCON _2, TCON _1, TCON _ CPV2, TCON _ CPV1, TCON _ STV2 and TCON _ STV 1; a twenty-fourth pin of the first interface is defined as LOCKOUT; the twenty-fifth pin to the sixty-first pin of the first interface are respectively defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, DATA +, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+, and GND; the sixty-eight pins of the first interface are defined as FLASH _ WP, FLASH _ DO, FLASH _ CS, FLASH _ DI, GND, FLASH _ CLK and GND respectively.
3. The LCD device according to claim 1, wherein the first through seventh pins of the second interface are defined as VCC; an eighth pin of the first interface is defined as NC; the ninth pin to the eleventh pin of the first interface are defined as GND; a twelfth leg and a thirteenth leg of the first interface are defined as P _ SDA and P _ SCL, respectively; a fourteenth pin and a fifteenth pin of the first interface are respectively defined as TEST _ IO and VB1_ HPN; a sixteenth pin of the first interface is defined as Panal _ EN; the seventeenth pin to the twenty-second pin of the first interface are respectively defined as TCON _2, TCON _1, TCON _ CPV2, TCON _ CPV1, TCON _ STV2 and TCON _ STV 1; a twenty-third pin of the first interface is defined as LOCKOUT; the twenty-fourth pin to the sixteenth pin of the first interface are respectively defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, DATA +, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+ and GND.
4. The liquid crystal display device according to claim 1, wherein a flexible flat cable is used for connection between the third interface and the first interface or between the third interface and the second interface; and the liquid crystal display screen is connected with the fourth interface and the fifth interface by adopting flexible flat cables.
5. The liquid crystal display device according to claim 1, wherein the main board further comprises: and the VBO interface is respectively connected with the first interface and the second interface.
6. The liquid crystal display device according to claim 1, wherein the main board further comprises: and the main chip is respectively connected with the first interface and the second interface.
7. The lcd apparatus of claim 1, wherein the logic adapter board further comprises: the display device comprises a power management unit, a display parameter unit and a power conversion unit, wherein the output ends of the power management unit, the display parameter unit and the power conversion unit are connected with the liquid crystal display screen.
8. The liquid crystal display device according to claim 1, wherein the first interface and the second interface are provided on the main board in a superimposed manner.
9. The liquid crystal display mainboard is characterized by comprising a first interface and a second interface, wherein the first interface and the second interface are arranged on the liquid crystal display mainboard in an overlapping manner; wherein the content of the first and second substances,
the first interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area, a display data area and a data communication area;
the second interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area and a display data area.
10. The lcd panel of claim 9, wherein the first pin to the eighth pin of the first interface are defined as VCC; a ninth pin of the first interface is defined as NC; the tenth pin to the twelfth pin of the first interface are defined as GND; the thirteenth pin and the fourteenth pin of the first interface are defined as P _ SDA and P _ SCL respectively; a fifteenth pin and a sixteenth pin of the first interface are respectively defined as TEST _ IO and VB1_ HPN; a seventeenth leg of the first interface is defined as Panal _ EN; the eighteenth pin to the twenty-third pin of the first interface are respectively defined as TCON _2, TCON _1, TCON _ CPV2, TCON _ CPV1, TCON _ STV2 and TCON _ STV 1; a twenty-fourth pin of the first interface is defined as LOCKOUT; twenty-fifth to sixty-sixth pins of the first interface are respectively defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, DATA +, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+, GND; the sixteenth to sixteenth pins of the first interface are respectively defined as FLASH _ WP, FLASH _ DO, FLASH _ CS, FLASH _ DI, GND, FLASH _ CLK and GND;
the first pin to the seventh pin of the second interface are defined as VCC; an eighth pin of the first interface is defined as NC; the ninth pin to the eleventh pin of the first interface are defined as GND; a twelfth leg and a thirteenth leg of the first interface are defined as P _ SDA and P _ SCL, respectively; a fourteenth pin and a fifteenth pin of the first interface are respectively defined as TEST _ IO and VB1_ HPN; a sixteenth pin of the first interface is defined as Panal _ EN; the seventeenth pin to the twenty-second pin of the first interface are respectively defined as TCON _2, TCON _1, TCON _ CPV2, TCON _ CPV1, TCON _ STV2 and TCON _ STV 1; a twenty-third pin of the first interface is defined as LOCKOUT; the twenty-fourth pin to the sixteenth pin of the first interface are respectively defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, DATA +, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+, and GND.
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Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106463098A (en) * | 2016-07-26 | 2017-02-22 | 北京小米移动软件有限公司 | Display device and motherboards applied to the display device |
| CN107241562A (en) * | 2017-07-25 | 2017-10-10 | 四川长虹电器股份有限公司 | Ultra high-definition LCD TV circuit system and interface |
| CN110087008A (en) * | 2019-04-01 | 2019-08-02 | 晶晨半导体(上海)股份有限公司 | A kind of compatible apparatus of Tconless interface |
| CN110381273A (en) * | 2019-06-06 | 2019-10-25 | 深圳康佳电子科技有限公司 | A kind of LCD TV circuit system and interface |
| CN210349267U (en) * | 2019-07-12 | 2020-04-17 | 深圳安时达电子服务有限公司 | Mainboard compatible circuit with built-in TCON |
| CN210722413U (en) * | 2019-12-09 | 2020-06-09 | 深圳创维－Rgb电子有限公司 | Point screen device of MIPI interface secondary screen |
| CN111405202A (en) * | 2020-03-24 | 2020-07-10 | 深圳创维－Rgb电子有限公司 | TCON L ESS mainboard signal conversion device and detection system |
| CN211828058U (en) * | 2020-04-02 | 2020-10-30 | 深圳市洲明科技股份有限公司 | Universal adapter plate and LED display screen comprising same |
| CN112468748A (en) * | 2020-11-06 | 2021-03-09 | 广东长虹电子有限公司 | Adapter plate applied to display screen and display device |
| CN213069082U (en) * | 2020-08-31 | 2021-04-27 | 深圳创维－Rgb电子有限公司 | Detection apparatus for detect TCONLESS mainboard |
| CN112752090A (en) * | 2019-10-31 | 2021-05-04 | 海信视像科技股份有限公司 | Testing device |
| CN213818026U (en) * | 2020-12-04 | 2021-07-27 | 广州晶序达电子科技有限公司 | TCON board and TCONLESS mainboard functional test system |
| CN213987487U (en) * | 2021-01-27 | 2021-08-17 | 深圳市康冠商用科技有限公司 | Mainboard interface expansion circuit and display device |
| CN114120882A (en) * | 2021-12-14 | 2022-03-01 | 惠州视维新技术有限公司 | Display device and method compatible with multiple display panels |
| CN216084272U (en) * | 2021-05-31 | 2022-03-18 | 广州视源电子科技股份有限公司 | TCON module and Tconless screen equipment |
| CN114267310A (en) * | 2021-12-28 | 2022-04-01 | 冠捷显示科技（厦门）有限公司 | Driving device of Tconless display screen |
| US20220139347A1 (en) * | 2020-11-02 | 2022-05-05 | Mediatek Singapore Pte. Ltd. | Mainboard, display device, displaying method, and computer readable storage medium |
| CN216561749U (en) * | 2021-09-13 | 2022-05-17 | 深圳市嘉润原新显科技有限公司 | Display mainboard, display and projection equipment of compatible interface of lying |
-
2022
- 2022-05-23 CN CN202210560764.0A patent/CN114999415B/en active Active
Patent Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106463098A (en) * | 2016-07-26 | 2017-02-22 | 北京小米移动软件有限公司 | Display device and motherboards applied to the display device |
| CN107241562A (en) * | 2017-07-25 | 2017-10-10 | 四川长虹电器股份有限公司 | Ultra high-definition LCD TV circuit system and interface |
| CN110087008A (en) * | 2019-04-01 | 2019-08-02 | 晶晨半导体(上海)股份有限公司 | A kind of compatible apparatus of Tconless interface |
| CN110381273A (en) * | 2019-06-06 | 2019-10-25 | 深圳康佳电子科技有限公司 | A kind of LCD TV circuit system and interface |
| CN210349267U (en) * | 2019-07-12 | 2020-04-17 | 深圳安时达电子服务有限公司 | Mainboard compatible circuit with built-in TCON |
| CN112752090A (en) * | 2019-10-31 | 2021-05-04 | 海信视像科技股份有限公司 | Testing device |
| CN210722413U (en) * | 2019-12-09 | 2020-06-09 | 深圳创维－Rgb电子有限公司 | Point screen device of MIPI interface secondary screen |
| CN111405202A (en) * | 2020-03-24 | 2020-07-10 | 深圳创维－Rgb电子有限公司 | TCON L ESS mainboard signal conversion device and detection system |
| CN211828058U (en) * | 2020-04-02 | 2020-10-30 | 深圳市洲明科技股份有限公司 | Universal adapter plate and LED display screen comprising same |
| CN213069082U (en) * | 2020-08-31 | 2021-04-27 | 深圳创维－Rgb电子有限公司 | Detection apparatus for detect TCONLESS mainboard |
| US20220139347A1 (en) * | 2020-11-02 | 2022-05-05 | Mediatek Singapore Pte. Ltd. | Mainboard, display device, displaying method, and computer readable storage medium |
| CN112468748A (en) * | 2020-11-06 | 2021-03-09 | 广东长虹电子有限公司 | Adapter plate applied to display screen and display device |
| CN213818026U (en) * | 2020-12-04 | 2021-07-27 | 广州晶序达电子科技有限公司 | TCON board and TCONLESS mainboard functional test system |
| CN213987487U (en) * | 2021-01-27 | 2021-08-17 | 深圳市康冠商用科技有限公司 | Mainboard interface expansion circuit and display device |
| CN216084272U (en) * | 2021-05-31 | 2022-03-18 | 广州视源电子科技股份有限公司 | TCON module and Tconless screen equipment |
| CN216561749U (en) * | 2021-09-13 | 2022-05-17 | 深圳市嘉润原新显科技有限公司 | Display mainboard, display and projection equipment of compatible interface of lying |
| CN114120882A (en) * | 2021-12-14 | 2022-03-01 | 惠州视维新技术有限公司 | Display device and method compatible with multiple display panels |
| CN114267310A (en) * | 2021-12-28 | 2022-04-01 | 冠捷显示科技（厦门）有限公司 | Driving device of Tconless display screen |
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|---|---|
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