CN203224819U - Mainboard - Google Patents
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- CN203224819U CN203224819U CN 201320170096 CN201320170096U CN203224819U CN 203224819 U CN203224819 U CN 203224819U CN 201320170096 CN201320170096 CN 201320170096 CN 201320170096 U CN201320170096 U CN 201320170096U CN 203224819 U CN203224819 U CN 203224819U
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Abstract
The utility model discloses a mainboard, comprising an SATA controller, a PCIE controller, a MINI PCIE interface, a detecting circuit and a switching circuit, wherein the MINI PCIE interface is used for MSATA equipment or MINI PCIE equipment to plug, the detecting circuit is used for detecting whether the MSATA equipment or the MINI PCIE equipment is plugged into the MINI PCIE interface, and the switching circuit is used for conducting the MSATA equipment plugged into the MINI PCIE interface with the SATA controller for being in data communication with the SATA controller or conducting the MINI PCIE equipment plugged into the MINI PCIE interface with the PCIE controller for being in data communication with the PCIE controller according to the detection results of the detection circuit, the detection circuit is connected with a preserved pin of the MINI PCIE interface, the switching circuit is connected with the detection circuit, and the SATA controller and the PCIE controller are both connected with the switching circuit. The mainboard has the beneficial effects that the MINI PCIE interface of the mainboard is enabled to be compatible with the MSATA equipment and the MINI PCIE equipment, so that use by a user is facilitated, and since one interface is compatible with different solid state discs, the cost is reduced.
Description
Technical field
The utility model relates to computer realm, more particularly, relates to a kind of mainboard.
Background technology
The MSATA interface is the international interface standard tissue of SATA-IO(SATA) a kind of novel interface standard of issue, be with solid state hard disc fields such as box (STB), printer on flat computer, mobile phone, Netbook, POS, machine of MSATA interface to have a wide range of applications.
MINI PCIE interface is based on the interface of PCIE bus, by this interface wireless LAN card, 3G network interface card, TV card, solid state hard disc etc. can be installed.
The MSATA interface is identical with the outward appearance of MINI PCIE interface, and physical pin is compatible, but generally directly intercommunication use.Because though the interface of MSATA is just the same with MINI PCIE interface in appearance, data-signal need be connected to the SATA controller, but not on the PCIE controller.Therefore, the MINI PCIE interface of most of panel computers, notebook computer, all-in-one, embedded main board all can not be realized compatible MSATA equipment and MINI PCIE equipment simultaneously, and the interface that need establish a MSATA on mainboard in addition is to support MSATA equipment, the complexity that this has just increased mainboard is unfavorable for reducing volume and reduces cost.
The utility model content
The technical problems to be solved in the utility model is, at the above-mentioned MINI PCIE interface of the prior art defective of compatible MSATA equipment and MINI PCIE equipment simultaneously, provides a kind of mainboard.
The technical scheme that its technical matters that solves the utility model adopts is:
A kind of mainboard, comprise for MSATA equipment carry out data communication the SATA controller, be used for the PCIE controller that carries out data communication with MINI PCIE equipment, described mainboard also comprises:
MINI PCIE interface is used for grafting MSATA equipment or MINI PCIE equipment;
Testing circuit is MSATA equipment or MINIPCIE equipment for detection of what be inserted into MINI PCIE interface;
Commutation circuit, be used for the testing result according to testing circuit, to be inserted into the MSATA equipment of MINI PCIE interface and the conducting of SATA controller to carry out data communication, maybe will be inserted into the MINI PCIE equipment of MINI PCIE interface and the conducting of PCIE controller to carry out data communication; Wherein,
Described testing circuit is reserved pin with one of MINI PCIE interface and is connected, and described commutation circuit is connected with described testing circuit, and described SATA controller all is connected with described commutation circuit with the PCIE controller.
Preferably, described mainboard also comprises for giving the motherboard circuit direct current power source supplying power.
Preferably, described testing circuit comprises pull-up resistor, and wherein, an end of described pull-up resistor is connected with a reservation pin of described MINI PCIE interface, the other end is connected described direct supply.
Preferably, described commutation circuit comprises a multiplexer, and wherein, the single-ended input pin of the low pressure of described multiplexer connects the reservation pin of described pull-up resistor and described MINI PCIE interface respectively;
First difference of described multiplexer leads directly to the straight-through input pin of input pin, second difference, the straight-through input pin of the 3rd difference, the straight-through input pin of the 4th difference and all connects described PCIE controller;
The 5th difference of described multiplexer leads directly to the straight-through input pin of input pin, the 6th difference, the straight-through input pin of the 7th difference, the straight-through input pin of the 8th difference and all connects described SATA controller.
Preferably, first difference of described MINI PCIE interface transmission pin, second difference transmission pin, the first differential received pin, the second differential received pin connect the first difference input pin, the second difference input pin, the 3rd difference input pin, the 4th difference input pin of described multiplexer respectively.
Preferably, the model of multiplexer is PI3PCIE2215, and the single-ended input pin of the low pressure of described multiplexer is its 16th pin;
The first difference input pin of described multiplexer, the second difference input pin, the 3rd difference input pin, the 4th difference input pin are respectively its 2nd pin, the 1st pin, the 6th pin, the 5th pin;
First difference of described multiplexer leads directly to the straight-through input pin of input pin, second difference, the straight-through input pin of the 3rd difference, the straight-through input pin of the 4th difference and is respectively its 3rd pin, the 4th pin, the 7th pin, the 8th pin;
The 5th difference of described multiplexer leads directly to the straight-through input pin of input pin, the 6th difference, the straight-through input pin of the 7th difference, the straight-through input pin of the 8th difference and is respectively its 23rd pin, the 22nd pin, the 19th pin, the 18th pin.
Preferably, first difference of described MINI PCIE interface transmission pin, second difference transmission pin, the first differential received pin, the second differential received pin are respectively its 31st pin, the 33rd pin, the 23rd pin, the 25th pin.
Preferably, the reservation pin of described MINI PCIE interface is its 51st pin.
Implement a kind of mainboard of the present utility model, have following beneficial effect: make that the MINI PCIE interface of mainboard can compatible MSATA equipment and MINI PCIE equipment, user-friendly, and a kind of interface can compatible different solid state hard discs, can save cost.
Description of drawings
The utility model is described in further detail below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the mainboard structure synoptic diagram of the utility model embodiment;
Fig. 2 is the part-structure of MINI PCIE interface of mainboard shown in Figure 1 and the circuit diagram of testing circuit;
Fig. 3 is the circuit diagram of the multiplexer of mainboard shown in Figure 1.
Embodiment
Understand for technical characterictic of the present utility model, purpose and effect being had more clearly, now contrast accompanying drawing and describe embodiment of the present utility model in detail.
Be illustrated in figure 1 as the mainboard structure synoptic diagram of the utility model embodiment.In the utility model, mainboard 10 comprises: SATA controller 105, PCIE controller 104, MINI PCIE interface 102, testing circuit 106, commutation circuit 107, testing circuit 106 is reserved pin with one of MINI PCIE interface 102 and is connected, commutation circuit 107 is connected with testing circuit 106, and SATA controller 105 all is connected with commutation circuit 107 with PCIE controller 104.
Wherein, SATA controller 105 is used for carrying out data communication with MSATA equipment;
PCIE controller 104 is used for carrying out data communication with MINI PCIE equipment;
MINI PCIE interface 102 is used for grafting MSATA equipment 101 or MINI PCIE equipment 100;
Testing circuit 106 is MSATA equipment or MINI PCIE equipment for detection of what be inserted into MINI PCIE interface;
Commutation circuit 107 is used for the testing result according to testing circuit 106, maybe will be inserted into the MINI PCIE equipment of MINI PCIE interface 102 and 104 conductings of PCIE controller to carry out data communication with being inserted into the MSATA equipment of MINI PCIE interface 102 and 105 conductings of SATA controller to carry out data communication.
In embodiment of the present utility model, as detecting pin, testing circuit 106 in the groove is MSATA equipment 101 according to current being inserted into of the signal identification of the 51st pin, or MINI PCIE equipment 100 with the 51st pin of MINI PCIE interface 102.Commutation circuit 107 selects to be communicated with SATA controller 105 or PCIE controller 104 then, thereby realizes that MINI PCIE interface 102 can compatible MSATA equipment 101 and MINI PCIE equipment 100.
As shown in Figure 2, be the part-structure of the MINI PCIE interface of mainboard shown in Figure 1 and the circuit diagram of testing circuit.Be illustrated in figure 3 as the circuit diagram of the multiplexer of mainboard shown in Figure 1.Mainboard 10 of the present utility model comprises that also this direct supply comprises a 3.3V power supply at least for giving the motherboard circuit direct current power source supplying power.
In embodiment of the present utility model, it is according to prior art, and MINI PCIE interface 102 comprises 52 standard pin.Each pin has corresponding function, and concrete pin function is prior art, need not to give unnecessary details at this.Wherein, the 31st pin of MINI PCIE interface 102, the 33rd pin are that difference sends pin, and the 23rd pin, the 25th pin are the differential received pin, and the 51st pin is a reservation pin.Wherein, the 31st pin is that first difference sends pin, and the 33rd pin is that second difference sends pin, and the 23rd pin is the first differential received pin, and the 25th pin is the second differential received pin.
Referring to Fig. 2, testing circuit 106 comprises pull-up resistor R1.Referring to Fig. 3, commutation circuit 107 comprises a multiplexer 103, and the model of multiplexer 103 is PI3PCIE2215, and it comprises 28 pins according to prior art.Each pin has corresponding function, and concrete pin function is prior art, need not to give unnecessary details at this.Wherein, the 2nd of multiplexer 103,1,6,5 pins are respectively the first difference input pin, the second difference input pin, the 3rd difference input pin, the 4th difference input pin, the 3rd, 4,7,8,23,22,19,18 pins are respectively the straight-through input pin of first difference, second difference leads directly to input pin, the 3rd difference leads directly to input pin, the 4th difference leads directly to input pin, the 5th difference leads directly to input pin, the 6th difference leads directly to input pin, the 7th difference leads directly to input pin, the 8th difference leads directly to input pin, and the 16th pin is the single-ended input pin of low pressure.
Referring to Fig. 2 and Fig. 3, the 51st pin of MINI PCIE interface 102 connects the 16th pin of multiplexer 103 by resistance R 2.And the 51st pin of the termination MINI PCIE interface 102 of pull-up resistor R1, the other end connect the 16th pin of multiplexer 103 respectively and connect the 3.3V power supply by pull-up resistor R1.The 31st pin of MINI PCIE interface 102, the 33rd pin, the 23rd pin, the 25th pin connect the 2nd pin, the 1st pin, the 6th pin, the 5th pin of multiplexer 103 respectively.The 3rd pin of multiplexer 103, the 4th pin, the 7th pin, the 8th pin all connect PCIE controller 104.The 23rd pin of multiplexer 103, the 22nd pin, the 19th pin, the 18th pin all connect SATA controller 105.Other pins of MINI PCIE interface 102 connect to realize corresponding function according to the connected mode of prior art.
The equal ground connection of the 11st, 13,15,21,24,26,28 pins of multiplexer 103; The 9th, 12,14,17,20,25,27 pins of multiplexer 103 all connect the 3.3V power supply.3.3V be connected to capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4 between power supply and the ground respectively, to realize the effect of filtering.
In the utility model, select for use the 51st pin of MINI PCIE interface 102 as detecting pin, be because the 51st pin of MINI PCIE equipment 100 is defined as not connecting, and the 51st pinout of MSATA equipment 101 is GND ground wires.Therefore, after different equipment was inserted into MINI PCIE interface 102, according to the signal of the 51st pin, it was any equipment that multiplexer 103 just can be judged, then with the data signal channel conducting of distinct device.
In the course of the work, because the 51st pin of MINI PCIE equipment 100 is defined as not connecting, therefore, when MINI PCIE equipment 100 inserts MINI PCIE interface, make the 16th pin of multiplexer 103 receive high level by pull-up resistor R1.Then the 1st pin of multiplexer 103, the 2nd pin are communicated with the 3rd pin, the 4th pin respectively, the 5th pin, the 6th pin are communicated with the 7th pin, the 8th pin respectively, thereby realize data-signal and 104 conductings of PCIE controller with MINI PCIE interface 102.
And the 51st pinout of MSATA equipment 101 is GND ground wires, and therefore, when MSATA equipment 101 insertion MINI PCIE interfaces 102, then the 16th pin of multiplexer 103 receives low level.Then the 1st pin of multiplexer 103, the 2nd pin are communicated with the 23rd pin, the 22nd pin respectively, the 5th pin, the 6th pin are communicated with the 19th pin, the 18th pin respectively, thereby realize data-signal and 105 conductings of SATA controller with MINIPCIE interface 102.
In the utility model, by one of the MINI PCIE interface on the mainboard is reserved pin as detecting pin, make that the MINI PCIE interface of mainboard can compatible MSATA equipment and MINI PCIE equipment, user-friendly, and a kind of interface can compatible different solid state hard disc, is conducive to simplify hardware configuration and saves cost.
Should be understood that in the utility model the 51st pin of selecting MINI PCIE interface as detecting pin only for exemplary, in addition, can also select other reservation pin of MINI PCIE interface to realize identical functions.
By reference to the accompanying drawings embodiment of the present utility model is described above; but the utility model is not limited to above-mentioned embodiment; above-mentioned embodiment only is schematic; rather than it is restrictive; those of ordinary skill in the art is under enlightenment of the present utility model; not breaking away under the scope situation that the utility model aim and claim protect, also can make a lot of forms, these all belong within the protection of the present utility model.
Claims (8)
1. mainboard, comprise for MSATA equipment carry out data communication SATA controller (105), be used for the PCIE controller (104) that carries out data communication with MINI PCIE equipment, it is characterized in that described mainboard also comprises:
MINI PCIE interface (102) is used for grafting MSATA equipment or MINI PCIE equipment;
Testing circuit (106) is MSATA equipment or MINI PCIE equipment for detection of what be inserted into MINI PCIE interface;
Commutation circuit (107), be used for the testing result according to testing circuit (106), the MSATA equipment of MINIPCIE interface (102) and SATA controller (105) conducting be will be inserted into to carry out data communication, the MINI PCIE equipment of MINI PCIE interface (102) and PCIE controller (104) conducting maybe will be inserted into to carry out data communication;
Wherein, described testing circuit (106) is reserved pin with one of MINI PCIE interface (102) and is connected, described commutation circuit (107) is connected with described testing circuit (106), and described SATA controller (105) all is connected with described commutation circuit (107) with PCIE controller (104).
2. mainboard according to claim 1 is characterized in that, described mainboard also comprises for giving the motherboard circuit direct current power source supplying power.
3. mainboard according to claim 2, it is characterized in that, described testing circuit (106) comprises pull-up resistor (R1), and wherein, an end of described pull-up resistor (R1) is connected with a reservation pin of described MINI PCIE interface (102), the other end is connected described direct supply.
4. mainboard according to claim 3, it is characterized in that, described commutation circuit (107) comprises a multiplexer (103), wherein, the single-ended input pin of low pressure of described multiplexer (103) connects the reservation pin of described pull-up resistor (R1) and described MINI PCIE interface (102) respectively;
First difference of described multiplexer (103) leads directly to the straight-through input pin of input pin, second difference, the straight-through input pin of the 3rd difference, the straight-through input pin of the 4th difference and all connects described PCIE controller (104);
The 5th difference of described multiplexer (103) leads directly to the straight-through input pin of input pin, the 6th difference, the straight-through input pin of the 7th difference, the straight-through input pin of the 8th difference and all connects described SATA controller (105).
5. mainboard according to claim 4, it is characterized in that first difference transmission pin of described MINI PCIE interface (102), second difference transmission pin, the first differential received pin, the second differential received pin connect the first difference input pin, the second difference input pin, the 3rd difference input pin, the 4th difference input pin of described multiplexer (103) respectively.
6. mainboard according to claim 5 is characterized in that, the model of multiplexer (103) is PI3PCIE2215, and the single-ended input pin of low pressure of described multiplexer (103) is its 16th pin;
The first difference input pin of described multiplexer (103), the second difference input pin, the 3rd difference input pin, the 4th difference input pin are respectively its 2nd pin, the 1st pin, the 6th pin, the 5th pin;
First difference of described multiplexer (103) leads directly to the straight-through input pin of input pin, second difference, the straight-through input pin of the 3rd difference, the straight-through input pin of the 4th difference and is respectively its 3rd pin, the 4th pin, the 7th pin, the 8th pin;
The 5th difference of described multiplexer (103) leads directly to the straight-through input pin of input pin, the 6th difference, the straight-through input pin of the 7th difference, the straight-through input pin of the 8th difference and is respectively its 23rd pin, the 22nd pin, the 19th pin, the 18th pin.
7. mainboard according to claim 5, it is characterized in that first difference transmission pin of described MINI PCIE interface (102), second difference transmission pin, the first differential received pin, the second differential received pin are respectively its 31st pin, the 33rd pin, the 23rd pin, the 25th pin.
8. mainboard according to claim 1 is characterized in that, the reservation pin of described MINI PCIE interface (102) is its 51st pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320170096 CN203224819U (en) | 2013-04-08 | 2013-04-08 | Mainboard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320170096 CN203224819U (en) | 2013-04-08 | 2013-04-08 | Mainboard |
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| CN203224819U true CN203224819U (en) | 2013-10-02 |
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| CN 201320170096 Expired - Fee Related CN203224819U (en) | 2013-04-08 | 2013-04-08 | Mainboard |
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409937A (en) * | 2014-11-25 | 2015-03-11 | 合肥宝龙达信息技术有限公司 | USB3.0 (universal serial bus 3.0) and eSATA (external serial advanced technology attachment) combined interface |
| CN105893298A (en) * | 2016-06-29 | 2016-08-24 | 联想(北京)有限公司 | Interface connecting method and electronic equipment |
| CN107092570A (en) * | 2017-05-27 | 2017-08-25 | 郑州云海信息技术有限公司 | The adaptive configuring method and system of a kind of onboard M.2 hard disk of server |
| CN107291649A (en) * | 2017-06-20 | 2017-10-24 | 郑州云海信息技术有限公司 | The design method and device of a kind of flexible support PCIE and SATA agreements M.2 self-identifying |
| CN107704272A (en) * | 2017-10-24 | 2018-02-16 | 郑州云海信息技术有限公司 | A kind of mainboard and its BIOS configuration determination method, system, device and storage medium |
| CN107765995A (en) * | 2017-09-22 | 2018-03-06 | 郑州云海信息技术有限公司 | A kind of hard-disk interface multichannel compatible system and implementation method |
| CN107832094A (en) * | 2017-10-24 | 2018-03-23 | 郑州云海信息技术有限公司 | A kind of mainboard and its BIOS configuration determination method, system and relevant apparatus |
| CN109815182A (en) * | 2019-01-28 | 2019-05-28 | 合肥联宝信息技术有限公司 | A kind of hardware device recognition methods and device |
| CN109857695A (en) * | 2018-12-27 | 2019-06-07 | 曙光信息产业(北京)有限公司 | The interface switch system of server master board |
| CN110554990A (en) * | 2018-06-01 | 2019-12-10 | 鸿富锦精密工业(武汉)有限公司 | Mainboard circuit compatible with PCIE and SATA circuits |
| CN111104360A (en) * | 2019-11-30 | 2020-05-05 | 北京浪潮数据技术有限公司 | NVMe protocol-based solid state disk |
| US11150842B1 (en) | 2020-04-20 | 2021-10-19 | Western Digital Technologies, Inc. | Dynamic memory controller and method for use therewith |
| WO2021262255A1 (en) * | 2020-06-24 | 2021-12-30 | Western Digital Technologies, Inc. | Dual-interface storage system and method for use therewith |
| US11442665B2 (en) | 2020-12-04 | 2022-09-13 | Western Digital Technologies, Inc. | Storage system and method for dynamic selection of a host interface |
| WO2023273140A1 (en) * | 2021-06-28 | 2023-01-05 | 深圳市商汤科技有限公司 | Signal transmission apparatus and method, and computer device and storage medium |
-
2013
- 2013-04-08 CN CN 201320170096 patent/CN203224819U/en not_active Expired - Fee Related
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409937A (en) * | 2014-11-25 | 2015-03-11 | 合肥宝龙达信息技术有限公司 | USB3.0 (universal serial bus 3.0) and eSATA (external serial advanced technology attachment) combined interface |
| CN105893298A (en) * | 2016-06-29 | 2016-08-24 | 联想(北京)有限公司 | Interface connecting method and electronic equipment |
| CN107092570A (en) * | 2017-05-27 | 2017-08-25 | 郑州云海信息技术有限公司 | The adaptive configuring method and system of a kind of onboard M.2 hard disk of server |
| CN107291649A (en) * | 2017-06-20 | 2017-10-24 | 郑州云海信息技术有限公司 | The design method and device of a kind of flexible support PCIE and SATA agreements M.2 self-identifying |
| WO2018233222A1 (en) * | 2017-06-20 | 2018-12-27 | 郑州云海信息技术有限公司 | Design method and apparatus for self-recognition of m.2 capable of flexibly supporting pcie and sata protocols |
| CN107765995A (en) * | 2017-09-22 | 2018-03-06 | 郑州云海信息技术有限公司 | A kind of hard-disk interface multichannel compatible system and implementation method |
| CN107704272A (en) * | 2017-10-24 | 2018-02-16 | 郑州云海信息技术有限公司 | A kind of mainboard and its BIOS configuration determination method, system, device and storage medium |
| CN107832094A (en) * | 2017-10-24 | 2018-03-23 | 郑州云海信息技术有限公司 | A kind of mainboard and its BIOS configuration determination method, system and relevant apparatus |
| CN110554990A (en) * | 2018-06-01 | 2019-12-10 | 鸿富锦精密工业(武汉)有限公司 | Mainboard circuit compatible with PCIE and SATA circuits |
| CN109857695A (en) * | 2018-12-27 | 2019-06-07 | 曙光信息产业(北京)有限公司 | The interface switch system of server master board |
| CN109815182A (en) * | 2019-01-28 | 2019-05-28 | 合肥联宝信息技术有限公司 | A kind of hardware device recognition methods and device |
| CN111104360A (en) * | 2019-11-30 | 2020-05-05 | 北京浪潮数据技术有限公司 | NVMe protocol-based solid state disk |
| CN111104360B (en) * | 2019-11-30 | 2021-08-10 | 北京浪潮数据技术有限公司 | NVMe protocol-based solid state disk |
| US11150842B1 (en) | 2020-04-20 | 2021-10-19 | Western Digital Technologies, Inc. | Dynamic memory controller and method for use therewith |
| WO2021262255A1 (en) * | 2020-06-24 | 2021-12-30 | Western Digital Technologies, Inc. | Dual-interface storage system and method for use therewith |
| US11281399B2 (en) | 2020-06-24 | 2022-03-22 | Western Digital Technologies, Inc. | Dual-interface storage system and method for use therewith |
| US11442665B2 (en) | 2020-12-04 | 2022-09-13 | Western Digital Technologies, Inc. | Storage system and method for dynamic selection of a host interface |
| WO2023273140A1 (en) * | 2021-06-28 | 2023-01-05 | 深圳市商汤科技有限公司 | Signal transmission apparatus and method, and computer device and storage medium |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131002 Termination date: 20200408 |
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| CF01 | Termination of patent right due to non-payment of annual fee |