CN203537553U - An Interface circuit realizing serial port and infrared multiplex functions - Google Patents
An Interface circuit realizing serial port and infrared multiplex functions Download PDFInfo
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- CN203537553U CN203537553U CN201320646815.8U CN201320646815U CN203537553U CN 203537553 U CN203537553 U CN 203537553U CN 201320646815 U CN201320646815 U CN 201320646815U CN 203537553 U CN203537553 U CN 203537553U
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- interface
- circuit
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- channel mos
- multiplex
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Abstract
Embodiments of the present utility model disclose an interface circuit realizing serial port and infrared multiplex functions. The interface circuit comprises a processing chip, a multiplex interface, an infrared receiving circuit, a serial port circuit and an interface detection circuit. The infrared receiving circuit is connected with the processing chip and the multiplex interface respectively. The serial port circuit is connected with the processing chip and the multiplex interface respectively. The interface detection circuit is connected with the multiplex circuit, the infrared receiving circuit and the serial port circuit respectively. The interface detection circuit detects whether an infrared device or a serial port device is connected into the multiplex interface, and if an infrared device is connected to the multiplex interface, the interface detection circuit controls the infrared receiving circuit to transmit infrared signals to the processing chip; and if a serial port device is connected to the multiplex interface, the interface detection circuit controls the serial port circuit to transmit serial port signals between the multiplex circuit and the processing chip. By means of the interface circuit, the conduction of an MOS transistor is controlled through the control level output by the interface detection circuit, and thus functions of the multiplex interface are controlled; and the interface circuit has the advantages of few circuit devices and low cost.
Description
Technical field
The utility model relates to electronic technology field, relates in particular to the interface circuit of a kind of serial ports and infrared multiplexing functions.
Background technology
Current era, the function that electronic product is realized is more and more, but electronic product is tending towards Miniaturization Design, therefore in the urgent need to realizing the interface circuit of several functions.At present, serial ports and infrared communication are widely used in various electronic products, such as Set Top Box, smart mobile phone, panel computer etc., therefore, the necessary interface circuit of realizing serial ports and infrared multiplexing functions.Prior art is mainly by operational amplifier, to detect external equipment to obtain corresponding level, thereby control electronic switch chip according to this level, with different paths, realize the selection of interface function, the components and parts that this circuit need to be arranged on mainboard are many, and cost is high.
Utility model content
The utility model provides the interface circuit of a kind of serial ports and infrared multiplexing functions, the control level of exporting by interface testing circuit is controlled the conducting of metal-oxide-semiconductor, thereby the use function of controlling multiplex interface, circuit structure is simple, and has advantages of that device is few, cost is low.
The utility model embodiment provides the interface circuit of a kind of serial ports and infrared multiplexing functions, comprises process chip, multiplex interface, infrared receiving circuit, serial port circuit and interface testing circuit, wherein:
Described multiplex interface is for transmitting infrared signal or rs 232 serial interface signal with external equipment;
Described interface testing circuit is connected with described multiplex interface, for detection of what access on described multiplex interface, is infrared equipment or serial equipment;
Described infrared receiving circuit is connected with described interface testing circuit, described process chip and described multiplex interface respectively, the infrared signal transmission that is used for described multiplex interface to receive is to described process chip, wherein, described infrared receiving circuit comprises N-channel MOS pipe, N-channel MOS pipe conducting described in described interface testing circuit and described infrared equipment co-controlling;
Described serial port circuit is connected with described interface testing circuit, described process chip and described multiplex interface respectively, for transmitting serial port signal between described multiplex interface and described process chip, wherein, described serial port circuit comprises P channel MOS tube, and described interface testing circuit is controlled the conducting of described P channel MOS tube.
Implement the utility model embodiment, the control level that can export by interface testing circuit is controlled the conducting of metal-oxide-semiconductor, thereby controls the use function of multiplex interface, and circuit structure is simple, and has advantages of that device is few, cost is low.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the utility model embodiment, to the accompanying drawing of required use in embodiment be briefly described below, apparently, accompanying drawing in the following describes is embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structured flowchart of the interface circuit of a kind of serial ports of the present utility model and infrared multiplexing functions;
Fig. 2 is the schematic diagram of the interface circuit of a kind of serial ports of the present utility model and infrared multiplexing functions.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is the utility model part embodiment, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
Refer to Fig. 1, in the utility model embodiment, the interface circuit of serial ports and infrared multiplexing functions can be applied on equipment such as Set Top Box, smart mobile phone, panel computer.As shown in Figure 1, the interface circuit of serial ports and infrared multiplexing functions comprises: process chip, multiplex interface 11, testing circuit 12, infrared receiving circuit 13 and interface serial port circuit 14.
Described multiplex interface 11 is for transmitting infrared signal or rs 232 serial interface signal with external equipment.
In specific implementation, refer to the multiplex interface shown in Fig. 2, there are four pins in described multiplex interface, wherein, pin 1 ground connection of multiplex interface, pin 2 access power supplys, pin 3 and pin 4 are for signal transmission, this multiplex interface can transmit infrared signal with infrared equipment, this multiplex interface can also with serial equipment transmitting serial port signal.
Described interface testing circuit 12 is connected with described multiplex interface 11, and for detection of access on described multiplex interface 11 is infrared equipment or serial equipment.
In specific implementation, described interface testing circuit 12 comprises triode, the first divider resistance, storage capacitor, the second divider resistance, the 3rd divider resistance, the 4th divider resistance, wherein, one end of the first divider resistance is connected with the collector electrode of triode, the other end access power supply of the first divider resistance, the collector electrode of triode is connected with described serial port circuit 14 and infrared receiving circuit 13, the base stage of triode, one end of the second divider resistance and one end of storage capacitor are connected with one end of the 3rd divider resistance, the emitter of triode, the other end ground connection of the other end of the second divider resistance and storage capacitor, the pin 4 of one end access multiplexing interface 11 of the other end of the 3rd divider resistance and the 4th divider resistance, other end access power supply and the process chip of the 4th divider resistance.
Described interface testing circuit 12 can be by the external equipment of the judgement of pressure drop over the ground multiplex interface 11 accesses between the 3rd divider resistance and the 4th divider resistance, pressure drop over the ground between the 3rd divider resistance and the 4th divider resistance is U for a long time, be that multiplex interface 11 does not access external equipment, when between the 3rd divider resistance and the 4th divider resistance pressure drop is less than U over the ground time, interface testing circuit 12 can judge multiplex interface 11 access infrared equipments; When between the 3rd divider resistance and the 4th divider resistance pressure drop is greater than U over the ground time, interface testing circuit 12 can judge multiplex interface 11 access serial equipments.
Further alternative, described interface testing circuit 12 also comprises the first current-limiting resistance and the 6th divider resistance, wherein, one end of the first current-limiting resistance is connected with the collector electrode of triode, the other end of the first current-limiting resistance is connected with described serial port circuit 14 and infrared receiving circuit 13, one end of the 6th divider resistance is connected with described process chip, the other end access power supply of the 6th divider resistance.
The circuit diagram of described interface testing circuit 12 refers to Fig. 2, and wherein, Q9 is triode, and C9 is storage capacitor, R97 is the first divider resistance, and R99 is the second divider resistance, and R100 is the 3rd divider resistance, R101 is the 4th divider resistance, and R22 is the first current-limiting resistance, and R44 is the 6th divider resistance.
Described infrared receiving circuit 13 is connected with described interface testing circuit 12, described process chip and described multiplex interface 11 respectively, the infrared signal transmission that is used for described multiplex interface 11 to receive is to described process chip, wherein, described infrared receiving circuit 13 comprises N-channel MOS pipe, N-channel MOS pipe conducting described in described interface testing circuit 13 and described infrared equipment co-controlling.
In specific implementation, described infrared receiving circuit 13 also comprises the first biasing resistor and the 3rd current-limiting resistance, wherein, the grid of N-channel MOS pipe is connected with one end of the first biasing resistor, the other end of the source electrode of N-channel MOS pipe and the first biasing resistor is connected with the pin 3 of multiplex interface 11, the drain electrode of N-channel MOS pipe is connected with the pin 2 of described process chip, multiplex interface 11 and one end of the 3rd current-limiting resistance, the other end access power supply of the 3rd current-limiting resistance.
In described interface testing circuit 12, the collector electrode of triode is connected with the grid of N-channel MOS pipe in infrared receiving circuit 13, while accessing infrared equipment on interface testing circuit 12 detection multiplex interfaces 11, by increasing, the collector voltage of triode is controlled P channel MOS tube and N-channel MOS pipe ends, when infrared receiving circuit 13 produces data transmission, by controlling conducting or the cut-off of N-channel MOS pipe, to described process chip, transmit infrared signal.
Further alternative, described infrared receiving circuit 13 also comprises the 4th current-limiting resistance, the second current-limiting resistance and decoupling capacitor, wherein, one end of one end of the 4th current-limiting resistance and the second current-limiting resistance is connected with the drain electrode of N-channel MOS pipe, the other end of the 4th current-limiting resistance is connected with process chip, the other end of the second current-limiting resistance and one end of decoupling capacitor are connected with the pin 2 of multiplex interface 11, the other end ground connection of decoupling capacitor.
The circuit diagram of described infrared receiving circuit 13 refers to Fig. 2, and wherein, Q10 is N-channel MOS pipe, and R4 is the first biasing resistor, and R200 is the 3rd current-limiting resistance, and R203 is the 4th current-limiting resistance, and R204 is the second current-limiting resistance, and C135 is decoupling capacitor.
Described serial port circuit 14 is connected with described interface testing circuit 12, described process chip and described multiplex interface 11 respectively, for transmitting serial port signal between described multiplex interface 11 and described process chip, wherein, described serial port circuit 14 comprises P channel MOS tube, and described interface testing circuit 12 is controlled the conducting of described P channel MOS tube.
In specific implementation, described serial port circuit 14 also comprises the second biasing resistor, wherein, the grid of P channel MOS tube is connected with one end of the second biasing resistor, other end access power supply and the process chip of the source electrode of P channel MOS tube and the second biasing resistor, the drain electrode of P channel MOS tube is connected with the pin 3 of multiplex interface 11.
In described interface testing circuit 12, three extreme collector electrodes are connected with the grid of P channel MOS tube in serial port circuit 14, while accessing serial equipment on interface testing circuit 12 detection multiplex interfaces 11, by reducing the collector voltage of triode, control the conducting of P channel MOS tube, make serial port circuit 14 transmitting serial port signal between described multiplex interface 11 and described process chip.
Further alternative, described serial port circuit 14 also comprises the 5th divider resistance, and one end of described the 5th divider resistance is connected with the source electrode of P channel MOS tube, the other end access power supply of the 5th divider resistance.
The circuit diagram of described serial port circuit 14 refers to Fig. 2, and wherein, Q7 is P channel MOS tube, and R15 is the second biasing resistor, and R47 is the 5th divider resistance.
The infrared receiving terminal of described process chip is connected with described infrared receiving module, and the serial ports output of described process chip is connected with described interface testing circuit, and the serial ports receiving terminal of described process chip is connected with described serial port circuit.
Implement the utility model embodiment, can export corresponding control level by the external equipment of interface testing circuit detection multiplex interface access, by this control level, control the conducting of metal-oxide-semiconductor, thereby control the use function of multiplex interface, the interface circuit of this serial ports and infrared multiplexing functions simple in structure, and have advantages of that device is few, cost is low.
Above disclosed is only the utility model preferred embodiment, certainly can not limit with this interest field of the utility model, and the equivalent variations of therefore doing according to the utility model claim, still belongs to the scope that the utility model is contained.
Claims (6)
1. an interface circuit of realizing serial ports and infrared multiplexing functions, is characterized in that, comprises process chip, multiplex interface, infrared receiving circuit, serial port circuit and interface testing circuit, wherein:
Described multiplex interface is for transmitting infrared signal or rs 232 serial interface signal with external equipment;
Described interface testing circuit is connected with described multiplex interface, for detection of what access on described multiplex interface, is infrared equipment or serial equipment;
Described infrared receiving circuit is connected with described interface testing circuit, described process chip and described multiplex interface respectively, the infrared signal transmission that is used for described multiplex interface to receive is to described process chip, wherein, described infrared receiving circuit comprises N-channel MOS pipe, and described interface testing circuit is controlled the conducting of described N-channel MOS pipe;
Described serial port circuit is connected with described interface testing circuit, described process chip and described multiplex interface respectively, for transmitting serial port signal between described multiplex interface and described process chip, wherein, described serial port circuit comprises P channel MOS tube, and described interface testing circuit is controlled the conducting of described P channel MOS tube.
2. the interface circuit of realizing serial ports and infrared multiplexing functions as claimed in claim 1, it is characterized in that, described interface testing circuit comprises triode, the first divider resistance, storage capacitor, the second divider resistance, the 3rd divider resistance, the 4th divider resistance, wherein, one end of the first divider resistance is connected with the collector electrode of triode, the other end access power supply of the first divider resistance, the base stage of triode, one end of the second divider resistance and one end of storage capacitor are connected with one end of the 3rd divider resistance, the emitter of triode, the other end ground connection of the other end of the second divider resistance and storage capacitor, the pin 4 of one end access multiplexing interface of the other end of the 3rd divider resistance and the 4th divider resistance, other end access power supply and the process chip of the 4th divider resistance,
Described infrared receiving circuit also comprises the first biasing resistor and the 3rd current-limiting resistance, wherein, the grid of N-channel MOS pipe is connected with one end of the first biasing resistor, the other end of the source electrode of N-channel MOS pipe and the first biasing resistor is connected with the pin of multiplex interface 3, the drain electrode of N-channel MOS pipe is connected with the pin 2 of described process chip, multiplex interface and one end of the 3rd current-limiting resistance, the other end access power supply of the 3rd current-limiting resistance;
In described interface testing circuit, the collector electrode of triode is connected with the grid of N-channel MOS pipe in infrared receiving circuit, while accessing infrared equipment on interface testing circuit detection multiplex interface, by increasing, the collector voltage of triode is controlled P channel MOS tube and N-channel MOS pipe ends, when infrared receiving circuit produces data transmission, by controlling conducting or the cut-off of N-channel MOS pipe, to described process chip, transmit infrared signal.
3. the interface circuit of realizing serial ports and infrared multiplexing functions as claimed in claim 2, it is characterized in that, described serial port circuit also comprises the second biasing resistor, wherein, the grid of P channel MOS tube is connected with one end of the second biasing resistor, other end access power supply and the process chip of the source electrode of P channel MOS tube and the second biasing resistor, the drain electrode of P channel MOS tube is connected with the pin of multiplex interface 3;
In described interface testing circuit, three extreme collector electrodes are connected with the grid of P channel MOS tube in serial port circuit, while accessing serial equipment on interface testing circuit detection multiplex interface, by reducing the collector voltage of triode, control the conducting of P channel MOS tube, make serial port circuit transmitting serial port signal between described multiplex interface and described process chip.
4. the interface circuit of realizing serial ports and infrared multiplexing functions as claimed in claim 3, it is characterized in that, described infrared receiving circuit also comprises the 4th current-limiting resistance, the second current-limiting resistance and decoupling capacitor, wherein, one end of one end of the 4th current-limiting resistance and the second current-limiting resistance is connected with the drain electrode of N-channel MOS pipe, the other end of the 4th current-limiting resistance is connected with process chip, the other end of the second current-limiting resistance and one end of decoupling capacitor are connected with the pin 2 of multiplex interface, the other end ground connection of decoupling capacitor.
5. the interface circuit of realizing serial ports and infrared multiplexing functions as claimed in claim 3, it is characterized in that, described serial port circuit also comprises the 5th divider resistance, and one end of described the 5th divider resistance is connected with the source electrode of P channel MOS tube, the other end access power supply of the 5th divider resistance.
6. the interface circuit of realizing serial ports and infrared multiplexing functions as claimed in claim 3, it is characterized in that, described interface testing circuit also comprises the first current-limiting resistance and the 6th divider resistance, wherein, one end of the first current-limiting resistance is connected with the collector electrode of triode, the other end of the first current-limiting resistance is connected with described serial port circuit and infrared receiving circuit, and one end of the 6th divider resistance is connected with described process chip, the other end access power supply of the 6th divider resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320646815.8U CN203537553U (en) | 2013-10-18 | 2013-10-18 | An Interface circuit realizing serial port and infrared multiplex functions |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320646815.8U CN203537553U (en) | 2013-10-18 | 2013-10-18 | An Interface circuit realizing serial port and infrared multiplex functions |
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| Publication Number | Publication Date |
|---|---|
| CN203537553U true CN203537553U (en) | 2014-04-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320646815.8U Expired - Fee Related CN203537553U (en) | 2013-10-18 | 2013-10-18 | An Interface circuit realizing serial port and infrared multiplex functions |
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| Country | Link |
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| CN (1) | CN203537553U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105721917A (en) * | 2016-02-24 | 2016-06-29 | 浪潮软件集团有限公司 | Port multiplexing circuit and digital television set top box |
| CN108259953A (en) * | 2018-03-06 | 2018-07-06 | 深圳康佳信息网络有限公司 | Interface multiplexing circuit, method for multiplexing interface and the set-top box of set-top box |
-
2013
- 2013-10-18 CN CN201320646815.8U patent/CN203537553U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105721917A (en) * | 2016-02-24 | 2016-06-29 | 浪潮软件集团有限公司 | Port multiplexing circuit and digital television set top box |
| CN105721917B (en) * | 2016-02-24 | 2018-08-07 | 浪潮软件集团有限公司 | Port multiplexing circuit and digital television set top box |
| CN108259953A (en) * | 2018-03-06 | 2018-07-06 | 深圳康佳信息网络有限公司 | Interface multiplexing circuit, method for multiplexing interface and the set-top box of set-top box |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140409 Termination date: 20161018 |