CN111104360A - NVMe protocol-based solid state disk - Google Patents
NVMe protocol-based solid state disk Download PDFInfo
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- CN111104360A CN111104360A CN201911208773.8A CN201911208773A CN111104360A CN 111104360 A CN111104360 A CN 111104360A CN 201911208773 A CN201911208773 A CN 201911208773A CN 111104360 A CN111104360 A CN 111104360A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
The application discloses a solid state disk based on an NVMe protocol, which comprises a connector, a server side connector and a controller, wherein the connector is used for connecting the server side connector; the controller is used for outputting the first path of PCIe signals and the second path of PCIe signals to the signal multiplexer, and outputting the third path of PCIe signals and the fourth path of PCIe signals to the connector; and the signal multiplexer is used for determining the interface definition type of the server-side connector connected with the connector, outputting the first path of PCIe signals and the second path of PCIe signals to the connector based on the interface definition type of the server-side connector, and sending pins corresponding to the pins of the first path of PCIe signals and the second path of PCIe signals by the server-side connector when the server-side connector is the interface definition type. When the solid state disk is connected with the server side connector defined by U.2 or U.3, the solid state disk can be identified and normally transmits data, and has strong adaptability.
Description
Technical Field
The application relates to the technical field of storage, in particular to a solid state disk based on an NVMe protocol; it also relates to a server.
Background
In order to meet the requirement that a large number of users instantly access a website without causing website paralysis, a data center deploys thousands of servers to provide high-throughput computing power, and each server configures several SSD (Solid State Disk) to ensure low-delay data transmission, thereby promoting rapid growth of the enterprise-level SSD market. According to different protocols, the solid state disk is roughly divided into three types, including a solid state disk (SATA solid state disk) realized by a SATA protocol, a solid state disk (SAS solid state disk) realized by an SAS protocol, and a solid state disk (NVMe-based solid state disk) realized by an NVMe protocol. Because the definition of pins of the connectors of the SATA solid state disk, the SAS solid state disk and the NVMe solid state disk is different, if the solid state disk connected to the server is different, the backplane connected to the solid state disk needs to use different connectors. Aiming at the problems, manufacturers for designing chips for connecting a CPU and a hard disk design a Tri-mode chip, and the Tri-mode chip shares physical pin signals, so that the signals connected to a backboard can be connected with the solid state disks with different protocols to work normally.
However, most of the existing solid state disks based on the NVMe protocol are solid state disks defined based on U.2, and for a solid state disk defined based on U.2, the solid state disk can be identified only when plugged into a server side connector defined by U.2, but cannot be identified when plugged into a server side connector defined by U.3.
In view of this, how to implement the solid state disk to be suitable for both the server-side connector defined by U.2 and the server-side connector defined by U.3 has become an urgent technical problem to be solved by those skilled in the art.
Disclosure of Invention
The solid state disk based on the NVMe protocol is applicable to server side connectors defined by U.2 and U.3 and has strong adaptability.
In order to solve the technical problem, the present application provides a solid state disk based on NVMe protocol, including:
a connector for connecting the server-side connector;
the controller is used for outputting a first path of PCIe signals and a second path of PCIe signals to the signal multiplexer, and outputting a third path of PCIe signals and a fourth path of PCIe signals to the connector;
and the signal multiplexer is used for determining the interface definition type of the server-side connector and outputting the first path of PCIe signals and the second path of PCIe signals to pins corresponding to pins for sending the first path of PCIe signals and the second path of PCIe signals by the server-side connector when the server-side connector is in the interface definition type based on the interface definition type of the server-side connector.
Optionally, the controller is further configured to receive an SMbus signal sent by the server and output a corresponding control signal to the signal multiplexer;
correspondingly, the signal multiplexer is specifically configured to determine the interface definition type of the server-side connector according to the control signal.
Optionally, the signal multiplexer is specifically configured to determine the interface definition type of the server-side connector by identifying a signal of any one or any several of a P2 pin, an E6 pin, and an E16 pin of the server-side connector.
Optionally, the method further includes:
a pull-up resistor; one end of the pull-up resistor is connected with a power supply, and the other end of the pull-up resistor is respectively connected with an S15 pin of the connector and the signal multiplexer;
correspondingly, the signal multiplexer is specifically configured to determine the interface definition type of the server-side connector by identifying the signal of the S15 pin.
Optionally, the signal multiplexer is specifically configured to:
when the interface definition type of the server-side connector is U.2, the signal multiplexer outputs the first path of PCIe signals to the E10 and E11 pins of the connector and outputs the second path of PCIe signals to the E17 and E18 pins of the connector;
when the interface definition type of the server-side connector is U.3, the signal multiplexer outputs the first path of PCIe signals to S2 and S3 pins on the connector and outputs the second path of PCIe signals to S9 and S10 pins on the connector.
Optionally, the controller is specifically configured to output the third PCIe signal to pins S17 and S18 of the connector, and output the fourth PCIe signal to pins S23 and S24 of the connector.
Optionally, the signal multiplexer is specifically a PI3DBS16412 type signal multiplexer.
In order to solve the technical problem, the application further provides a server, wherein the server is provided with the NVMe protocol-based solid state disk as described in any one of the above.
The solid state disk based on the NVMe protocol comprises a connector, a server side connector and a controller, wherein the connector is used for connecting the server side connector; the controller is used for outputting a first path of PCIe signals and a second path of PCIe signals to the signal multiplexer, and outputting a third path of PCIe signals and a fourth path of PCIe signals to the connector; and the signal multiplexer is used for determining the interface definition type of the server-side connector and outputting the first path of PCIe signals and the second path of PCIe signals to pins corresponding to pins for sending the first path of PCIe signals and the second path of PCIe signals by the server-side connector when the server-side connector is in the interface definition type based on the interface definition type of the server-side connector.
Therefore, the solid state disk based on the NVMe protocol provided by the application is additionally provided with the signal multiplexer, so that the interface definition type of the server-side connector is confirmed through the signal multiplexer, and the pins are switched according to the interface definition type of the server-side connector, so that the solid state disk can normally transmit data with the server under the condition that the interface definition type of the server-side connector is U.2 or U.3, the purpose that the solid state disk is suitable for both the server-side connector defined by U.2 and the server-side connector defined by U.3 is achieved, and the adaptability and the product competitiveness of the solid state disk are greatly enhanced.
The server provided by the application also has the technical effects.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the prior art and the embodiments are briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic diagram of a solid state disk based on NVMe protocol according to an embodiment of the present application;
fig. 2 is a schematic diagram of a signal multiplexer according to an embodiment of the present disclosure.
Detailed Description
The solid state disk based on the NVMe protocol is applicable to server side connectors defined by U.2 and U.3 and has strong adaptability.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic diagram of a solid state disk based on NVMe protocol according to an embodiment of the present application; referring to fig. 1, the solid state disk includes:
a connector 10 for connecting a server-side connector;
the controller 20 is configured to output the first path of PCIe signals and the second path of PCIe signals to the signal multiplexer 30, and output the third path of PCIe signals and the fourth path of PCIe signals to the connector 10;
and the signal multiplexer 30 is configured to determine an interface definition type of the server-side connector, and output the first path of PCIe signals and the second path of PCIe signals to the connector 10 based on the interface definition type of the server-side connector, and the server-side connector is configured to send pins corresponding to the pins of the first path of PCIe signals and the second path of PCIe signals when the server-side connector is the interface definition type.
Specifically, the connector 10 is responsible for connecting a server-side connector, i.e., a hard disk connector on a server backplane. The controller 20 is respectively connected to the connector 10 and the signal multiplexer 30, and configured to output the first path of PCIe signal and the second path of PCIe signal to the signal multiplexer 30, so as to output the first path of PCIe signal and the second path of PCIe signal to pins on the connector 10, which can be recognized by a server and implement normal data transmission, through the signal multiplexer 30. In addition, the controller 20 also directly outputs the third PCIe signal and the fourth PCIe signal to the connector.
It should be noted that the descriptions of the first, second, third and fourth are only used to distinguish the PCIe signals, and do not indicate any actual sequential or magnitude relationship between the PCIe signals.
The signal multiplexer 30 is respectively connected to the controller 20 and the connector 10, and is responsible for determining the interface definition type of the server-side connector, and further outputting the first path of PCIe signal and the second path of PCIe signal to corresponding pins on the connector 10 according to the interface definition type of the server-side connector, so that the server and the solid state disk can normally transmit the first path of PCIe signal and the second path of PCIe signal under the condition that the interface definition type of the server-side connector is defined as U.2 or U.3.
In a specific embodiment, the controller 20 is further configured to receive an SMbus signal sent by the server and output a corresponding control signal to the signal multiplexer 30; correspondingly, the signal multiplexer 30 is specifically configured to determine the interface definition type of the server-side connector according to the control signal.
Specifically, in the present embodiment, the way for the signal multiplexer 30 to determine the interface definition type of the server-side connector is as follows: the server sends the SMbus signal to the controller 20 of the solid state disk through the SMbus interface, i.e. the pin E23 and the pin E24 of the server-side connector, and the controller 20 can know the interface definition type of the server-side connector according to the SMbus signal, and further outputs a corresponding control signal to the signal multiplexer 30, so that the signal multiplexer 30 determines the interface definition type of the server-side connector according to the control signal.
In addition, in another specific embodiment, the signal multiplexer 30 is specifically configured to determine the interface definition type of the server-side connector by identifying a signal of any one or any several of the P2 pin, the E6 pin, and the E16 pin of the server-side connector.
Specifically, referring to table 1, U.2 and U.3 have different definitions of the P2 pin, the E6 pin and the E16 pin, based on which the signal multiplexer 30 can be connected to any one or any several of the P2 pin, the E6 pin and the E16 pin of the connector 10, and since the connector 10 of the solid-state hard disk corresponds to each pin of the server-side connector, the signal multiplexer 30 can determine the interface definition type of the server-side connector by identifying any one or any several of the P2 pin, the E6 pin and the E16 pin of the server-side connector after the connector 10 of the solid-state hard disk is connected to the server-side connector.
Tables 1 U.2 and U.3 define the pin definition table of the lower connector
Further, in another specific embodiment, the NVMe protocol-based solid state disk further includes a pull-up resistor; one end of the pull-up resistor is connected with the power supply, and the other end is respectively connected with the S15 pin of the connector 10 and the signal multiplexer 30; correspondingly, signal multiplexer 30 is specifically configured to determine the type of hard disk interface by identifying the signal at pin S15.
Specifically, referring to table 1, U.2 is defined differently from S15 under the definition of U.3, S15 under the definition of U.3 is HPTO, and S15 under the definition of U.2 is Reserved. Therefore, in this embodiment, a pull-up resistor is added in the solid state disk, and one end of the pull-up resistor is connected to the power supply, and the other end is connected to the S15 pin of the connector 10 and the signal multiplexer 30. When the solid state disk is inserted into the server-side connector defined by U.2, the S15 pin sensed by the solid state disk at this time is at a high level, and when the solid state disk is inserted into the server-side connector defined by U.3, since the S15 pin is grounded at the server side at this time, the solid state disk can sense that the S15 pin is at a low level, so that the interface definition type of the server-side connector can be determined by distinguishing the level of the S15 pin.
Upon determining whether the type of the server-side connector is the connector defined by U.2 or the connector defined by U.3, the signal multiplexer 30 outputs the first path of PCIe signals and the second path of PCIe signals to respective pins on the connector 10. Specifically, as shown in table 1, U.3 is defined for all of the S1-S28 pins in the connector, and U.2 is not defined for S2, S3, S5, S6, S10, S11, S12, and S13 pins. U.2 of pins E1-E25 are all defined, and U.3 does not define pins E10, E11, E13, E14, E17, E18, E20 and E21, and since the pins defined by U.2 and U.3 are different, the solid state disk defined by U.2 cannot work when the connector 10 of the solid state disk defined by U.2 is plugged into the connector defined by U.3 on the server backplane. In order to achieve the purpose that the solid state disk can normally work no matter the solid state disk is plugged into a server-side connector defined in U.2 or a server-side connector defined in U.3, the NVMe protocol-based solid state disk provided by the application is additionally provided with a signal multiplexer 30, and the signal multiplexer 30 is respectively connected with a controller 20 of the solid state disk and a connector 10 connected with the server-side connector to the outside. And the signal multiplexer 30 is specifically connected to the pins of the connector 10 corresponding to the pins of the server-side connector for transceiving the first PCIe signal and the second PCIe signal when the interface definition type of the server-side connector is U.2, and connected to the pins of the connector 10 corresponding to the pins of the server-side connector for transceiving the first PCIe signal and the second PCIe signal when the interface definition type of the server-side connector is U.3.
Since all of the pins S1-S28 are defined in U.3, whereas pins S2, S3, S5, S6, S10, S11, S12 and S13 in U.2 are not defined. For pins E1-E25, U.2 are all defined, and U.3 does not define pins E10, E11, E13, E14, E17, E18, E20 and E21. The signal multiplexer 30 is thus connected to the S2, S3, S5, S6, S10, S11, S12 and S13 pins and the E10, E11, E13, E14, E17, E18, E20 and E21 pins of the connector 10.
Therefore, if the connector defined by U.2 is disposed on the server backplane, the signal multiplexing connector transmits the first PCIe signal and the second PCIe signal output by the controller 20 to corresponding pins of the connector on the server backplane through the pins E10, E11, E17, and E18. Similarly, the signal multiplexer 30 may also receive the first PCIe signal and the second PCIe signal sent by the server through E13, E14, E20, and E21 pins on the connector 10, and further output the first PCIe signal and the second PCIe signal to the controller 20 of the solid state disk, so as to implement normal transceiving of the first PCIe signal and the second PCIe signal between the solid state disk and the server when the connector defined by U.2 is arranged on the server backplane.
If the connector defined by U.3 is disposed on the server backplane, the signal multiplexing connector transmits the first PCIe signal and the second PCIe signal output by the controller 20 to corresponding pins of the connector on the server backplane through the S2, S3, S9, and S10 pins at this time. Similarly, the signal multiplexer 30 may further receive the first PCIe signal and the second PCIe signal sent by the server through the S5, S6, S12, and S13 pins, and further output the first PCIe signal and the second PCIe signal to the controller 20 of the solid state disk, so that when a connector defined by U.3 is arranged on the server backplane, the first PCIe signal and the second PCIe signal between the solid state disk and the server are normally received and sent.
In a specific embodiment, the signal multiplexer 30 is specifically configured to, when the interface definition type of the server-side connector is U.2, output a first PCIe signal to pins E10 and E11 of the connector, and output a second PCIe signal to pins E17 and E18 of the connector; when the interface definition type of the server-side connector is U.3, the signal multiplexer outputs the first path of PCIe signals to the S2 and S3 pins on the connector and outputs the second path of PCIe signals to the S9 and S10 pins on the connector.
Furthermore, in one embodiment, signal multiplexer 30 may be a PI3DBS16412 type signal multiplexer 30.
Specifically, referring to the schematic diagram of the PI3DBS16412 type signal multiplexer 30 shown in fig. 2, pins a0+ to A3-of the signal multiplexer 30 are connected to the controller 20 of the solid state disk, and pins B0+ to C3-of the signal multiplexer 30 are connected to the connector 10. Specifically, A0+, A0-, A1+ and A1-channels that can be connected to the controller 20 for transmitting the first path of PCIe signals, and A2+, A2-, A3+ and A3-channels that can be connected to the controller 20 for transmitting the second path of PCIe signals. B0+ and B0-are respectively connected to the S2 pin and the S3 pin of the connector 10, and B1+ and B1-are respectively connected to the S6 pin and the S5 pin of the connector 10. C0+ and C0-may be respectively connected to the E10 pin and E11 pin of the connector 10, and C1+ and C1-may be respectively connected to the E14 pin and E13 pin of the connector 10. B2+ and B2-are respectively connected to the S9 pin and the S10 pin of the connector 10, and B3+ and B3-are respectively connected to the S13 pin and the S12 pin of the connector 10. C0+ and C0-may be respectively connected to the E17 pin and E18 pin of the connector 10, and C1+ and C1-may be respectively connected to the E21 pin and E20 pin of the connector 10.
Therefore, when the server backplane is provided with the connector defined by U.2, since the pins E10, E11, E13, E14, E17, E18, E20 and E21 on the connector 10 provided on the server backplane at this time are defined, and the pins S2, S3, S5, S6, S10, S11, S12 and S13 are not defined, at this time, the signal multiplexer 30 closes the switches K2 and K4, so that the first PCIe signal is output to the server through the pins E10 and E11, and the first PCIe signal sent by the server can be received through the pins E13 and E14, the second PCIe signal is output to the server through the pins E17 and E18, and the second PCIe signal sent by the server can be received through the pins E20 and E21.
When the server backplane is provided with the connector defined by U.3, since the pins S2, S3, S5, S6, S10, S11, S12 and S13 on the connector provided on the server backplane are defined at this time, and the pins E10, E11, E13, E14, E17, E18, E20 and E21 are not defined at this time, the signal multiplexer 30 closes the switches K1 and K3 at this time, so that the first PCIe signal is output to the server through the pins S2 and S3, and the first PCIe signal sent by the server can be received through the pins S5 and S6, the second PCIe signal is output to the server through the pins S9 and S10, and the second PCIe signal sent by the server can be received through the pins S12 and S13.
Further, in one embodiment, the controller 20 is specifically configured to output the third PCIe signal to the pins S17 and S18 of the connector 10, and output the fourth PCIe signal to the pins S23 and S24 of the connector 10. That is, the channel through which the controller 20 transmits the third PCIe signal may be connected to the pins S17, S18, S20, and S21 of the connector 10, and the channel through which the controller 20 transmits the fourth PCIe signal may be connected to the pins S23, S24, S26, and S27 of the connector 10, since the pins S17, S18, S20, S21, S23, S24, S26, and S27 of the server-side connector are defined regardless of whether the U.2-defined connector or the U.3-defined connector is disposed on the server backplane, the third PCIe signal and the fourth PCIe signal may be recognized by the server when the solid state disk outputs the third PCIe signal to the server via the pins S17 and S18 and outputs the fourth PCIe signal to the server via the pins S23 and S24, regardless of whether the connector defined by U.2 or the connector defined by U.3 is disposed on the server backplane. Certainly, the solid state disk can also receive the third PCIe signal output by the server through the S20 and S21 pins and receive the fourth PCIe signal output by the server through the S26 and S27 pins, so as to achieve the purpose of normally transmitting the third PCIe signal and the fourth PCIe signal between the server and the solid state disk.
In summary, the NVMe protocol-based solid-state disk provided by the present application includes a connector for connecting a server-side connector; the controller is used for outputting a first path of PCIe signals and a second path of PCIe signals to the signal multiplexer, and outputting a third path of PCIe signals and a fourth path of PCIe signals to the connector; and the signal multiplexer is used for determining the interface definition type of the server-side connector and outputting the first path of PCIe signals and the second path of PCIe signals to pins corresponding to pins for sending the first path of PCIe signals and the second path of PCIe signals by the server-side connector when the server-side connector is in the interface definition type based on the interface definition type of the server-side connector. The solid state disk based on the NVMe protocol is additionally provided with the signal multiplexer, so that the interface definition type of the server-side connector is confirmed through the signal multiplexer, and the pins are switched according to the interface definition type of the server-side connector, so that the solid state disk can perform normal data transmission with a server under the condition that the interface definition type of the server-side connector is U.2 or U.3, the purpose that the solid state disk is suitable for both the server-side connector defined by U.2 and the server-side connector defined by U.3 is achieved, and the adaptability and the product competitiveness of the solid state disk are greatly enhanced.
The application also provides a server, and the server is provided with the solid state disk based on the NVMe protocol. Introduction to the server, the present application does not need to be described herein any more, and may refer to the above-mentioned embodiment of the solid state disk.
Because the situation is complicated and cannot be illustrated by a list, those skilled in the art can appreciate that there can be many examples in combination with the actual situation under the basic principle of the embodiments provided in the present application and that it is within the scope of the present application without sufficient inventive effort.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The NVMe protocol-based solid state disk provided by the present application is described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (8)
1. A solid state disk based on NVMe protocol, comprising:
a connector for connecting the server-side connector;
the controller is used for outputting a first path of PCIe signals and a second path of PCIe signals to the signal multiplexer, and outputting a third path of PCIe signals and a fourth path of PCIe signals to the connector;
and the signal multiplexer is used for determining the interface definition type of the server-side connector and outputting the first path of PCIe signals and the second path of PCIe signals to pins corresponding to pins for sending the first path of PCIe signals and the second path of PCIe signals by the server-side connector when the server-side connector is in the interface definition type based on the interface definition type of the server-side connector.
2. The solid state disk of claim 1, wherein the controller is further configured to receive an SMbus signal sent by a server and output a corresponding control signal to the signal multiplexer;
correspondingly, the signal multiplexer is specifically configured to determine the interface definition type of the server-side connector according to the control signal.
3. The solid state disk of claim 1, wherein the signal multiplexer is specifically configured to determine the interface definition type of the server-side connector by identifying a signal of any one or any several of a P2 pin, an E6 pin, and an E16 pin of the server-side connector.
4. The solid state disk of claim 1, further comprising:
a pull-up resistor; one end of the pull-up resistor is connected with a power supply, and the other end of the pull-up resistor is respectively connected with an S15 pin of the connector and the signal multiplexer;
correspondingly, the signal multiplexer is specifically configured to determine the interface definition type of the server-side connector by identifying the signal of the S15 pin.
5. The solid state disk of claim 1, wherein the signal multiplexer is specifically configured to:
when the interface definition type of the server-side connector is U.2, the signal multiplexer outputs the first path of PCIe signals to the E10 and E11 pins of the connector and outputs the second path of PCIe signals to the E17 and E18 pins of the connector;
when the interface definition type of the server-side connector is U.3, the signal multiplexer outputs the first path of PCIe signals to S2 and S3 pins on the connector and outputs the second path of PCIe signals to S9 and S10 pins on the connector.
6. The solid state disk of claim 5, wherein the controller is specifically configured to output the third PCIe signal to S17 and S18 pins of the connector and the fourth PCIe signal to S23 and S24 pins of the connector.
7. The solid state disk of claim 6, wherein the signal multiplexer is specifically a PI3DBS16412 type signal multiplexer.
8. A server, characterized in that the server is provided with the NVMe protocol-based solid state disk according to any one of claims 1 to 7.
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| CN201911208773.8A CN111104360B (en) | 2019-11-30 | 2019-11-30 | NVMe protocol-based solid state disk |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112579001A (en) * | 2020-12-11 | 2021-03-30 | 卓曜（北京）科技有限公司 | Storage device and data processing system |
| CN114443522A (en) * | 2021-12-31 | 2022-05-06 | 苏州浪潮智能科技有限公司 | Hard disk backboard device and server |
| CN115061958A (en) * | 2022-07-05 | 2022-09-16 | 中国长城科技集团股份有限公司 | Hard disk identification method, identification system, storage medium and computer equipment |
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| CN114443522B (en) * | 2021-12-31 | 2023-08-11 | 苏州浪潮智能科技有限公司 | Hard disk backboard device and server |
| CN115061958A (en) * | 2022-07-05 | 2022-09-16 | 中国长城科技集团股份有限公司 | Hard disk identification method, identification system, storage medium and computer equipment |
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