CN114999415B - Liquid crystal display device and main board thereof - Google Patents
Liquid crystal display device and main board thereof Download PDFInfo
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- CN114999415B CN114999415B CN202210560764.0A CN202210560764A CN114999415B CN 114999415 B CN114999415 B CN 114999415B CN 202210560764 A CN202210560764 A CN 202210560764A CN 114999415 B CN114999415 B CN 114999415B
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- 238000004891 communication Methods 0.000 claims abstract description 16
- 238000006243 chemical reaction Methods 0.000 claims description 15
- 238000013461 design Methods 0.000 description 12
- 230000002093 peripheral effect Effects 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G3/2096—Details of the interface to the display terminal specific for a flat panel
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Abstract
The utility model discloses a liquid crystal display device and a main board thereof, wherein the liquid crystal display device comprises: the device comprises a main board, a logic adapter plate connected with the main board and a liquid crystal display screen connected with the logic adapter plate; the main board comprises a first interface and a second interface; the logic adapter plate is provided with a third interface, a fourth interface and a fifth interface; the logic adapter board is connected with the first interface or the second interface through a third interface so as to be connected with the main board, and is connected with the liquid crystal display screen through a fourth interface and a fifth interface; the first interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area, a display data area and a data communication area; the second interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area and a display data area. The utility model is generally used for various liquid crystal display screens and reduces interface cost.
Description
Technical Field
The utility model relates to the technical field of display, in particular to a liquid crystal display device and a main board thereof.
Background
The existing television ultra-high definition liquid crystal display screen driving circuit is mainly divided into three modes: A. the independent Tcon board mode is input BY adopting a V-BY-ONE standard interface, and a screen manufacturer self-defines a screen interface for output; B. in the Open Cell mode, a Tcon IC is integrated in a main Chip (SOC) and is integrated On a main board together with a peripheral PM/GAMMA/LEVEL SHIFT circuit (level conversion unit), and then an access screen is output by matching with a screen interface; C. the TCONLESS adapter plate mode is that the Tcon Ic is integrated in the SOC, the TCON peripheral PM/GAMMA/LEVEL SHIFT circuit is integrated on the adapter plate, the main board and the adapter plate are connected through a special interface, and then the interface is output by a user-defined screen interface of an adapter plate matching screen manufacturer.
Aiming at the TCONLESS adapter plate mode, the existing market does not have a unified design scheme which can be compatible with interface definition of various screen interfaces and has complete functional requirements, so that the problem of universality of an integrated circuit board is solved.
Accordingly, the prior art is still in need of improvement and development.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present utility model is directed to a liquid crystal display device and a motherboard thereof, so as to solve the problem that there is no unified design scheme compatible with interface definition and functional requirements of various screen interfaces in the TCONLESS adapter mode, so that the integrated circuit board cannot be commonly used.
The technical scheme of the utility model is as follows:
a liquid crystal display device, comprising: the device comprises a main board, a logic adapter board connected with the main board and a liquid crystal display connected with the logic adapter board; wherein,
the main board comprises a first interface and a second interface;
the logic adapter plate is provided with a third interface, a fourth interface and a fifth interface;
the logic adapter board is connected with the first interface or the second interface through the third interface so as to be connected with the main board, and is connected with the liquid crystal display through the fourth interface and the fifth interface;
the first interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area, a display data area and a data communication area;
the second interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area and a display data area.
In a further arrangement of the utility model, the first to eighth pins of the first interface are defined as VCC; the ninth pin of the first interface is defined as NC; the tenth pin to the twelfth pin of the first interface are defined as GND; the thirteenth pin and the fourteenth pin of the first interface are respectively defined as P_SDA and P_SCL; the fifteenth pin and the sixteenth pin of the first interface are respectively defined as test_io and VB1_HPN; the seventeenth pin of the first interface is defined as a Panal_EN, and the eighteenth pin to the twenty third pin of the first interface are respectively defined as TCON_Lc2, TCON_Lc1, TCON_CPV2, TCON_CPV1, TCON_STV2 and TCON_STV1; the twenty-fourth pin of the first interface is defined as LOCOUT; the second fifteenth to sixtieth pins of the first interface are defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, data+, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+, GND, respectively; the sixty-two to sixty-eight pins of the first interface are respectively defined as FLASH_WP, FLASH_DO, FLASH_CS, FLASH_ DI, GND, FLASH _CLK and GND.
In a further arrangement of the utility model, the first to seventh pins of the second interface are defined as VCC; the eighth pin of the second interface is defined as NC; the ninth to eleventh pins of the second interface are defined as GND; the twelfth leg and the thirteenth leg of the second interface are respectively defined as P_SDA and P_SCL; the fourteenth pin and the fifteenth pin of the second interface are respectively defined as TEST_IO and VB1_HPN; the seventeenth pin to the twenty second pin of the second interface are respectively defined as TCON_Lc2, TCON_Lc1, TCON_CPV2, TCON_CPV1, TCON_STV2 and TCON_STV1; a twenty-third leg of the second interface is defined as LOCOKOUT; the twenty-four to sixty pins of the second interface are defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, data+, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+ and GND, respectively.
According to the utility model, the third interface is connected with the first interface or the third interface is connected with the second interface by adopting a flexible flat cable; and the liquid crystal display screen is connected with the fourth interface and the fifth interface by adopting a flexible flat cable.
According to a further arrangement of the utility model, the motherboard further comprises: and the VBO interface is respectively connected with the first interface and the second interface.
According to a further arrangement of the utility model, the motherboard further comprises: and the main chip is respectively connected with the first interface and the second interface.
In a further arrangement of the present utility model, the logic patch panel further includes: the display device comprises a power management unit, a display parameter unit and a power conversion unit, wherein the power management unit, the display parameter unit and the output end of the power conversion unit are connected with the liquid crystal display.
According to the utility model, the first interface and the second interface are overlapped on the main board.
The liquid crystal display main board comprises a first interface and a second interface, wherein the first interface and the second interface are overlapped on the liquid crystal display main board; wherein,
the first interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area, a display data area and a data communication area;
the second interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area and a display data area.
In a further arrangement of the utility model, the first to eighth pins of the first interface are defined as VCC; the ninth pin of the first interface is defined as NC; the tenth to twelfth pins of the first interface are defined as GND; the thirteenth pin and the fourteenth pin of the first interface are respectively defined as P_SDA and P_SCL; the fifteenth pin and the sixteenth pin of the first interface are respectively defined as test_io and VB1_HPN; the seventeenth pin of the first interface is defined as a Panal_EN, and the eighteenth pin to the twenty third pin of the first interface are respectively defined as TCON_Lc2, TCON_Lc1, TCON_CPV2, TCON_CPV1, TCON_STV2 and TCON_STV1; the twenty-fourth pin of the first interface is defined as LOCOUT; the second fifteenth pin to the sixtieth pin of the first interface are defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, data+, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+, GND, respectively; the sixty-eighth pin to the sixty-eighth pin of the first interface are respectively defined as FLASH_WP, FLASH_DO, FLASH_CS, FLASH_ DI, GND, FLASH _CLK and GND;
the first to seventh pins of the second interface are defined as VCC; the eighth pin of the second interface is defined as NC; the ninth to eleventh pins of the second interface are defined as GND; the twelfth pin and the thirteenth pin of the second interface are respectively defined as P_SDA and P_SCL; the fourteenth pin and the fifteenth pin of the second interface are respectively defined as TEST_IO and VB1_HPN; the seventeenth pin to the twenty second pin of the second interface are respectively defined as TCON_Lc2, TCON_Lc1, TCON_CPV2, TCON_CPV1, TCON_STV2 and TCON_STV1; a twenty-third leg of the second interface is defined as LOCOKOUT; the twenty-fourth pin through the sixtieth pin of the second interface are defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, data+, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+ and GND, respectively.
The utility model provides a liquid crystal display device and a main board thereof, wherein the liquid crystal display device comprises: the device comprises a main board, a logic adapter board connected with the main board and a liquid crystal display connected with the logic adapter board; the main board comprises a first interface and a second interface; the logic adapter plate is provided with a third interface, a fourth interface and a fifth interface; the logic adapter board is connected with the first interface or the second interface through the third interface so as to be connected with the main board, and is connected with the liquid crystal display through the fourth interface and the fifth interface; the first interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area, a display data area and a data communication area; the second interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area and a display data area. The utility model can be compatible with the interface definition of various liquid crystal display screens by defining the pins of the first interface and the second interface on the main board, so that the main board is commonly used for various liquid crystal display screens. In addition, the mainboard can select the first interface or the second interface according to the interface requirement of the liquid crystal display, the mainboard end can be kept unchanged, the requirements of different liquid crystal display interfaces can be met only by correspondingly replacing different logic adapter plates, and the interface cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained from the structures shown in these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a liquid crystal display device according to the present utility model.
Fig. 2 is a pin diagram of a first interface in the present utility model.
Fig. 3 is a pin diagram of a second interface in the present utility model.
Fig. 4 is a schematic structural diagram of the first interface and the second interface layout on the PCB according to the present utility model.
The marks in the drawings are as follows: 100. a main board; 101. a first interface; 102. a second interface; 103. a main chip; 104. a VBO interface; 200. a logic adapter plate; 201. a third interface; 202. a fourth interface; 203. a fifth interface; 204. a power management unit; 205. a display parameter unit; 206. a power supply conversion unit; 300. a flexible flat cable; 400. a liquid crystal display.
Detailed Description
The utility model provides a liquid crystal display device and a mainboard thereof, wherein the liquid crystal display device can be devices with liquid crystal display screens such as televisions and displays, and is particularly suitable for application of 4K ultra-high definition display screens in televisions.
In order to make the objects, technical solutions and effects of the present utility model clearer and more obvious, the present utility model will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.
In the description and claims, unless the context specifically defines the terms "a," "an," "the," and "the" include plural referents. If there is a description of "first", "second", etc. in an embodiment of the present utility model, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature.
It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.
It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.
The inventor researches find that the current screen input end has a plurality of custom interface modes, such as protocols EPI, CEDS, CHPI, USI-T, CSPI and the like. Because the display screen glass manufacturers at home and abroad do not form unified standards for the screen input end interfaces, the driving circuit implementation scheme interfaces are different, and the integrated circuit board signal processing and screen driving mode is adopted, circuits with different interfaces are required to be developed, so that the problems of low development efficiency, poor universality of the integrated circuit board and the like are caused, and the development cost is too high.
Aiming at the TCONLESS adapter plate mode, the existing market does not have a unified design scheme which can be compatible with interface definition of various screen interfaces and has complete functional requirements, so that the problem of universality of an integrated circuit board is solved. The existing interface definition is too redundant, the practical application is not simple enough and the circuit design is complex, and the cost waste exists to a certain extent.
In view of the above technical problems, the present utility model provides a liquid crystal display device and a motherboard thereof, which can be compatible with interface definitions of various liquid crystal display screens by defining pins of a first interface and a second interface on the motherboard, so that the motherboard is commonly used for various liquid crystal display screens. In addition, the mainboard can select the first interface or the second interface according to the interface requirement of the liquid crystal display, the mainboard end can be kept unchanged, and the requirements of different liquid crystal display interfaces can be met only by correspondingly replacing different logic adapter plates, so that the circuit of the interface is simpler, and the interface cost is reduced.
Referring to fig. 1 to 3, the present utility model provides a preferred embodiment of a liquid crystal display device.
As shown in fig. 1 to 3, the present utility model provides a liquid crystal display device, which includes: a main board 100, a logic adapter board 200 connected with the main board 100, and a liquid crystal display 400 connected with the logic adapter board 200; wherein, the motherboard 100 includes a first interface 101 and a second interface 102; the logic adapter board 200 is provided with a third interface 201, a fourth interface 202 and a fifth interface 203; the logic adapter board 200 is connected with the first interface 101 or the second interface 102 through the third interface 201 to be connected with the motherboard 100, and is connected with the liquid crystal display 400 through the fourth interface 202 and the fifth interface 203; the first interface 101 has a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area, a display data area and a data communication area; the second interface 102 has a power supply area, a short circuit prevention area, a ground area, a data burning area, an interface detection area, an enable control area, a drive control area, a lock area, and a display data area.
Specifically, the liquid crystal display device in the present utility model adopts a TCONLESS adapter BOARD module, that is, adopts a logic adapter BOARD (TCONLESS BOARD) 200, and the logic adapter BOARD 200 is connected with the first interface 101 or the second interface 102 on the motherboard 100 through the third interface 201, so as to realize connection with the motherboard 100, where a pin of the third interface 201 corresponds to a pin of the first interface 101 or corresponds to a pin of the second interface 102. The first interface 101 and the second interface 102 each have a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area and a display data area, and the first interface 101 also has a data communication area. It can be seen that the interface of the motherboard 100 covers the communication control function and Demura (eliminating image non-uniformity) function required by the lcd 400, and can support the data signals, clk signals, driving control signals and power supply lines required by the interfaces EPI, CEDS, CHPI, USI-T, CSPI, so that the interface definition of various lcds 400 can be compatible, and the motherboard 100 is generally used for various lcds.
The first interface 101 has 68pin, the second interface 102 has 60pin, in practical application, the first interface 101 or the second interface 102 may be selected according to the interface requirement of the lcd 400 (if the lcd 400 needs to perform a Demura function, the first interface 101 is selected, otherwise the second interface 102 is selected), the end of the motherboard 100 may remain unchanged, and only needs to correspondingly replace different logic adapter boards 200, software adapts corresponding screen parameters and control signal timing, so as to meet the requirements of different lcd interfaces, thereby implementing driving display of various lcds 400, simplifying circuit design and interface definition, and reducing interface cost. The first interface 101 and the second interface 102 can be compatible with the application of a 4K ultra-high-definition liquid crystal display screen with the size of 43-75 inches.
Referring to fig. 1, in some embodiments, a main chip 103 is disposed on the motherboard 100, and the main chip 103 is connected to the first interface 101 and the second interface 102, respectively.
Referring to fig. 1, the logic adapter board 200 further includes: the display device comprises a power management unit 204, a display parameter unit 205 and a power conversion unit 206, wherein the output ends of the power management unit 204, the display parameter unit 205 and the power conversion unit 206 are connected with the liquid crystal display 400.
The main chip 103 may perform data writing on a peripheral Power Management Unit (PMU) 204, a display parameter unit (Gamma) 205, and a power conversion unit (Level Shfit) 206 by using I2C communication for writing.
Referring to fig. 1, in some embodiments, the motherboard 100 further includes: the VBO (V-BY-ONE) interface, where the VBO interface 104 is connected to the first interface 101 and the second interface 102, and through cooperation of software setting, data can be converted into data transmission of the existing VBO interface 104, so as to implement signal detection using the motherboard 100.
Referring to fig. 1 and 3, in some embodiments, the first to eighth pins (i.e., power supply areas) of the first interface 101 are defined as VCC, and the circuit design power supply satisfies that 8 paths of currents are 4A;
the ninth leg (i.e., the short-circuit prevention area) of the first interface 101 is defined as NC, and can be used to prevent the VCC12V or the ground GND from being shorted. The tenth to twelfth pins (ground areas) of the first interface 101 are defined as GND;
the thirteenth pin and the fourteenth pin (i.e., the data writing area) of the first interface 101 are communication signal pins, respectively defined as p_sda and p_scl, and the main chip 103 may use I2C communication to perform data writing on the peripheral power management unit 204, the display parameter unit 205 and the power conversion unit 206 to provide writing for writing, and the pull-up 3.3V may be reserved by the main chip 103 or the logic adapter board 200;
the fifteenth pin and the sixteenth pin (i.e., interface detection areas) of the first interface 101 are respectively defined as test_io and vb1_hpn, and are reserved as interface detection pins of the motherboard 100, and are converted into V-BY-ONE interface data of the existing standard BY making different screen driving data through an external module, and then are subjected to circuit detection;
a seventeenth pin (enable control area) of the first interface 101 is defined as a pin_en, and is connected to an EN pin of the power management unit 204, for enabling control use by the power management unit 204;
the eighteenth leg to the twenty third leg (driving control area) of the first interface 101 are respectively defined as tcon_lc2, tcon_lc1, tcon_cpv2, tcon_cpv1, tcon_stv2, tcon_stv1, and are used for connecting 6ch control signals required by the screen driving power conversion unit 206, and control IO ports of the 6 main chips 103, corresponding to STV1, STV2/TE/CLR, CPV1, CPV2, LC1, LC2/RST/CLR, where STV2 can be multiplexed with TE and CLR doing functions of the screen, and LC2 can be multiplexed with RST and CLR doing functions of the screen;
the twenty-four pins (locking area) of the first interface 101 are LOCKOUT signal pins, defined as LOCKOUT, and are transmitted back to the main chip 103 from the LCD 400 end, and are compatible for LOCK signal use during VBO conversion;
the second to sixty pins (display DATA areas) of the first interface 101 are defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, data+, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+, GND, and all 12 sets of DATA pairs required for the display of the DATA signal pins and the signal ground GND of the lcd 400, and compatible with the panel interfaces EPI, CEDS, CHPI, USI-T, CSPI, may support the transmission rate of 1.5Gbps, 3.0Gbps, and 4.0 Gbps;
the sixty-second to sixty-eighth pins (data communication areas) of the first interface 101 are respectively defined as flash_wp, flash_do, flash_cs, flash_ DI, GND, FLASH _clk and GND, and are used for the lcd 400 with the Demura function, where flash_do corresponds to the spi_do of the main chip 103 and corresponds to the spi_di of the lcd terminal, and flash_di corresponds to the spi_di of the main chip 103 and corresponds to the spi_do of the lcd terminal.
Referring to fig. 1 and 2, in some embodiments, the first pin to the seventh pin (i.e., the power supply area) of the second interface 102 are defined as VCC, and the circuit design power supply satisfies that 8 paths of currents are 3.5A;
the eighth leg of the second interface 102 is defined as NC (i.e. a short-circuit prevention area) and can be used to prevent the VCC12V or the ground GND from being shorted. The tenth to twelfth pins (ground areas) of the second interface 102 are defined as GND;
the ninth to eleventh pins (ground areas) of the second interface 102 are defined as GND;
the twelfth pin and the thirteenth pin (i.e., the data writing area) of the second interface 102 are communication signal pins, respectively defined as p_sda and p_scl, the main chip 103 may use I2C communication to perform data writing on the peripheral circuit, the main chip 103 may use I2C communication to perform data writing on the peripheral power management unit 204, the display parameter unit 205 and the power conversion unit 206 for writing, and the pull-up 3.3V may be reserved by the main chip 103 end or reserved by the logic adapter board 200;
the fourteenth pin and the fifteenth pin (i.e., interface detection areas) of the second interface 102 are respectively defined as test_io and vb1_hpn, and are reserved as interface detection pins of the motherboard 100, and are converted into the V-BY-ONE interface data of the existing standard BY making different screen driving data through an external module, and then are subjected to circuit detection;
the sixteenth pin (enable control area) of the second interface 102 is defined as panal_en, and is connected to the EN pin of the power management unit 204, for enabling control usage by the power management unit 204;
seventeenth to twenty-second pins (driving control areas) of the second interface 102 are respectively defined as tcon_lc2, tcon_lc1, tcon_cpv2, tcon_cpv1, tcon_stv2, tcon_stv1, and are used for connecting 6ch control signals required by the screen driving power conversion unit 206 to control IO ports of the 6 main chips 103, and correspond to STV1, STV2/TE/CLR, CPV1, CPV2, LC1, LC2/RST/CLR, wherein STV2 can be multiplexed with TE and CLR functions of the screen, LC2 can be multiplexed with RST and CLR functions of the screen;
the second thirteenth pin (LOCK area) of the second interface 102 is a LOCK signal pin, defined as LOCK signal, and is transmitted back to the main chip 103 from the lcd 400 end, and is compatible with LOCK signal when VBO conversion is performed;
the twenty-fourth pin to sixtieth pin (display DATA area) of the second interface 102 are defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, data+, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+ and GND, respectively, and can support 1.5Gbps, 3.0Gbps, 4.0Gbps transmission rate for all 12 sets of DATA pairs required for the display DATA signal pins and signal ground GND of the lcd, compatible with the EPI, CEDS, CHPI, USI-T, CSPI, etc. of the screen interfaces.
Referring to fig. 1, in a further implementation of an embodiment, a flexible flat cable (Flexible Flat Cable, FFC) 300 is used to connect the third interface 201 with the first interface 101 or the third interface 201 with the second interface 102; the liquid crystal display 400 is connected to the fourth interface 202 and the fifth interface 203 by using a flexible flat cable 300.
Specifically, the first interface 101, the second interface 102, the third interface 201, the fourth interface 202 and the fifth interface 203 are flexible flat cable interfaces (FFC interfaces), the third interface 201 and the first interface 101 or the third interface 201 and the second interface 102 are connected by using a flexible flat cable 300, when the third interface 201 and the first interface 101 are connected, a 68pin flexible flat cable is used, and when the third interface 201 and the second interface 102 are connected, a 60pin flexible flat cable is used. The liquid crystal display 400 is connected to the fourth interface 202 and the fifth interface 203 by using a flexible flat cable 300.
Referring to fig. 1 and fig. 4, in a further implementation manner of an embodiment, the first interface 101 and the second interface 102 are disposed on the motherboard 100 in a stacked manner.
Specifically, when the first interface 101 and the second interface 102 are applied, the packages of the two interfaces can be packaged with the same type of specification, and the main board 100 end can superimpose the interfaces with pclbayout, so as to reduce the PCB area and the material cost of the main board 100.
In summary, the liquid crystal display device provided by the utility model has the following beneficial effects:
the utility model is used as a brand new multifunctional interface definition, can be combined with a screen manufacturer for design, and becomes a new unified standard in industry;
the new interface definition is compatible with all data transmission signal pairs, demura functions and I2C regulation required BY the existing screen drive, can be completely adaptive to 4K ultra-high definition liquid crystal display screens of different manufacturers at home and abroad, can support the 4K ultra-high definition liquid crystal display screens of 43-75 inches of the main current manufacturers at home and abroad, can be matched with software setting, can convert data into the data transmission of the existing V-BY-ONE interface, and uses main board signal detection;
the design of the utility model solves the problem of display compatibility of the main board driven by different display screens, and an interface circuit is not required to be changed when the screen is selected and matched. The practical application circuit design is flexible, 68pin or 60pin interfaces can be selected according to different screen requirements, and the 68pin+60pin interfaces can be placed on PCLAyout in a compatible mode, so that the circuit design area and the material cost are saved, and the circuit design method is applicable to any conventional Tconless adapter plate display screen circuit scheme, for example, screen display driving of intelligent television products.
It is to be understood that the utility model is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.
Claims (7)
1. A liquid crystal display device, comprising: the device comprises a main board, a logic adapter board connected with the main board and a liquid crystal display connected with the logic adapter board; wherein,
the main board comprises a first interface and a second interface;
the logic adapter plate is provided with a third interface, a fourth interface and a fifth interface;
the logic adapter board is connected with the first interface or the second interface through the third interface so as to be connected with the main board, and is connected with the liquid crystal display through the fourth interface and the fifth interface;
the first interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area, a display data area and a data communication area;
the second interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area and a display data area;
the first to eighth pins of the first interface are defined as VCC; the ninth pin of the first interface is defined as NC; the tenth pin to the twelfth pin of the first interface are defined as GND; the thirteenth pin and the fourteenth pin of the first interface are respectively defined as P_SDA and P_SCL; the fifteenth pin and the sixteen pins of the first interface are respectively defined as TEST_IO and VB1_HPN; the seventeenth pin of the first interface is defined as a Panal_EN, and the eighteenth pin to twenty-three pins of the first interface are respectively defined as TCON_Lc2, TCON_Lc1, TCON_CPV2, TCON_CPV1, TCON_STV2 and TCON_STV1; the twenty-fourth pin of the first interface is defined as LOCOUT; the second fifteen pins to sixty pins of the first interface are defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, data+, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+, GND, respectively; the sixty-eighth pin to sixty-eighth pin of the first interface are respectively defined as FLASH_WP, FLASH_DO, FLASH_CS, FLASH_ DI, GND, FLASH _CLK and GND;
the first to seventh pins of the second interface are defined as VCC; the eighth pin of the second interface is defined as NC; the ninth to eleventh pins of the second interface are defined as GND; the twelfth pin and the thirteenth pin of the second interface are respectively defined as P_SDA and P_SCL; the fourteenth pin and the fifteenth pin of the second interface are respectively defined as TEST_IO and VB1_HPN; the seventeenth pin to the twenty second pin of the second interface are respectively defined as TCON_Lc2, TCON_Lc1, TCON_CPV2, TCON_CPV1, TCON_STV2 and TCON_STV1; a twenty-third leg of the second interface is defined as LOCOKOUT; the twenty-fourth pin to the sixtieth pin of the second interface are defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, data+, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+ and GND, respectively;
the interface of the motherboard may select the first interface or the second interface, and the motherboard end may remain unchanged as long as different logic adapter boards are correspondingly replaced.
2. The liquid crystal display device according to claim 1, wherein a flexible flat cable is used between the third interface and the first interface or between the third interface and the second interface; and the liquid crystal display screen is connected with the fourth interface and the fifth interface by adopting a flexible flat cable.
3. The liquid crystal display device according to claim 1, wherein the main board further comprises: and the VBO interface is respectively connected with the first interface and the second interface.
4. The liquid crystal display device according to claim 1, wherein the main board further comprises: and the main chip is respectively connected with the first interface and the second interface.
5. The liquid crystal display device of claim 1, wherein the logic interposer further comprises: the display device comprises a power management unit, a display parameter unit and a power conversion unit, wherein the power management unit, the display parameter unit and the output end of the power conversion unit are connected with the liquid crystal display.
6. The liquid crystal display device according to claim 1, wherein the first interface and the second interface are disposed on the main board in a superimposed manner.
7. The liquid crystal display main board is characterized by comprising a first interface and a second interface, wherein the first interface and the second interface are overlapped on the liquid crystal display main board; wherein,
the logic adapter plate is connected with the liquid crystal display main board;
the logic adapter plate is provided with a third interface, a fourth interface and a fifth interface;
the logic adapter board is connected with the first interface or the second interface through the third interface so as to be connected with the main board, and is connected with the liquid crystal display through the fourth interface and the fifth interface;
the first interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area, a display data area and a data communication area;
the second interface is provided with a power supply area, a short circuit prevention area, a grounding area, a data burning area, an interface detection area, an enabling control area, a driving control area, a locking area and a display data area;
the first to eighth pins of the first interface are defined as VCC;
the ninth pin of the first interface is defined as NC; the tenth to twelfth pins of the first interface are defined as GND; the thirteenth pin and the fourteenth pin of the first interface are respectively defined as P_SDA and P_SCL; the fifteenth pin and the sixteenth pin of the first interface are respectively defined as test_io and VB1_HPN; the seventeenth pin of the first interface is defined as a Panal_EN, and the eighteenth pin to the twenty third pin of the first interface are respectively defined as TCON_Lc2, TCON_Lc1, TCON_CPV2, TCON_CPV1, TCON_STV2 and TCON_STV1; the twenty-fourth pin of the first interface is defined as LOCOUT;
the second fifteenth to sixtieth pins of the first interface are defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, data+, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+, GND, respectively; the sixty-eighth pins of the first interface are respectively defined as FLASH_WP, FLASH_DO, FLASH_CS, FLASH_ DI, GND, FLASH _CLK and GND;
the first to seventh pins of the second interface are defined as VCC; the eighth pin of the second interface is defined as NC; the ninth to eleventh pins of the second interface are defined as GND; the twelfth pin and the thirteenth pin of the second interface are respectively defined as P_SDA and P_SCL; the fourteenth pin and the fifteenth pin of the second interface are respectively defined as TEST_IO and VB1_HPN; the seventeenth pin to the twenty second pin of the second interface are respectively defined as TCON_Lc2, TCON_Lc1, TCON_CPV2, TCON_CPV1, TCON_STV2 and TCON_STV1; a twenty-third leg of the second interface is defined as LOCOKOUT; the twenty-fourth pin to the sixtieth pin of the second interface are defined as GND, DATA12-, DATA12+, GND, DATA11-, DATA12+, GND, DATA10-, DATA10+, GND, DATA9-, DATA9+, GND, DATA8-, DATA8+, GND, DATA7-, DATA8+, GND, DATA6-, DATA6+, GND, DATA5-, DATA5+, GND, DATA4-, DATA4+, GND, DATA3-, data+, GND, DATA2-, DATA2+, GND, DATA1-, DATA1+ and GND, respectively;
the interface of the liquid crystal display main board can select a first interface or a second interface, and the main board end can be kept unchanged as long as different logic adapter boards are correspondingly replaced.
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