CN201429969Y - Main board interface circuit and television with the circuit - Google Patents
Main board interface circuit and television with the circuit Download PDFInfo
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- CN201429969Y CN201429969Y CN2009201639233U CN200920163923U CN201429969Y CN 201429969 Y CN201429969 Y CN 201429969Y CN 2009201639233 U CN2009201639233 U CN 2009201639233U CN 200920163923 U CN200920163923 U CN 200920163923U CN 201429969 Y CN201429969 Y CN 201429969Y
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Abstract
The utility model discloses a main board interface circuit and a television with the circuit, and relates to the technical field of interface circuits. The main board interface and the television aredesigned for solving the problems in the prior art that television main board interface circuits are complicated and various, the debugging is trivial, and the design cost is high. The main board interface circuit provided by the utility model comprises a liquid crystal screen control interface, a power supply interface, an earthing interface and an LVDS signal interface, wherein the liquid crystal screen control interface is used to interchange information with liquid crystal screen and the main board. Liquid crystal display screens of various types can be connected through adopting the mainboard interface circuit and the television, thereby lowering the debugging process and lowering the design cost.
Description
Technical field
The utility model relates to a kind of interface circuit, relates in particular to a kind of mainboard interface circuit and has the televisor of this circuit.
Background technology
At present, the 120HZ LCD Interface that different manufacturers is produced is inequality, and control mode is also inequality.For example: what the CMO screen used is GPIO (General Purpose Input Output, general I/O) mouthful of control 120HZ module; What the LG screen used is I2C (Inter-Integrated Circuit, twin wire universal serial bus) interface control 120HZ module.Do not need described interface for common 60HZ screen, but need other interface of control flow, for example: LVDS form base pin selection, dynamic backlight control pin.
In realizing process of the present utility model, the designer finds to have following problem in the prior art at least: in the prior art, because the liquid crystal display that present each producer is produced is used to control the interface difference of 120HZ module, make that TV motherboard interface circuit complexity is various, debug loaded down with trivial detailsly, design cost is higher.
The utility model content
In order to solve in the prior art because TV motherboard interface circuit complexity is various, debug loaded down with trivial details, the design cost problem of higher, the utility model provides a kind of mainboard interface circuit and has had the televisor of this circuit.
A kind of mainboard interface circuit that the utility model provides, this circuit comprises: liquid crystal display control interface, power supply interface, ground connection interface and LVDS signaling interface; Wherein, described LCD Interface is used for liquid crystal display and mainboard carries out information interaction.
Further, described liquid crystal display control interface further comprises: SEL pin, AI pin, BRI_OUT pin, BRI_EXT pin, GVMODSEL pin, 8/10BITSEL pin; Wherein,
Described SEL pin is used for controlling the SDA data-signal of LVDS model selection or I2C bus;
Described AI pin is used for that the automatic backlight adjustment enables to control or the GPIO_1 of the liquid crystal display two of 120HZ;
Described BRI_EXT pin is used to control the GPIO_3 of the liquid crystal display two of 120HZ;
Described GVMODSEL pin is used to control the GPIO_4 of liquid crystal display two of 120HZ or figure/image model of liquid crystal display two is selected;
Described 8/10BITSEL pin is used to control liquid crystal display 8/10BIT and selects.
Further, when liquid crystal display be liquid crystal display for the moment, described SEL pin is by first resistance and second resistance eutral grounding or meet DV33; Described AI pin is by the 3rd resistance and the 4th resistance eutral grounding or meet DV33; Described BRI_OUT pin, BRI_EXT pin are unsettled; Described GVMODSEL pin is by the 5th resistance eutral grounding or meet DV33; Described 8/10BITSEL pin is by the 6th resistance eutral grounding or meet DV33.
Further, when liquid crystal display was liquid crystal display two, described SEL pin was by the 7th resistance and the 8th resistance eutral grounding or meet DV33; Described AI pin meets GPIO_1; Described BRI_OUT pin meets GPIO_2, the BRI_EXT pin meets GPIO_3; Described GVMODSEL pin is by the 9th resistance eutral grounding or meet DV33; Described 8/10BITSEL pin is by the tenth resistance eutral grounding or meet DV33.
A kind of televisor that the utility model provides, this televisor comprises: described mainboard interface circuit; This circuit further comprises: liquid crystal display control interface, power supply interface, ground connection interface and LVDS signaling interface; Wherein, described LCD Interface is used for liquid crystal display and mainboard carries out information interaction.
Further, described LCD Interface further comprises: SEL pin, AI pin, BRI_OUT pin, BRI_EXT pin, GVMODSEL pin, 8/10BITSEL pin; Wherein,
Described SEL pin is used for controlling the SDA data-signal of LVDS model selection or I2C bus;
Described AI pin is used for that the automatic backlight adjustment enables to control or the GPIO_1 of the liquid crystal display two of 120HZ;
Described BRI_EXT pin is used to control the GPIO_3 of the liquid crystal display two of 120HZ;
Described GVMODSEL pin is used to control the GPIO_4 of liquid crystal display two of 120HZ or figure/image model of liquid crystal display two is selected;
Described 8/10BITSEL pin is used to control liquid crystal display 8/10BIT and selects.
Further, when liquid crystal display be liquid crystal display for the moment, described SEL pin is by first resistance and second resistance eutral grounding or meet DV33; Described AI pin is by the 3rd resistance and the 4th resistance eutral grounding or meet DV33; Described BRI_OUT pin, BRI_EXT pin are unsettled; Described GVMODSEL pin is by the 5th resistance eutral grounding or meet DV33; Described 8/10BITSEL pin is by the 6th resistance eutral grounding or meet DV33.
Further, when liquid crystal display was liquid crystal display two, described SEL pin was by the 7th resistance and the 8th resistance eutral grounding or meet DV33; Described AI pin meets GPIO_1; Described BRI_OUT pin meets GPIO_2, the BRI_EXT pin meets GPIO_3; Described GVMODSEL pin is by the 9th resistance eutral grounding or meet DV33; Described 8/10BITSEL pin is by the tenth resistance eutral grounding or meet DV33.
The mainboard interface circuit that the utility model provides and have the televisor of this circuit is by being provided with liquid crystal display control interface, power supply interface, ground connection interface and LVDS signaling interface; Wherein, described LCD Interface pin liquid crystal display control interface is used for liquid crystal display and mainboard carries out information interaction; This liquid crystal display can carry out different circuit connections according to the dissimilar of screen, inserts mainboard thereby can adapt to the plurality of liquid crystals screen, and compared with prior art, the utility model has been simplified the debug process of mainboard, has reduced the design cost of mainboard.
Description of drawings
A kind of mainboard interface embodiment of circuit structural representation that Fig. 1 provides for the utility model;
A kind of mainboard interface circuit that Fig. 2 (a) provides for the utility model is used to connect LG when screen and is the effective embodiment circuit diagram of low level;
A kind of mainboard interface circuit that Fig. 2 (b) provides for the utility model is used to connect LG when screen and is the effective embodiment circuit diagram of high level;
A kind of mainboard interface circuit that Fig. 3 (a) provides for the utility model is used to connect CMO when screen and is the effective embodiment circuit diagram of low level;
A kind of mainboard interface circuit that Fig. 3 (b) provides for the utility model is used to connect CMO when screen and is the effective embodiment circuit diagram of high level;
The example structure synoptic diagram of a kind of televisor that Fig. 4 provides for the utility model.
Embodiment
A kind of mainboard interface circuit that the utility model embodiment is provided below in conjunction with accompanying drawing and the televisor with this circuit are described in detail.
As shown in Figure 1, be a kind of mainboard interface circuit that the utility model embodiment provides, this circuit comprises: liquid crystal display control interface, power supply interface, ground connection interface and LVDS signaling interface; Wherein, described liquid crystal display control interface is used for liquid crystal display and mainboard carries out information interaction.
Wherein, described liquid crystal display control interface further comprises: SEL pin, AI pin, BRI_OUT pin, BRI_EXT pin, GVMODSEL pin, 8/10BITSEL pin; Wherein,
Described SEL pin is used for controlling the SDA data-signal of LVDS model selection or I2C bus;
Described AI pin is used for that the automatic backlight adjustment enables to control or the GPIO_1 of the liquid crystal display two of 120HZ;
Described BRI_EXT pin is used to control the GPIO_3 of the liquid crystal display two of 120HZ;
Described GVMODSEL pin is used to control the GPIO_4 of liquid crystal display two of 120HZ or figure/image model of liquid crystal display two is selected;
Described 8/10BITSEL pin is used to control liquid crystal display 8/10BIT and selects.
As shown in Figure 2, a kind of mainboard interface circuit for the utility model provides when this circuit is used to connect liquid crystal display one, when promptly LG shields, comprising: liquid crystal display control interface, power supply interface LVDSVDD, ground connection interface GND and LVDS signaling interface;
Wherein, described liquid crystal display control interface is used for liquid crystal display and mainboard carries out information interaction; It further comprises: SEL pin, AI pin, BRI_OUT pin, BRI_EXT pin, GVMODSEL pin, 8/10BITSEL pin; Described SEL pin is used to control the LVDS model selection; Described AI pin is used for the automatic backlight adjustment and enables control.
When described liquid crystal display control interface is low level when effective, shown in Fig. 2 (a) as described in the SEL pin by first resistance and second resistance eutral grounding; Described AI pin is by the 3rd resistance and the 4th resistance eutral grounding; Described BRI_OUT pin, BRI_EXT pin are unsettled; Described GVMODSEL pin is by the 5th resistance eutral grounding; Described 8/10BITSEL pin is by the 6th resistance eutral grounding.Wherein, described first resistance, second resistance, the 3rd resistance, the 4th resistance, the 5th resistance and the 6th resistance are 0 Europe resistance;
When described liquid crystal display control interface is high level when effective, shown in Fig. 2 (b) as described in the SEL pin meet DV33 by first resistance and second resistance; Described AI pin meets DV33 by the 3rd resistance and the 4th resistance; Described BRI_OUT pin, BRI_EXT pin are unsettled; Described GVMODSEL pin meets DV33 by the 5th resistance; Described 8/10BITSEL pin meets DV33 by the 6th resistance.Wherein, described first resistance and the 3rd resistance are 0 Europe resistance; Second resistance, the 4th resistance, the 5th resistance and the 6th resistance are 4.7 Europe resistance; DV33 is+3.3V voltage.
Need to prove that described LVDS signaling interface comprises following pin: A0P/A0N, AIP/AIN, A2P/A2N, A3P/A3N, A4P/A4N, A5P/A5N,, A6P/A6N, A7P/A7N, CLK1P/CLK1N, CLK2P/CLK2N.
As shown in Figure 3, a kind of mainboard interface circuit for the utility model provides when this circuit is used to connect liquid crystal display two, when promptly CMO shields, comprising: liquid crystal display control interface, power supply interface LVDSVDD, ground connection interface GND and LVDS signaling interface;
Wherein, described liquid crystal display control interface is used for liquid crystal display and mainboard carries out information interaction; It further comprises: SEL pin, AI pin, BRI_OUT pin, BRI_EXT pin, GVMODSEL pin, 8/10BITSEL pin; Described SEL pin is used for controlling the SDA data-signal of LVDS model selection or I2C bus; Described AI pin is used for the GPIO_1 of the liquid crystal display two of 120HZ; Described BRI_EXT pin is used to control the GPIO_3 of the liquid crystal display two of 120HZ; Described GVMODSEL pin is used to control the GPIO_4 of liquid crystal display two of 120HZ or figure/image model of liquid crystal display two is selected; Described 8/10BITSEL pin is used to control liquid crystal display 8/10BIT and selects.
When described liquid crystal display control interface is low level when effective, shown in Fig. 3 (a) as described in the SEL pin by the 7th resistance and the 8th resistance eutral grounding; Described AI pin meets GPIO_1; Described BRI_OUT pin meets GPIO_2, the BRI_EXT pin meets GPIO_3; Described GVMODSEL pin is by the 9th resistance eutral grounding; Described 8/10BITSEL pin meets DV33 by the tenth resistance.Wherein, described the 7th resistance, the 8th resistance and the 9th resistance are 0 Europe resistance, and described the tenth resistance is 4.7 Europe resistance, and DV33 is+3.3V voltage.
When described liquid crystal display control interface is high level when effective, shown in Fig. 3 (b) as described in the SEL pin meet DV33 by the 7th resistance and the 8th resistance; Described AI pin meets GPIO_1; Described BRI_OUT pin meets GPIO_2, the BRI_EXT pin meets GPIO_3; Described GVMODSEL pin meets DV33 by the 9th resistance; Described 8/10BITSEL pin meets DV33 by the tenth resistance.Wherein, described the 7th resistance is 0 Europe resistance, and described the 8th resistance, the 9th resistance and the tenth resistance are 4.7 Europe resistance, and DV33 is+3.3V voltage.
Need to prove that described LVDS signaling interface comprises following pin: A0P/A0N, AIP/AIN, A2P/A2N, A3P/A3N, A4P/A4N, A5P/A5N,, A6P/A6N, A7P/A7N, CLK1P/CLK1N, CLK2P/CLK2N.
As shown in Figure 4, be a kind of televisor that the utility model provides, this televisor comprises: described mainboard interface circuit; This circuit further comprises: liquid crystal display control interface, power supply interface, ground connection interface and LVDS signaling interface; Wherein, described liquid crystal display control interface is used for liquid crystal display and mainboard carries out information interaction.
Further, described liquid crystal display control interface further comprises: SEL pin, AI pin, BRI_OUT pin, BRI_EXT pin, GVMODSEL pin, 8/10BITSEL pin; Wherein,
Described SEL pin is used for controlling the SDA data-signal of LVDS model selection or I2C bus;
Described AI pin is used for that the automatic backlight adjustment enables to control or the GPIO_1 of the liquid crystal display two of 120HZ;
Described BRI_EXT pin is used to control the GPIO_3 of the liquid crystal display two of 120HZ;
Described GVMODSEL pin is used to control the GPIO_4 of liquid crystal display two of 120HZ or figure/image model of liquid crystal display two is selected;
Described 8/10BITSEL pin is used to control liquid crystal display 8/10BIT and selects.
Further, when described liquid crystal display is a liquid crystal display one, promptly during the LG screen, described SEL pin is by first resistance and second resistance eutral grounding or meet DV33; Described AI pin is by the 3rd resistance and the 4th resistance eutral grounding or meet DV33; Described BRI_OUT pin, BRI_EXT pin are unsettled; Described GVMODSEL pin is by the 5th resistance eutral grounding or meet DV33; Described 8/10BITSEL pin is by the 6th resistance eutral grounding or meet DV33.
Further, when described liquid crystal display is a liquid crystal display two, promptly during the CMO screen, described SEL pin is by the 7th resistance and the 8th resistance eutral grounding or meet DV33; Described AI pin meets GPIO_1; Described BRI_OUT pin meets GPIO_2, the BRI_EXT pin meets GPIO_3; Described GVMODSEL pin is by the 9th resistance eutral grounding or meet DV33; Described 8/10BITSEL pin is by the tenth resistance eutral grounding or meet DV33.
The mainboard interface circuit that the utility model provides and have the televisor of this circuit is by being provided with liquid crystal display control interface, power supply interface, ground connection interface and LVDS signaling interface; Wherein, described LCD Interface is used for liquid crystal display and mainboard carries out information interaction; This liquid crystal display can carry out different circuit connections according to the dissimilar of screen, inserts mainboard thereby can adapt to the plurality of liquid crystals screen, and compared with prior art, the utility model has been simplified the debug process of mainboard, has reduced the design cost of mainboard.
The above; it only is embodiment of the present utility model; protection domain of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; can expect easily changing or replacing, all should be encompassed within the protection domain of the present utility model.
Claims (8)
1, a kind of mainboard interface circuit is characterized in that, comprising: liquid crystal display control interface, power supply interface, ground connection interface and LVDS signaling interface; Wherein, described liquid crystal display control interface is used for liquid crystal display and mainboard carries out information interaction.
2, mainboard interface circuit according to claim 1 is characterized in that, described liquid crystal display control interface further comprises: SEL pin, AI pin, BRI_OUT pin, BRI_EXT pin, GVMODSEL pin, 8/10BITSEL pin; Wherein,
Described SEL pin is used for controlling the SDA data-signal of LVDS model selection or I2C bus;
Described AI pin is used for that the automatic backlight adjustment enables to control or the GPIO_1 of the liquid crystal display two of 120HZ;
Described BRI_EXT pin is used to control the GPIO_3 of the liquid crystal display two of 120HZ;
Described GVMODSEL pin is used to control the GPIO_4 of liquid crystal display two of 120HZ or figure/image model of liquid crystal display two is selected;
Described 8/10BITSEL pin is used to control liquid crystal display 8/10BIT and selects.
3, mainboard interface circuit according to claim 2 is characterized in that, when liquid crystal display be liquid crystal display for the moment, described SEL pin is by first resistance and second resistance eutral grounding or meet DV33; Described AI pin is by the 3rd resistance and the 4th resistance eutral grounding or meet DV33; Described BRI_OUT pin, BRI_EXT pin are unsettled; Described GVMODSEL pin is by the 5th resistance eutral grounding or meet DV33; Described 8/10BITSEL pin is by the 6th resistance eutral grounding or meet DV33.
4, mainboard interface circuit according to claim 3 is characterized in that, when liquid crystal display was liquid crystal display two screens, described SEL pin was by the 7th resistance and the 8th resistance eutral grounding or meet DV33; Described AI pin meets GPIO_1; Described BRI_OUT pin meets GPIO_2, the BRI_EXT pin meets GPIO_3; Described GVMODSEL pin is by the 9th resistance eutral grounding or meet DV33; Described 8/10BITSEL pin is by the tenth resistance eutral grounding or meet DV33.
5, a kind of televisor is characterized in that, comprising: described mainboard interface circuit; This circuit further comprises: liquid crystal display control interface, power supply interface, ground connection interface and LVDS signaling interface; Wherein, described LCD Interface is used for liquid crystal display and mainboard carries out information interaction.
6, televisor according to claim 5 is characterized in that, described liquid crystal display control interface further comprises: SEL pin, AI pin, BRI_OUT pin, BRI_EXT pin, GVMODSEL pin, 8/10BITSEL pin; Wherein,
Described SEL pin is used for controlling the SDA data-signal of LVDS model selection or I2C bus;
Described AI pin is used for that the automatic backlight adjustment enables to control or the GPIO_1 of the liquid crystal display two of 120HZ;
Described BRI_EXT pin is used to control the GPIO_3 of the liquid crystal display two of 120HZ;
Described GVMODSEL pin is used to control the GPIO_4 of liquid crystal display two of 120HZ or figure/image model of liquid crystal display two is selected;
Described 8/10BITSEL pin is used to control liquid crystal display 8/10BIT and selects.
7, televisor according to claim 6 is characterized in that, when liquid crystal display be liquid crystal display for the moment, described SEL pin is by first resistance and second resistance eutral grounding or meet DV33; Described AI pin is by the 3rd resistance and the 4th resistance eutral grounding or meet DV33; Described BRI_OUT pin, BRI_EXT pin are unsettled; Described GVMODSEL pin is by the 5th resistance eutral grounding or meet DV33; Described 8/10BITSEL pin is by the 6th resistance eutral grounding or meet DV33.
8, televisor according to claim 7 is characterized in that, when liquid crystal display was liquid crystal display two, described SEL pin was by the 7th resistance and the 8th resistance eutral grounding or meet DV33; Described AI pin meets GPIO_1; Described BRI_OUT pin meets GPIO_2, the BRI_EXT pin meets GPIO_3; Described GVMODSEL pin is by the 9th resistance eutral grounding or meet DV33; Described 8/10BITSEL pin is by the tenth resistance eutral grounding or meet DV33.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009201639233U CN201429969Y (en) | 2009-07-09 | 2009-07-09 | Main board interface circuit and television with the circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009201639233U CN201429969Y (en) | 2009-07-09 | 2009-07-09 | Main board interface circuit and television with the circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201429969Y true CN201429969Y (en) | 2010-03-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009201639233U Expired - Fee Related CN201429969Y (en) | 2009-07-09 | 2009-07-09 | Main board interface circuit and television with the circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201429969Y (en) |
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2009
- 2009-07-09 CN CN2009201639233U patent/CN201429969Y/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100324 Termination date: 20130709 |