CN112181122B - Management device and method of digital power supply chip - Google Patents
Management device and method of digital power supply chip Download PDFInfo
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- CN112181122B CN112181122B CN202010857042.2A CN202010857042A CN112181122B CN 112181122 B CN112181122 B CN 112181122B CN 202010857042 A CN202010857042 A CN 202010857042A CN 112181122 B CN112181122 B CN 112181122B
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000007726 management method Methods 0.000 claims abstract description 41
- 238000001514 detection method Methods 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a management device and a management method of a digital power supply chip, and belongs to the technical field of electronic equipment. The management device of the digital power supply chip comprises a connector, a graphical user interface and a host; the connector is connected with the host through a USB, and the graphical user interface is connected with the connector through a PMBus; the connector is connected with the plurality of digital power chips through the PMBus, the external resistance of each digital power chip is obtained through the PMBus instruction, and the management address of each digital power chip is defined according to the external resistance; and the host and the graphical user interface uniformly manage the plurality of digital power supply chips through the PMBus instruction based on the management address. The technical problem that the applicability of the BMC control method is not strong is solved.
Description
Technical Field
The present invention relates to the field of electronic devices, and in particular, to a management apparatus and method for a digital power chip.
Background
With the continuous development of cloud computing technology and the gradual reduction of the cost of digital power chips, the use of digital power chips in server power supply design has become more and more frequent.
In the existing server, the motherboard of the server usually does not use only the products of one digital power chip manufacturer, each power chip manufacturer has its own Graphical User Interface (GUI), the User must own the connector (Dongle) of each manufacturer and the corresponding GUI software to control the chip, and the GUI communication modes of each manufacturer are not all the same; on the other hand, the motherboard of the server does not include any BMC chip, or the motherboard has an extended interface but does not have Data and clock (Clk) signals connected to the Power Management Bus (PMBus), so that the current status of the digital Power chip cannot be confirmed through the BMC.
In practical application, operating personnel need be according to the frequent change connecting device of different firm chips and software, and the loss in man-hour can be brought in the process of changing, and the operating condition and the parameter of chip can't in time be confirmed to the more of chip kind moreover, can bring certain influence for the management and control of server power chip, lead to the technical problem that work efficiency is low. Since the BMC chip does not fully cover all servers, the method for acquiring and managing the chip by using the BMC chip cannot be widely popularized, which results in a technical problem that the method is not strong in applicability.
Disclosure of Invention
The invention aims to provide a management device of a digital power chip and a management method of the digital power chip, and aims to solve the technical problems of low efficiency and poor applicability of the management method of the digital power chip in the prior art.
In a first aspect, the present invention provides a management device for a digital power chip, including a connector, a graphical user interface and a host;
the connector is connected with the host through a USB, and the graphical user interface is connected with the connector through a PMBus;
the connector is connected with the plurality of digital power chips through the PMBus, the external resistance of each digital power chip is obtained through the PMBus instruction, and the management address of each digital power chip is defined according to the external resistance;
and the host and the graphical user interface uniformly manage the plurality of digital power supply chips through the PMBus instruction based on the management address. ,
further, the connector includes an input USB interface and an integrated circuit bus interface connected to the digital power supply chip, wherein:
the USB interface is an input end and is connected with a host interface;
the integrated circuit Bus interface is an output end and is connected with a PM Bus interface.
Further, the pins of the integrated circuit bus include: the clock signal line SCL, the digital transmission signal line SDA and the GND are correspondingly connected with the GND on the digital power supply chip to be tested.
Further, the input end voltage is 5.0V, and the output end voltage is 3.3V.
Furthermore, the connector still includes the row needle, the input of row needle passes through the PMBus and connects the connector, a plurality of outputs of row needle connect a plurality of digital power supply chip through the PMBus respectively.
Furthermore, the structure of the pin header is a Single Row Pitch 2.54mm Dip Stright type.
In a second aspect, the present invention further provides a management method for a digital power chip, which is applied to the connection device for the digital power chip, and the method includes:
the connector acquires the external resistance of each digital power supply chip through a PMBus instruction;
defining a management address of each digital power supply chip according to the external resistor;
the host machine performs unified management on a plurality of digital power chips through a PMBus instruction based on the management address
Further, the step of performing unified management on the plurality of digital power chips through the PMBus instruction includes:
according to the output voltage of the digital power supply chip, the VID output voltage level is adjusted,
according to the output current of the digital power supply chip, the IOUT _ CAL _ OFFSET is corrected, and the OFFSET in current detection is eliminated, so that the error of a current detection circuit is minimized.
Further, the graphical user interface outputs digital signals of the relevant digital power supply chip, wherein the digital signals comprise voltage, current, power and temperature.
The invention can achieve the following beneficial effects: the management device of the digital power chip provided by the invention comprises a Dongle, a GUI (graphical user interface) and a host. The Dongle comprises two pairs of pin interfaces and a USB interface, when in use, the digital power chips on the server mainboard can be connected together through a unified PMbus, the external resistance of each digital power chip is obtained through a PMbus instruction, and the management address of each digital power chip is defined according to the external resistance. One pair of pins of the PMBus and the Dongle are connected together, so that the uniformity of a digital power supply signal is improved; connecting the GUI together through another pair of pins of the PMBus and the Dongle, and outputting the voltage, current, temperature and power working state of the digital power supply chip through the GUI; the USB interface is combined with a host of a computer, and a plurality of digital power supplies are uniformly managed through the host and a PMBus instruction. The address and the information of the digital power supply chip are uniformly controlled by utilizing PMBus and Dongle, and the connecting device and software do not need to be frequently replaced according to chips of different manufacturers, so that the technical problem of low working efficiency is caused. The digital power supply chip can be managed without popularization of a BMC chip, and the technical problem that the BMC management and control method is not strong in applicability is solved.
Accordingly, the management method of the digital power chip provided by the embodiment of the invention also has the technical effects.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic view of a connection device according to an embodiment of the present invention;
FIG. 2 is a block diagram of a connector according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of unified commands of a graphical user interface provided by an embodiment of the present invention;
fig. 4 is a flowchart of a digital power chip management method according to an embodiment of the present invention.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "comprising" and "having," and any variations thereof, as referred to in embodiments of the present invention, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The first embodiment is as follows:
the embodiment of the invention provides a management device of a digital power supply chip, which comprises a connector, a graphical user interface and a host, as shown in figure 1;
the connector is connected with the host through a USB, and the graphical user interface is connected with the connector through a PMBus;
the connector is connected with the plurality of digital power chips through PMBus, acquires the external resistance of each digital power chip through PMBus instructions, and defines the management address of each digital power chip according to the external resistance;
and the host and the graphical user interface uniformly manage the plurality of digital power supply chips through the PMBus instruction based on the management address.
The information of the digital power chips of different manufacturers is defined by dividing the voltage through the unified PMBus and the external resistor, connecting devices of different manufacturers do not need to be switched one by one, and the digital power chips can be managed and controlled under the condition that no BMC chip is needed.
Further, the connector includes an input USB interface and an integrated circuit bus interface connected to the digital power chip, as shown in fig. 2, wherein:
the USB interface is an input end and is connected with a host interface;
the integrated circuit Bus interface is an output end and is connected with a PM Bus interface.
The USB interface is used, so that the USB interface is conveniently connected with a host and issues instructions to the digital power supply chip; the integrated circuit bus interface is used as an output end, so that the integrated circuit bus interface is conveniently connected with a PMBus interface, and the uniformity of digital instructions is improved.
In one possible embodiment, as shown in fig. 2, the pins of the integrated circuit bus include: the clock signal line SCL, the digital transmission signal line SDA and the GND are correspondingly connected with the GND on the digital power supply chip to be tested.
The clock line signal SCL and the digital transmission signal line SDA can be connected with the PMBus through the digital signal transmission of the clock line signal SCL and the digital transmission signal line SDA connecting the host and the graphic display, and the connecting device is simplified.
Preferably, the input end voltage is 5.0V, the output end voltage is 3.3V, and the universal USB interface and the universal PMBus interface are suitable.
Furthermore, the connector still includes the row needle, the input of row needle passes through the PMBus and connects the connector, a plurality of outputs of row needle connect a plurality of digital power supply chip through the PMBus respectively.
The pin header is responsible for the task of current or signal transmission. The PMBus are matched for use, form board-to-line connection, and increase the uniformity of digital signals.
Furthermore, the structure of the pin header is a Single Row Pitch 2.54mm Dip Stright type.
Example two:
the invention also provides a management method of the digital power supply chip, which is applied to the connecting device of the digital power supply chip, and the method comprises the following steps:
s1: the connector acquires the external resistance of each digital power supply chip through a PMBus instruction;
s2: defining a management address of each digital power supply chip according to the external resistor;
s3: and the host machine performs unified management on the plurality of digital power chips through the PMBus instruction based on the management address.
Further, the step S3 may specifically include:
as shown in fig. 3, the step of performing unified management on a plurality of digital power chips through a PMBus instruction includes:
according to the output voltage of the digital power supply chip, the VID output voltage level is adjusted,
according to the output current of the digital power supply chip, the IOUT _ CAL _ OFFSET is corrected, and the OFFSET in current detection is eliminated, so that the error of a current detection circuit is minimized.
The host can more conveniently issue instructions and further control the digital power supply.
Further, the graphical user interface outputs digital signals of the relevant digital power supply chip, wherein the digital signals comprise voltage, current, power and temperature.
The working state of the digital power supply chip can be more intuitively seen from the screen through the graphical user interface.
The management method of the digital power chip provided by the embodiment of the invention has the same technical characteristics as the management device of the digital power chip provided by the embodiment, so that the same technical problems can be solved, and the same technical effects can be achieved.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships that the present product is conventionally placed in use, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Claims (9)
1. The management device of a digital power supply chip is characterized by comprising a connector, a graphical user interface and a host;
the connector is connected with the host through a USB, and the graphical user interface is connected with the connector through a PMBus;
the connector is connected with the plurality of digital power chips through the PMBus, the external resistance of each digital power chip is obtained through the PMBus instruction, and the management address of each digital power chip is defined according to the external resistance;
and the host and the graphical user interface uniformly manage the plurality of digital power supply chips through the PMBus instruction based on the management address.
2. The apparatus of claim 1, wherein the connector comprises an input USB interface and two pairs of integrated circuit bus interfaces for connecting to a digital power chip, wherein:
the USB interface is an input end and is connected with a host interface;
the integrated circuit Bus interface is an output end and is connected with a PM Bus interface.
3. The apparatus of claim 2, wherein the pins of the integrated circuit bus comprise: the clock signal line SCL, the digital transmission signal line SDA and the GND are correspondingly connected with the GND on the digital power supply chip to be tested.
4. The apparatus of claim 2, wherein the input voltage is 5.0V and the output voltage is 3.3V.
5. The apparatus of claim 1, wherein the connector further comprises a pin header, an input terminal of the pin header is connected to the connector through a PMBus, and a plurality of output terminals of the pin header are respectively connected to the plurality of digital power chips through the PMBus.
6. The device of claim 5, wherein the configuration of the pin header is a Single Row Pitch 2.54mm Dip Stright type.
7. A management method of a digital power supply chip, which is applied to the connection device of the digital power supply chip of any one of claims 1 to 6, the method comprising:
the connector acquires the external resistance of each digital power supply chip through a PMBus instruction;
defining a management address of each digital power supply chip according to the external resistor;
and the host and the graphical user interface uniformly manage the plurality of digital power supply chips through the PMBus instruction based on the management address.
8. The method of claim 7, wherein the step of uniformly managing the plurality of digital power chips via the PMBus command comprises:
according to the output voltage of the digital power supply chip, the VID output voltage level is adjusted,
according to the output current of the digital power supply chip, the IOUT _ CAL _ OFFSET is corrected, and the OFFSET in current detection is eliminated, so that the error of a current detection circuit is minimized.
9. The method of claim 7, wherein the graphical user interface outputs digital signals of an associated digital power chip, the digital signals including voltage, current, power, temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010857042.2A CN112181122B (en) | 2020-08-24 | 2020-08-24 | Management device and method of digital power supply chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010857042.2A CN112181122B (en) | 2020-08-24 | 2020-08-24 | Management device and method of digital power supply chip |
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| Publication Number | Publication Date |
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| CN112181122A CN112181122A (en) | 2021-01-05 |
| CN112181122B true CN112181122B (en) | 2022-06-03 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103792923A (en) * | 2014-02-14 | 2014-05-14 | 浪潮电子信息产业股份有限公司 | Method for detecting and controlling sets of power supplies of main board through digital chips |
| CN104767385B (en) * | 2015-04-13 | 2017-03-01 | 湖北三江航天万峰科技发展有限公司 | A kind of digital power based on PMBus bus |
| CN110989815A (en) * | 2019-12-09 | 2020-04-10 | 思尔芯(上海)信息科技有限公司 | Power supply monitoring method and system based on development board |
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